| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.481958 # Number of seconds simulated 4sim_ticks 481957625500 # Number of ticks simulated 5final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.481958 # Number of seconds simulated 4sim_ticks 481957625500 # Number of ticks simulated 5final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 86883 # Simulator instruction rate (inst/s) 8host_op_rate 160778 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50643012 # Simulator tick rate (ticks/s) 10host_mem_usage 314272 # Number of bytes of host memory used 11host_seconds 9516.76 # Real time elapsed on the host | 7host_inst_rate 134289 # Simulator instruction rate (inst/s) 8host_op_rate 248503 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 78275315 # Simulator tick rate (ticks/s) 10host_mem_usage 362988 # Number of bytes of host memory used 11host_seconds 6157.21 # Real time elapsed on the host |
| 12sim_insts 826847303 # Number of instructions simulated 13sim_ops 1530082520 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826847303 # Number of instructions simulated 13sim_ops 1530082520 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory --- 255 unchanged lines hidden (view full) --- 279system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) 281system.physmem_1.averagePower 689.434954 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states 283system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory --- 255 unchanged lines hidden (view full) --- 280system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) 282system.physmem_1.averagePower 689.434954 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states 284system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 286system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 287system.cpu.branchPred.lookups 297786504 # Number of BP lookups 288system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 0 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. 296system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. 297system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. 298system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. 299system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. 300system.cpu_clk_domain.clock 500 # Clock period in ticks | 289system.cpu.branchPred.lookups 297786504 # Number of BP lookups 290system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted 291system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect 292system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 0 # Number of BTB hits 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 295system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. 297system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. 298system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. 299system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. 300system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. 301system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. 302system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 301system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 304system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 305system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states 306system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 302system.cpu.workload.num_syscalls 551 # Number of system calls | 307system.cpu.workload.num_syscalls 551 # Number of system calls |
| 308system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states |
|
| 303system.cpu.numCycles 963915252 # number of cpu cycles simulated 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 306system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss 307system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed 308system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered 309system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken 310system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 589system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads 590system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes 591system.cpu.fp_regfile_reads 239177 # number of floating regfile reads 592system.cpu.fp_regfile_writes 8 # number of floating regfile writes 593system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads 594system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes 595system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads 596system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 309system.cpu.numCycles 963915252 # number of cpu cycles simulated 310system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 311system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 312system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss 313system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed 314system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered 315system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken 316system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 595system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads 596system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes 597system.cpu.fp_regfile_reads 239177 # number of floating regfile reads 598system.cpu.fp_regfile_writes 8 # number of floating regfile writes 599system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads 600system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes 601system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads 602system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 603system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 597system.cpu.dcache.tags.replacements 2545945 # number of replacements 598system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use 599system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. 600system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. 601system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. 602system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. 603system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor 604system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy 605system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy 606system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 607system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 608system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 609system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id 611system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 612system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses 613system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses | 604system.cpu.dcache.tags.replacements 2545945 # number of replacements 605system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use 606system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. 607system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. 608system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. 609system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. 610system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor 611system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy 612system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy 613system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 614system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 615system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 616system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id 617system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id 618system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 619system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses 620system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses |
| 621system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 614system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits 615system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits 616system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits 617system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits 618system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits 619system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits 620system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits 621system.cpu.dcache.overall_hits::total 421064470 # number of overall hits --- 80 unchanged lines hidden (view full) --- 702system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency 704system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency 706system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 707system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency 708system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency | 622system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits 623system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits 624system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits 625system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits 626system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits 627system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits 628system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits 629system.cpu.dcache.overall_hits::total 421064470 # number of overall hits --- 80 unchanged lines hidden (view full) --- 710system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency 711system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency 712system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency 713system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 715system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 717system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency |
| 718system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 710system.cpu.icache.tags.replacements 4014 # number of replacements 711system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use 712system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. 713system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. 714system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. 715system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 716system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor 717system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy 718system.cpu.icache.tags.occ_percent::total 0.529250 # Average percentage of cache occupancy 719system.cpu.icache.tags.occ_task_id_blocks::1024 1724 # Occupied blocks per task id 720system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 721system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 722system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 723system.cpu.icache.tags.age_task_id_blocks_1024::3 78 # Occupied blocks per task id 724system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id 725system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id 726system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses 727system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses | 719system.cpu.icache.tags.replacements 4014 # number of replacements 720system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use 721system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. 722system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. 723system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. 724system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 725system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor 726system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy 727system.cpu.icache.tags.occ_percent::total 0.529250 # Average percentage of cache occupancy 728system.cpu.icache.tags.occ_task_id_blocks::1024 1724 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 730system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 731system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 732system.cpu.icache.tags.age_task_id_blocks_1024::3 78 # Occupied blocks per task id 733system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id 734system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id 735system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses 736system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses |
| 737system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 728system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits 729system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits 730system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits 731system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits 732system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits 733system.cpu.icache.overall_hits::total 216344175 # number of overall hits 734system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses 735system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 794system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses 795system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 796system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency 797system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency 798system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 799system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency 800system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 801system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency | 738system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits 739system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits 740system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits 741system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits 742system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits 743system.cpu.icache.overall_hits::total 216344175 # number of overall hits 744system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses 745system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 804system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses 805system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 806system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency 807system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency 808system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 809system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency 810system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 811system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency |
| 812system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 802system.cpu.l2cache.tags.replacements 355161 # number of replacements 803system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. 807system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. 808system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 816system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id 819system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11314 # Occupied blocks per task id 820system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 # Occupied blocks per task id 821system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id 822system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses 823system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses | 813system.cpu.l2cache.tags.replacements 355161 # number of replacements 814system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use 815system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. 816system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. 817system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. 818system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. 819system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor 820system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 827system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 829system.cpu.l2cache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id 830system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11314 # Occupied blocks per task id 831system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 # Occupied blocks per task id 832system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id 833system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses 834system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses |
| 835system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
|
| 824system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits 825system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits 826system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits 827system.cpu.l2cache.WritebackClean_hits::total 3923 # number of WritebackClean hits 828system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits 829system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits 830system.cpu.l2cache.ReadExReq_hits::cpu.data 577397 # number of ReadExReq hits 831system.cpu.l2cache.ReadExReq_hits::total 577397 # number of ReadExReq hits --- 150 unchanged lines hidden (view full) --- 982system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 983system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency 984system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. 985system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. 986system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 987system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. 988system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 989system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 836system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits 837system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits 838system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits 839system.cpu.l2cache.WritebackClean_hits::total 3923 # number of WritebackClean hits 840system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits 841system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits 842system.cpu.l2cache.ReadExReq_hits::cpu.data 577397 # number of ReadExReq hits 843system.cpu.l2cache.ReadExReq_hits::total 577397 # number of ReadExReq hits --- 150 unchanged lines hidden (view full) --- 994system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 995system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency 996system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. 997system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. 998system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 999system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. 1000system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1001system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1002system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
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| 990system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution 991system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution 992system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution 993system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution 994system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution 995system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution 996system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution 997system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution --- 18 unchanged lines hidden (view full) --- 1016system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1017system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram 1018system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) 1019system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 1020system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) 1021system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1022system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) 1023system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | 1003system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution 1006system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution 1009system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution 1010system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution --- 18 unchanged lines hidden (view full) --- 1029system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1030system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram 1031system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) 1032system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 1033system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) 1034system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1035system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) 1036system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 1037system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states |
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| 1024system.membus.trans_dist::ReadResp 180179 # Transaction distribution 1025system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution 1026system.membus.trans_dist::CleanEvict 57436 # Transaction distribution 1027system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution 1028system.membus.trans_dist::ReadExReq 206676 # Transaction distribution 1029system.membus.trans_dist::ReadExResp 206676 # Transaction distribution 1030system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution 1031system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) --- 22 unchanged lines hidden --- | 1038system.membus.trans_dist::ReadResp 180179 # Transaction distribution 1039system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution 1040system.membus.trans_dist::CleanEvict 57436 # Transaction distribution 1041system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution 1042system.membus.trans_dist::ReadExReq 206676 # Transaction distribution 1043system.membus.trans_dist::ReadExResp 206676 # Transaction distribution 1044system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution 1045system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) --- 22 unchanged lines hidden --- |