| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.481958 # Number of seconds simulated 4sim_ticks 481957625500 # Number of ticks simulated 5final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.481958 # Number of seconds simulated 4sim_ticks 481957625500 # Number of ticks simulated 5final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 104668 # Simulator instruction rate (inst/s) 8host_op_rate 193689 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 61009723 # Simulator tick rate (ticks/s) 10host_mem_usage 318640 # Number of bytes of host memory used 11host_seconds 7899.69 # Real time elapsed on the host | 7host_inst_rate 100765 # Simulator instruction rate (inst/s) 8host_op_rate 186466 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58734658 # Simulator tick rate (ticks/s) 10host_mem_usage 318636 # Number of bytes of host memory used 11host_seconds 8205.68 # Real time elapsed on the host |
| 12sim_insts 826847303 # Number of instructions simulated 13sim_ops 1530082520 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory --- 640 unchanged lines hidden (view full) --- 660system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency 661system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency 662system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked 663system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked 664system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked 665system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked 666system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked 667system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked | 12sim_insts 826847303 # Number of instructions simulated 13sim_ops 1530082520 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory --- 640 unchanged lines hidden (view full) --- 660system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency 661system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency 662system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked 663system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked 664system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked 665system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked 666system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked 667system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked |
| 668system.cpu.dcache.fast_writes 0 # number of fast writes performed 669system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 670system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks 671system.cpu.dcache.writebacks::total 2337968 # number of writebacks 672system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits 673system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits 674system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits 675system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits 676system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits 677system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency 705system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency 707system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 709system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 711system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency | 668system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks 669system.cpu.dcache.writebacks::total 2337968 # number of writebacks 670system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits 671system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits 672system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits 673system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits 674system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits 675system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 702system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency 704system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency 706system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 707system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency 708system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency |
| 712system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 713system.cpu.icache.tags.replacements 4014 # number of replacements 714system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use 715system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. 716system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. 717system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. 718system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 719system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor 720system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 765system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency 767system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked 768system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 769system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked 770system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 771system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked 772system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 710system.cpu.icache.tags.replacements 4014 # number of replacements 711system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use 712system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. 713system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. 714system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. 715system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 716system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor 717system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 762system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency 763system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency 764system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked 765system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked 767system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 768system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked 769system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 773system.cpu.icache.fast_writes 0 # number of fast writes performed 774system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 775system.cpu.icache.writebacks::writebacks 4014 # number of writebacks 776system.cpu.icache.writebacks::total 4014 # number of writebacks 777system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits 778system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits 779system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits 780system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits 781system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits 782system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 799system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses 800system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 801system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency 803system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency 805system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency | 770system.cpu.icache.writebacks::writebacks 4014 # number of writebacks 771system.cpu.icache.writebacks::total 4014 # number of writebacks 772system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits 773system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits 774system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits 775system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits 776system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits 777system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 794system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses 795system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 796system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency 797system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency 798system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 799system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency 800system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 801system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency |
| 807system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 808system.cpu.l2cache.tags.replacements 355161 # number of replacements 809system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use 810system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. 811system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. 812system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. 813system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. 814system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 920system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946 # average overall miss latency 922system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 925system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 926system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 927system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 802system.cpu.l2cache.tags.replacements 355161 # number of replacements 803system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. 807system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. 808system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 914system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946 # average overall miss latency 916system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 917system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 918system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 919system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 920system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 921system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 928system.cpu.l2cache.fast_writes 0 # number of fast writes performed 929system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 930system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks 931system.cpu.l2cache.writebacks::total 294920 # number of writebacks 932system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses 933system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses 934system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1342 # number of UpgradeReq MSHR misses 935system.cpu.l2cache.UpgradeReq_mshr_misses::total 1342 # number of UpgradeReq MSHR misses 936system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206686 # number of ReadExReq MSHR misses 937system.cpu.l2cache.ReadExReq_mshr_misses::total 206686 # number of ReadExReq MSHR misses --- 46 unchanged lines hidden (view full) --- 984system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency 985system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency 986system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency 987system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 988system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency 989system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency 990system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 991system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency | 922system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks 923system.cpu.l2cache.writebacks::total 294920 # number of writebacks 924system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses 925system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses 926system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1342 # number of UpgradeReq MSHR misses 927system.cpu.l2cache.UpgradeReq_mshr_misses::total 1342 # number of UpgradeReq MSHR misses 928system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206686 # number of ReadExReq MSHR misses 929system.cpu.l2cache.ReadExReq_mshr_misses::total 206686 # number of ReadExReq MSHR misses --- 46 unchanged lines hidden (view full) --- 976system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency 977system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency 978system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency 979system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 980system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency 981system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency 982system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 983system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency |
| 992system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 993system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. 994system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. 995system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 996system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. 997system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 998system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 999system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution 1000system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution --- 62 unchanged lines hidden --- | 984system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. 985system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. 986system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 987system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. 988system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 989system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 990system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution 991system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution --- 62 unchanged lines hidden --- |