| stats.txt (11232:135c16fa409d) | stats.txt (11336:b318499f676c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.403750 # Number of seconds simulated 4sim_ticks 403750101500 # Number of ticks simulated 5final_tick 403750101500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.403427 # Number of seconds simulated 4sim_ticks 403427114500 # Number of ticks simulated 5final_tick 403427114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 79008 # Simulator instruction rate (inst/s) 8host_op_rate 146095 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38578288 # Simulator tick rate (ticks/s) 10host_mem_usage 372460 # Number of bytes of host memory used 11host_seconds 10465.73 # Real time elapsed on the host | 7host_inst_rate 97075 # Simulator instruction rate (inst/s) 8host_op_rate 179503 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47362243 # Simulator tick rate (ticks/s) 10host_mem_usage 432836 # Number of bytes of host memory used 11host_seconds 8517.91 # Real time elapsed on the host |
| 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24546112 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24709696 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 383533 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386089 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 405162 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 60795309 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 61200470 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 405162 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 405162 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 46787436 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 46787436 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 46787436 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 405162 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 60795309 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 107987906 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386089 # Number of read requests accepted 40system.physmem.writeReqs 295163 # Number of write requests accepted 41system.physmem.readBursts 386089 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24690880 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18889216 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24709696 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 163328 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24540032 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24703360 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 163328 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 163328 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2552 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 383438 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 385990 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 404851 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 60828911 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 61233762 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 404851 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 404851 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 46816645 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 46816645 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 46816645 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 404851 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 60828911 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 108050407 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 385990 # Number of read requests accepted 40system.physmem.writeReqs 295111 # Number of write requests accepted 41system.physmem.readBursts 385990 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24683712 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24703360 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 50system.physmem.neitherReadNorWriteReqs 250150 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24088 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26446 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24837 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24496 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23228 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23719 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24505 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24301 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23634 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23532 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24794 # Per bank write bursts 62system.physmem.perBankRdBursts::11 23986 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23318 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22932 # Per bank write bursts 65system.physmem.perBankRdBursts::14 24086 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23893 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18617 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19942 # Per bank write bursts 69system.physmem.perBankWrBursts::2 19199 # Per bank write bursts | 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24081 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26417 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24826 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24490 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23233 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23715 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24493 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24296 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23625 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23520 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24786 # Per bank write bursts 62system.physmem.perBankRdBursts::11 23961 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23329 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22937 # Per bank write bursts 65system.physmem.perBankRdBursts::14 24074 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23900 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18616 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19936 # Per bank write bursts 69system.physmem.perBankWrBursts::2 19195 # Per bank write bursts |
| 70system.physmem.perBankWrBursts::3 19026 # Per bank write bursts | 70system.physmem.perBankWrBursts::3 19026 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::4 18119 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18516 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19139 # Per bank write bursts | 71system.physmem.perBankWrBursts::4 18116 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18513 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19137 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 19093 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 19093 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::8 18647 # Per bank write bursts 76system.physmem.perBankWrBursts::9 17956 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18916 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17762 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17409 # Per bank write bursts 80system.physmem.perBankWrBursts::13 17014 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17906 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17883 # Per bank write bursts | 75system.physmem.perBankWrBursts::8 18645 # Per bank write bursts 76system.physmem.perBankWrBursts::9 17955 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18907 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17752 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17408 # Per bank write bursts 80system.physmem.perBankWrBursts::13 17006 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17895 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17879 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 403750059500 # Total gap between requests | 85system.physmem.totGap 403427072500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 386089 # Read request sizes (log2) | 92system.physmem.readPktSize::6 385990 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 295163 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 380878 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4562 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 295111 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 380786 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4546 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see | 102system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see | 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 6189 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6615 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16935 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17522 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17619 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17656 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6569 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16986 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17639 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17648 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17662 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::22 17655 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::22 17655 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::23 17709 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17672 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17720 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17697 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17763 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17761 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17932 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::23 17706 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17690 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17770 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17759 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17891 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17597 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17537 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see |
| 170system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see | 170system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see |
| 171system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see | 171system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see |
| 174system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see --- 6 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 174system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see --- 6 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 146856 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 296.750885 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 175.556415 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 322.540822 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54126 36.86% 36.86% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 39800 27.10% 63.96% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13820 9.41% 73.37% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7615 5.19% 78.55% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5593 3.81% 82.36% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 4060 2.76% 85.13% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 2963 2.02% 87.14% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2671 1.82% 88.96% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16208 11.04% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 146856 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17505 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.039017 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 217.962707 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17495 99.94% 99.94% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 146923 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 296.528440 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 175.268112 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 322.869611 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54238 36.92% 36.92% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 39906 27.16% 64.08% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13861 9.43% 73.51% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7527 5.12% 78.63% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5392 3.67% 82.30% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3977 2.71% 85.01% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3022 2.06% 87.07% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.98% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16198 11.02% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 146923 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.029360 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 217.887118 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 17505 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17505 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.860554 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.781765 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.832914 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17316 98.92% 98.92% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 135 0.77% 99.69% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 27 0.15% 99.85% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::36-39 3 0.02% 99.92% # Writes before turning the bus around for reads | 218system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.854915 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.776896 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.816664 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17316 98.91% 98.91% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 131 0.75% 99.66% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 34 0.19% 99.85% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads |
| 229system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads | 229system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads |
| 230system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads | 230system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads |
| 231system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads | 231system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads |
| 232system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads | 232system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads |
| 233system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads | 233system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads |
| 241system.physmem.wrPerTurnAround::total 17505 # Writes before turning the bus around for reads 242system.physmem.totQLat 4284897750 # Total ticks spent queuing 243system.physmem.totMemAccLat 11518554000 # Total ticks spent from burst creation until serviced by the DRAM 244system.physmem.totBusLat 1928975000 # Total ticks spent in databus transfers 245system.physmem.avgQLat 11106.67 # Average queueing delay per DRAM burst | 241system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads 242system.physmem.totQLat 4287997000 # Total ticks spent queuing 243system.physmem.totMemAccLat 11519553250 # Total ticks spent from burst creation until serviced by the DRAM 244system.physmem.totBusLat 1928415000 # Total ticks spent in databus transfers 245system.physmem.avgQLat 11117.93 # Average queueing delay per DRAM burst |
| 246system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 246system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 247system.physmem.avgMemAccLat 29856.67 # Average memory access latency per DRAM burst 248system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s 249system.physmem.avgWrBW 46.78 # Average achieved write bandwidth in MiByte/s 250system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s 251system.physmem.avgWrBWSys 46.79 # Average system write bandwidth in MiByte/s | 247system.physmem.avgMemAccLat 29867.93 # Average memory access latency per DRAM burst 248system.physmem.avgRdBW 61.19 # Average DRAM read bandwidth in MiByte/s 249system.physmem.avgWrBW 46.81 # Average achieved write bandwidth in MiByte/s 250system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s 251system.physmem.avgWrBWSys 46.82 # Average system write bandwidth in MiByte/s |
| 252system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 253system.physmem.busUtil 0.84 # Data bus utilization in percentage 254system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads 255system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes 256system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 252system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 253system.physmem.busUtil 0.84 # Data bus utilization in percentage 254system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads 255system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes 256system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 257system.physmem.avgWrQLen 20.88 # Average write queue length when enqueuing 258system.physmem.readRowHits 318212 # Number of row buffer hits during reads 259system.physmem.writeRowHits 215865 # Number of row buffer hits during writes | 257system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing 258system.physmem.readRowHits 318108 # Number of row buffer hits during reads 259system.physmem.writeRowHits 215717 # Number of row buffer hits during writes |
| 260system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads | 260system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads |
| 261system.physmem.writeRowHitRate 73.13 # Row buffer hit rate for writes 262system.physmem.avgGap 592658.90 # Average gap between requests 263system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined 264system.physmem_0.actEnergy 568406160 # Energy for activate commands per rank (pJ) 265system.physmem_0.preEnergy 310142250 # Energy for precharge commands per rank (pJ) 266system.physmem_0.readEnergy 1525828200 # Energy for read commands per rank (pJ) 267system.physmem_0.writeEnergy 982679040 # Energy for write commands per rank (pJ) 268system.physmem_0.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) 269system.physmem_0.actBackEnergy 62107024725 # Energy for active background per rank (pJ) 270system.physmem_0.preBackEnergy 187769234250 # Energy for precharge background per rank (pJ) 271system.physmem_0.totalEnergy 279634184865 # Total energy per rank (pJ) 272system.physmem_0.averagePower 692.595037 # Core power per rank (mW) 273system.physmem_0.memoryStateTime::IDLE 311821526250 # Time in different power states 274system.physmem_0.memoryStateTime::REF 13482040000 # Time in different power states | 261system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes 262system.physmem.avgGap 592316.08 # Average gap between requests 263system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined 264system.physmem_0.actEnergy 568655640 # Energy for activate commands per rank (pJ) 265system.physmem_0.preEnergy 310278375 # Energy for precharge commands per rank (pJ) 266system.physmem_0.readEnergy 1525157400 # Energy for read commands per rank (pJ) 267system.physmem_0.writeEnergy 982374480 # Energy for write commands per rank (pJ) 268system.physmem_0.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) 269system.physmem_0.actBackEnergy 62248054410 # Energy for active background per rank (pJ) 270system.physmem_0.preBackEnergy 187449302250 # Energy for precharge background per rank (pJ) 271system.physmem_0.totalEnergy 279433333275 # Total energy per rank (pJ) 272system.physmem_0.averagePower 692.658624 # Core power per rank (mW) 273system.physmem_0.memoryStateTime::IDLE 311288113000 # Time in different power states 274system.physmem_0.memoryStateTime::REF 13471120000 # Time in different power states |
| 275system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 275system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 276system.physmem_0.memoryStateTime::ACT 78445652750 # Time in different power states | 276system.physmem_0.memoryStateTime::ACT 78663487000 # Time in different power states |
| 277system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 277system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 278system.physmem_1.actEnergy 541726920 # Energy for activate commands per rank (pJ) 279system.physmem_1.preEnergy 295585125 # Energy for precharge commands per rank (pJ) 280system.physmem_1.readEnergy 1483162200 # Energy for read commands per rank (pJ) 281system.physmem_1.writeEnergy 929646720 # Energy for write commands per rank (pJ) 282system.physmem_1.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) 283system.physmem_1.actBackEnergy 60264291960 # Energy for active background per rank (pJ) 284system.physmem_1.preBackEnergy 189385666500 # Energy for precharge background per rank (pJ) 285system.physmem_1.totalEnergy 279270949665 # Total energy per rank (pJ) 286system.physmem_1.averagePower 691.695380 # Core power per rank (mW) 287system.physmem_1.memoryStateTime::IDLE 314524575500 # Time in different power states 288system.physmem_1.memoryStateTime::REF 13482040000 # Time in different power states | 278system.physmem_1.actEnergy 541689120 # Energy for activate commands per rank (pJ) 279system.physmem_1.preEnergy 295564500 # Energy for precharge commands per rank (pJ) 280system.physmem_1.readEnergy 1482585000 # Energy for read commands per rank (pJ) 281system.physmem_1.writeEnergy 929322720 # Energy for write commands per rank (pJ) 282system.physmem_1.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) 283system.physmem_1.actBackEnergy 60147053505 # Energy for active background per rank (pJ) 284system.physmem_1.preBackEnergy 189292285500 # Energy for precharge background per rank (pJ) 285system.physmem_1.totalEnergy 279038011065 # Total energy per rank (pJ) 286system.physmem_1.averagePower 691.678700 # Core power per rank (mW) 287system.physmem_1.memoryStateTime::IDLE 314369366250 # Time in different power states 288system.physmem_1.memoryStateTime::REF 13471120000 # Time in different power states |
| 289system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 289system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 290system.physmem_1.memoryStateTime::ACT 75741865750 # Time in different power states | 290system.physmem_1.memoryStateTime::ACT 75582067750 # Time in different power states |
| 291system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 291system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 292system.cpu.branchPred.lookups 219275491 # Number of BP lookups 293system.cpu.branchPred.condPredicted 219275491 # Number of conditional branches predicted 294system.cpu.branchPred.condIncorrect 8530842 # Number of conditional branches incorrect 295system.cpu.branchPred.BTBLookups 123996876 # Number of BTB lookups 296system.cpu.branchPred.BTBHits 121809369 # Number of BTB hits | 292system.cpu.branchPred.lookups 219277494 # Number of BP lookups 293system.cpu.branchPred.condPredicted 219277494 # Number of conditional branches predicted 294system.cpu.branchPred.condIncorrect 8530091 # Number of conditional branches incorrect 295system.cpu.branchPred.BTBLookups 124020025 # Number of BTB lookups 296system.cpu.branchPred.BTBHits 121811454 # Number of BTB hits |
| 297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 298system.cpu.branchPred.BTBHitPct 98.235837 # BTB Hit Percentage 299system.cpu.branchPred.usedRAS 27061771 # Number of times the RAS was used to get a target. 300system.cpu.branchPred.RASInCorrect 1406477 # Number of incorrect RAS predictions. | 298system.cpu.branchPred.BTBHitPct 98.219182 # BTB Hit Percentage 299system.cpu.branchPred.usedRAS 27064699 # Number of times the RAS was used to get a target. 300system.cpu.branchPred.RASInCorrect 1406143 # Number of incorrect RAS predictions. |
| 301system.cpu_clk_domain.clock 500 # Clock period in ticks 302system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 303system.cpu.workload.num_syscalls 551 # Number of system calls | 301system.cpu_clk_domain.clock 500 # Clock period in ticks 302system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 303system.cpu.workload.num_syscalls 551 # Number of system calls |
| 304system.cpu.numCycles 807500204 # number of cpu cycles simulated | 304system.cpu.numCycles 806854230 # number of cpu cycles simulated |
| 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 307system.cpu.fetch.icacheStallCycles 175896513 # Number of cycles fetch is stalled on an Icache miss 308system.cpu.fetch.Insts 1208663738 # Number of instructions fetch has processed 309system.cpu.fetch.Branches 219275491 # Number of branches that fetch encountered 310system.cpu.fetch.predictedBranches 148871140 # Number of branches that fetch has predicted taken 311system.cpu.fetch.Cycles 621734900 # Number of cycles fetch has run and was not squashing or blocked 312system.cpu.fetch.SquashCycles 17770351 # Number of cycles fetch has spent squashing 313system.cpu.fetch.TlbCycles 224 # Number of cycles fetch has spent waiting for tlb 314system.cpu.fetch.MiscStallCycles 92919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 315system.cpu.fetch.PendingTrapStallCycles 734617 # Number of stall cycles due to pending traps 316system.cpu.fetch.PendingQuiesceStallCycles 1497 # Number of stall cycles due to pending quiesce instructions 317system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR 318system.cpu.fetch.CacheLines 170765697 # Number of cache lines fetched 319system.cpu.fetch.IcacheSquashes 2319587 # Number of outstanding Icache misses that were squashed | 307system.cpu.fetch.icacheStallCycles 175890438 # Number of cycles fetch is stalled on an Icache miss 308system.cpu.fetch.Insts 1208681477 # Number of instructions fetch has processed 309system.cpu.fetch.Branches 219277494 # Number of branches that fetch encountered 310system.cpu.fetch.predictedBranches 148876153 # Number of branches that fetch has predicted taken 311system.cpu.fetch.Cycles 621110348 # Number of cycles fetch has run and was not squashing or blocked 312system.cpu.fetch.SquashCycles 17764353 # Number of cycles fetch has spent squashing 313system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb 314system.cpu.fetch.MiscStallCycles 91101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 315system.cpu.fetch.PendingTrapStallCycles 722324 # Number of stall cycles due to pending traps 316system.cpu.fetch.PendingQuiesceStallCycles 1300 # Number of stall cycles due to pending quiesce instructions 317system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 318system.cpu.fetch.CacheLines 170768195 # Number of cache lines fetched 319system.cpu.fetch.IcacheSquashes 2322348 # Number of outstanding Icache misses that were squashed |
| 320system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed | 320system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed |
| 321system.cpu.fetch.rateDist::samples 807345886 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::mean 2.785599 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) | 321system.cpu.fetch.rateDist::samples 806697934 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::mean 2.787860 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::stdev 3.367990 # Number of instructions fetched each cycle (Total) |
| 324system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 324system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 325system.cpu.fetch.rateDist::0 417315550 51.69% 51.69% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::1 32556197 4.03% 55.72% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::2 31914797 3.95% 59.68% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::3 32648264 4.04% 63.72% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::4 26601298 3.29% 67.01% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::5 26865092 3.33% 70.34% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::6 35140610 4.35% 74.69% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::7 31395380 3.89% 78.58% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::8 172908698 21.42% 100.00% # Number of instructions fetched each cycle (Total) | 325system.cpu.fetch.rateDist::0 416692027 51.65% 51.65% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::1 32514924 4.03% 55.68% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::2 31852485 3.95% 59.63% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::3 32737208 4.06% 63.69% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::4 26535487 3.29% 66.98% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::5 26940530 3.34% 70.32% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::6 35175393 4.36% 74.68% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::7 31366288 3.89% 78.57% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::8 172883592 21.43% 100.00% # Number of instructions fetched each cycle (Total) |
| 334system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 334system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 337system.cpu.fetch.rateDist::total 807345886 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.branchRate 0.271549 # Number of branch fetches per cycle 339system.cpu.fetch.rate 1.496797 # Number of inst fetches per cycle 340system.cpu.decode.IdleCycles 120455538 # Number of cycles decode is idle 341system.cpu.decode.BlockedCycles 370723147 # Number of cycles decode is blocked 342system.cpu.decode.RunCycles 225174137 # Number of cycles decode is running 343system.cpu.decode.UnblockCycles 82107889 # Number of cycles decode is unblocking 344system.cpu.decode.SquashCycles 8885175 # Number of cycles decode is squashing 345system.cpu.decode.DecodedInsts 2132090689 # Number of instructions handled by decode 346system.cpu.rename.SquashCycles 8885175 # Number of cycles rename is squashing 347system.cpu.rename.IdleCycles 152508786 # Number of cycles rename is idle 348system.cpu.rename.BlockCycles 150703188 # Number of cycles rename is blocking 349system.cpu.rename.serializeStallCycles 44276 # count of cycles rename stalled for serializing inst 350system.cpu.rename.RunCycles 271505228 # Number of cycles rename is running 351system.cpu.rename.UnblockCycles 223699233 # Number of cycles rename is unblocking 352system.cpu.rename.RenamedInsts 2088450374 # Number of instructions processed by rename 353system.cpu.rename.ROBFullEvents 134027 # Number of times rename has blocked due to ROB full 354system.cpu.rename.IQFullEvents 138145056 # Number of times rename has blocked due to IQ full 355system.cpu.rename.LQFullEvents 24847890 # Number of times rename has blocked due to LQ full 356system.cpu.rename.SQFullEvents 50675847 # Number of times rename has blocked due to SQ full 357system.cpu.rename.RenamedOperands 2190623948 # Number of destination operands rename has renamed 358system.cpu.rename.RenameLookups 5277971052 # Number of register rename lookups that rename has made 359system.cpu.rename.int_rename_lookups 3356955770 # Number of integer rename lookups 360system.cpu.rename.fp_rename_lookups 59583 # Number of floating rename lookups | 337system.cpu.fetch.rateDist::total 806697934 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.branchRate 0.271768 # Number of branch fetches per cycle 339system.cpu.fetch.rate 1.498017 # Number of inst fetches per cycle 340system.cpu.decode.IdleCycles 120436174 # Number of cycles decode is idle 341system.cpu.decode.BlockedCycles 370050155 # Number of cycles decode is blocked 342system.cpu.decode.RunCycles 225346926 # Number of cycles decode is running 343system.cpu.decode.UnblockCycles 81982503 # Number of cycles decode is unblocking 344system.cpu.decode.SquashCycles 8882176 # Number of cycles decode is squashing 345system.cpu.decode.DecodedInsts 2132175908 # Number of instructions handled by decode 346system.cpu.rename.SquashCycles 8882176 # Number of cycles rename is squashing 347system.cpu.rename.IdleCycles 152549485 # Number of cycles rename is idle 348system.cpu.rename.BlockCycles 150499256 # Number of cycles rename is blocking 349system.cpu.rename.serializeStallCycles 41235 # count of cycles rename stalled for serializing inst 350system.cpu.rename.RunCycles 271495233 # Number of cycles rename is running 351system.cpu.rename.UnblockCycles 223230549 # Number of cycles rename is unblocking 352system.cpu.rename.RenamedInsts 2088541699 # Number of instructions processed by rename 353system.cpu.rename.ROBFullEvents 133771 # Number of times rename has blocked due to ROB full 354system.cpu.rename.IQFullEvents 138231059 # Number of times rename has blocked due to IQ full 355system.cpu.rename.LQFullEvents 24777266 # Number of times rename has blocked due to LQ full 356system.cpu.rename.SQFullEvents 50120464 # Number of times rename has blocked due to SQ full 357system.cpu.rename.RenamedOperands 2190713921 # Number of destination operands rename has renamed 358system.cpu.rename.RenameLookups 5278163786 # Number of register rename lookups that rename has made 359system.cpu.rename.int_rename_lookups 3357090809 # Number of integer rename lookups 360system.cpu.rename.fp_rename_lookups 59859 # Number of floating rename lookups |
| 361system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed | 361system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed |
| 362system.cpu.rename.UndoneMaps 576583094 # Number of HB maps that are undone due to squashing 363system.cpu.rename.serializingInsts 3244 # count of serializing insts renamed 364system.cpu.rename.tempSerializingInsts 3058 # count of temporary serializing insts renamed 365system.cpu.rename.skidInsts 422095496 # count of insts added to the skid buffer 366system.cpu.memDep0.insertedLoads 507123971 # Number of loads inserted to the mem dependence unit. 367system.cpu.memDep0.insertedStores 200816092 # Number of stores inserted to the mem dependence unit. 368system.cpu.memDep0.conflictingLoads 229029695 # Number of conflicting loads. 369system.cpu.memDep0.conflictingStores 68201156 # Number of conflicting stores. 370system.cpu.iq.iqInstsAdded 2023089277 # Number of instructions added to the IQ (excludes non-spec) 371system.cpu.iq.iqNonSpecInstsAdded 22810 # Number of non-speculative instructions added to the IQ 372system.cpu.iq.iqInstsIssued 1789046992 # Number of instructions issued 373system.cpu.iq.iqSquashedInstsIssued 413186 # Number of squashed instructions issued 374system.cpu.iq.iqSquashedInstsExamined 494123386 # Number of squashed instructions iterated over during squash; mainly for profiling 375system.cpu.iq.iqSquashedOperandsExamined 832685562 # Number of squashed operands that are examined and possibly removed from graph 376system.cpu.iq.iqSquashedNonSpecRemoved 22258 # Number of squashed non-spec instructions that were removed 377system.cpu.iq.issued_per_cycle::samples 807345886 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::mean 2.215961 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::stdev 2.071124 # Number of insts issued each cycle | 362system.cpu.rename.UndoneMaps 576673067 # Number of HB maps that are undone due to squashing 363system.cpu.rename.serializingInsts 3285 # count of serializing insts renamed 364system.cpu.rename.tempSerializingInsts 3078 # count of temporary serializing insts renamed 365system.cpu.rename.skidInsts 422612041 # count of insts added to the skid buffer 366system.cpu.memDep0.insertedLoads 507148674 # Number of loads inserted to the mem dependence unit. 367system.cpu.memDep0.insertedStores 200824572 # Number of stores inserted to the mem dependence unit. 368system.cpu.memDep0.conflictingLoads 228968697 # Number of conflicting loads. 369system.cpu.memDep0.conflictingStores 68242516 # Number of conflicting stores. 370system.cpu.iq.iqInstsAdded 2023165492 # Number of instructions added to the IQ (excludes non-spec) 371system.cpu.iq.iqNonSpecInstsAdded 27791 # Number of non-speculative instructions added to the IQ 372system.cpu.iq.iqInstsIssued 1789027795 # Number of instructions issued 373system.cpu.iq.iqSquashedInstsIssued 414599 # Number of squashed instructions issued 374system.cpu.iq.iqSquashedInstsExamined 494204582 # Number of squashed instructions iterated over during squash; mainly for profiling 375system.cpu.iq.iqSquashedOperandsExamined 832990276 # Number of squashed operands that are examined and possibly removed from graph 376system.cpu.iq.iqSquashedNonSpecRemoved 27239 # Number of squashed non-spec instructions that were removed 377system.cpu.iq.issued_per_cycle::samples 806697934 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::mean 2.217717 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::stdev 2.070743 # Number of insts issued each cycle |
| 380system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 380system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 381system.cpu.iq.issued_per_cycle::0 238839063 29.58% 29.58% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::1 123555302 15.30% 44.89% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::2 118726852 14.71% 59.59% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::3 107721401 13.34% 72.94% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::4 89742056 11.12% 84.05% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::5 60203262 7.46% 91.51% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::6 42304747 5.24% 96.75% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::7 18964857 2.35% 99.10% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::8 7288346 0.90% 100.00% # Number of insts issued each cycle | 381system.cpu.iq.issued_per_cycle::0 238149356 29.52% 29.52% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::1 123576451 15.32% 44.84% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::2 118711028 14.72% 59.56% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::3 107747587 13.36% 72.91% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::4 89829016 11.14% 84.05% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::5 60156883 7.46% 91.51% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::6 42289548 5.24% 96.75% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::7 18955760 2.35% 99.10% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::8 7282305 0.90% 100.00% # Number of insts issued each cycle |
| 390system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 390system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 393system.cpu.iq.issued_per_cycle::total 807345886 # Number of insts issued each cycle | 393system.cpu.iq.issued_per_cycle::total 806697934 # Number of insts issued each cycle |
| 394system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 394system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 395system.cpu.iq.fu_full::IntAlu 11498108 42.65% 42.65% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntMult 0 0.00% 42.65% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntDiv 0 0.00% 42.65% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.65% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.65% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.65% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatMult 0 0.00% 42.65% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.65% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.65% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.65% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.65% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.65% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.65% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.65% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.65% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMult 0 0.00% 42.65% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.65% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShift 0 0.00% 42.65% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.65% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.65% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.65% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.65% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.65% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.65% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.65% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.65% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.65% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.65% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.65% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemRead 12352662 45.82% 88.47% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemWrite 3109525 11.53% 100.00% # attempts to use FU when none available | 395system.cpu.iq.fu_full::IntAlu 11505863 42.68% 42.68% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemRead 12343295 45.78% 88.46% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemWrite 3110421 11.54% 100.00% # attempts to use FU when none available |
| 426system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 427system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 426system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 427system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 428system.cpu.iq.FU_type_0::No_OpClass 2715586 0.15% 0.15% # Type of FU issued 429system.cpu.iq.FU_type_0::IntAlu 1183095329 66.13% 66.28% # Type of FU issued 430system.cpu.iq.FU_type_0::IntMult 369789 0.02% 66.30% # Type of FU issued 431system.cpu.iq.FU_type_0::IntDiv 3881135 0.22% 66.52% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.52% # Type of FU issued | 428system.cpu.iq.FU_type_0::No_OpClass 2715990 0.15% 0.15% # Type of FU issued 429system.cpu.iq.FU_type_0::IntAlu 1183116627 66.13% 66.28% # Type of FU issued 430system.cpu.iq.FU_type_0::IntMult 369664 0.02% 66.30% # Type of FU issued 431system.cpu.iq.FU_type_0::IntDiv 3881147 0.22% 66.52% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatAdd 118 0.00% 66.52% # Type of FU issued |
| 433system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued | 433system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued |
| 435system.cpu.iq.FU_type_0::FloatMult 62 0.00% 66.52% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatDiv 375 0.00% 66.52% # Type of FU issued | 435system.cpu.iq.FU_type_0::FloatMult 58 0.00% 66.52% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued |
| 437system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 450system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued | 437system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 450system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued |
| 458system.cpu.iq.FU_type_0::MemRead 428554849 23.95% 90.47% # Type of FU issued 459system.cpu.iq.FU_type_0::MemWrite 170429736 9.53% 100.00% # Type of FU issued | 458system.cpu.iq.FU_type_0::MemRead 428537576 23.95% 90.47% # Type of FU issued 459system.cpu.iq.FU_type_0::MemWrite 170406235 9.53% 100.00% # Type of FU issued |
| 460system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 460system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 462system.cpu.iq.FU_type_0::total 1789046992 # Type of FU issued 463system.cpu.iq.rate 2.215538 # Inst issue rate 464system.cpu.iq.fu_busy_cnt 26960295 # FU busy when requested 465system.cpu.iq.fu_busy_rate 0.015070 # FU busy rate (busy events/executed inst) 466system.cpu.iq.int_inst_queue_reads 4412783736 # Number of integer instruction queue reads 467system.cpu.iq.int_inst_queue_writes 2517485001 # Number of integer instruction queue writes 468system.cpu.iq.int_inst_queue_wakeup_accesses 1762397634 # Number of integer instruction queue wakeup accesses 469system.cpu.iq.fp_inst_queue_reads 29615 # Number of floating instruction queue reads 470system.cpu.iq.fp_inst_queue_writes 68960 # Number of floating instruction queue writes 471system.cpu.iq.fp_inst_queue_wakeup_accesses 5614 # Number of floating instruction queue wakeup accesses 472system.cpu.iq.int_alu_accesses 1813278705 # Number of integer alu accesses 473system.cpu.iq.fp_alu_accesses 12996 # Number of floating point alu accesses 474system.cpu.iew.lsq.thread0.forwLoads 186120882 # Number of loads that had data forwarded from stores | 462system.cpu.iq.FU_type_0::total 1789027795 # Type of FU issued 463system.cpu.iq.rate 2.217287 # Inst issue rate 464system.cpu.iq.fu_busy_cnt 26959579 # FU busy when requested 465system.cpu.iq.fu_busy_rate 0.015069 # FU busy rate (busy events/executed inst) 466system.cpu.iq.int_inst_queue_reads 4412098039 # Number of integer instruction queue reads 467system.cpu.iq.int_inst_queue_writes 2517646847 # Number of integer instruction queue writes 468system.cpu.iq.int_inst_queue_wakeup_accesses 1762392188 # Number of integer instruction queue wakeup accesses 469system.cpu.iq.fp_inst_queue_reads 29663 # Number of floating instruction queue reads 470system.cpu.iq.fp_inst_queue_writes 69110 # Number of floating instruction queue writes 471system.cpu.iq.fp_inst_queue_wakeup_accesses 5652 # Number of floating instruction queue wakeup accesses 472system.cpu.iq.int_alu_accesses 1813258358 # Number of integer alu accesses 473system.cpu.iq.fp_alu_accesses 13026 # Number of floating point alu accesses 474system.cpu.iew.lsq.thread0.forwLoads 185949248 # Number of loads that had data forwarded from stores |
| 475system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 475system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 476system.cpu.iew.lsq.thread0.squashedLoads 123024315 # Number of loads squashed 477system.cpu.iew.lsq.thread0.ignoredResponses 213288 # Number of memory responses ignored because the instruction is squashed 478system.cpu.iew.lsq.thread0.memOrderViolation 372216 # Number of memory ordering violations 479system.cpu.iew.lsq.thread0.squashedStores 51655906 # Number of stores squashed | 476system.cpu.iew.lsq.thread0.squashedLoads 123048931 # Number of loads squashed 477system.cpu.iew.lsq.thread0.ignoredResponses 213773 # Number of memory responses ignored because the instruction is squashed 478system.cpu.iew.lsq.thread0.memOrderViolation 371791 # Number of memory ordering violations 479system.cpu.iew.lsq.thread0.squashedStores 51664386 # Number of stores squashed |
| 480system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 481system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 480system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 481system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 482system.cpu.iew.lsq.thread0.rescheduledLoads 23026 # Number of loads that were rescheduled 483system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked | 482system.cpu.iew.lsq.thread0.rescheduledLoads 23126 # Number of loads that were rescheduled 483system.cpu.iew.lsq.thread0.cacheBlocked 1127 # Number of times an access to memory failed due to the cache being blocked |
| 484system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 484system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 485system.cpu.iew.iewSquashCycles 8885175 # Number of cycles IEW is squashing 486system.cpu.iew.iewBlockCycles 97857746 # Number of cycles IEW is blocking 487system.cpu.iew.iewUnblockCycles 6188485 # Number of cycles IEW is unblocking 488system.cpu.iew.iewDispatchedInsts 2023112087 # Number of instructions dispatched to IQ 489system.cpu.iew.iewDispSquashedInsts 370282 # Number of squashed instructions skipped by dispatch 490system.cpu.iew.iewDispLoadInsts 507126472 # Number of dispatched load instructions 491system.cpu.iew.iewDispStoreInsts 200816092 # Number of dispatched store instructions 492system.cpu.iew.iewDispNonSpecInsts 7124 # Number of dispatched non-speculative instructions 493system.cpu.iew.iewIQFullEvents 1833420 # Number of times the IQ has become full, causing a stall 494system.cpu.iew.iewLSQFullEvents 3447634 # Number of times the LSQ has become full, causing a stall 495system.cpu.iew.memOrderViolationEvents 372216 # Number of memory order violations 496system.cpu.iew.predictedTakenIncorrect 4845141 # Number of branches that were predicted taken incorrectly 497system.cpu.iew.predictedNotTakenIncorrect 4138975 # Number of branches that were predicted not taken incorrectly 498system.cpu.iew.branchMispredicts 8984116 # Number of branch mispredicts detected at execute 499system.cpu.iew.iewExecutedInsts 1770027933 # Number of executed instructions 500system.cpu.iew.iewExecLoadInsts 423156069 # Number of load instructions executed 501system.cpu.iew.iewExecSquashedInsts 19019059 # Number of squashed instructions skipped in execute | 485system.cpu.iew.iewSquashCycles 8882176 # Number of cycles IEW is squashing 486system.cpu.iew.iewBlockCycles 97661574 # Number of cycles IEW is blocking 487system.cpu.iew.iewUnblockCycles 6126306 # Number of cycles IEW is unblocking 488system.cpu.iew.iewDispatchedInsts 2023193283 # Number of instructions dispatched to IQ 489system.cpu.iew.iewDispSquashedInsts 371095 # Number of squashed instructions skipped by dispatch 490system.cpu.iew.iewDispLoadInsts 507151088 # Number of dispatched load instructions 491system.cpu.iew.iewDispStoreInsts 200824572 # Number of dispatched store instructions 492system.cpu.iew.iewDispNonSpecInsts 12039 # Number of dispatched non-speculative instructions 493system.cpu.iew.iewIQFullEvents 1828108 # Number of times the IQ has become full, causing a stall 494system.cpu.iew.iewLSQFullEvents 3395741 # Number of times the LSQ has become full, causing a stall 495system.cpu.iew.memOrderViolationEvents 371791 # Number of memory order violations 496system.cpu.iew.predictedTakenIncorrect 4845230 # Number of branches that were predicted taken incorrectly 497system.cpu.iew.predictedNotTakenIncorrect 4136012 # Number of branches that were predicted not taken incorrectly 498system.cpu.iew.branchMispredicts 8981242 # Number of branch mispredicts detected at execute 499system.cpu.iew.iewExecutedInsts 1770011750 # Number of executed instructions 500system.cpu.iew.iewExecLoadInsts 423132476 # Number of load instructions executed 501system.cpu.iew.iewExecSquashedInsts 19016045 # Number of squashed instructions skipped in execute |
| 502system.cpu.iew.exec_swp 0 # number of swp insts executed 503system.cpu.iew.exec_nop 0 # number of nop insts executed | 502system.cpu.iew.exec_swp 0 # number of swp insts executed 503system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 504system.cpu.iew.exec_refs 590393535 # number of memory reference insts executed 505system.cpu.iew.exec_branches 168976878 # Number of branches executed 506system.cpu.iew.exec_stores 167237466 # Number of stores executed 507system.cpu.iew.exec_rate 2.191985 # Inst execution rate 508system.cpu.iew.wb_sent 1766902573 # cumulative count of insts sent to commit 509system.cpu.iew.wb_count 1762403248 # cumulative count of insts written-back 510system.cpu.iew.wb_producers 1339734836 # num instructions producing a value 511system.cpu.iew.wb_consumers 2050019870 # num instructions consuming a value 512system.cpu.iew.wb_rate 2.182542 # insts written-back per cycle 513system.cpu.iew.wb_fanout 0.653523 # average fanout of values written-back 514system.cpu.commit.commitSquashedInsts 494186003 # The number of squashed insts skipped by commit | 504system.cpu.iew.exec_refs 590347878 # number of memory reference insts executed 505system.cpu.iew.exec_branches 168976982 # Number of branches executed 506system.cpu.iew.exec_stores 167215402 # Number of stores executed 507system.cpu.iew.exec_rate 2.193719 # Inst execution rate 508system.cpu.iew.wb_sent 1766881473 # cumulative count of insts sent to commit 509system.cpu.iew.wb_count 1762397840 # cumulative count of insts written-back 510system.cpu.iew.wb_producers 1339889750 # num instructions producing a value 511system.cpu.iew.wb_consumers 2050179516 # num instructions consuming a value 512system.cpu.iew.wb_rate 2.184283 # insts written-back per cycle 513system.cpu.iew.wb_fanout 0.653548 # average fanout of values written-back 514system.cpu.commit.commitSquashedInsts 494265381 # The number of squashed insts skipped by commit |
| 515system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 515system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 516system.cpu.commit.branchMispredicts 8613223 # The number of times a branch was mispredicted 517system.cpu.commit.committed_per_cycle::samples 740134628 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::mean 2.065825 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::stdev 2.576078 # Number of insts commited each cycle | 516system.cpu.commit.branchMispredicts 8610728 # The number of times a branch was mispredicted 517system.cpu.commit.committed_per_cycle::samples 739482483 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::mean 2.067647 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::stdev 2.576172 # Number of insts commited each cycle |
| 520system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 520system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 521system.cpu.commit.committed_per_cycle::0 276181742 37.32% 37.32% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::1 172028130 23.24% 60.56% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::2 55891908 7.55% 68.11% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::3 86294140 11.66% 79.77% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::4 25858762 3.49% 83.26% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::5 26505188 3.58% 86.84% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::6 9830635 1.33% 88.17% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::7 9003447 1.22% 89.39% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::8 78540676 10.61% 100.00% # Number of insts commited each cycle | 521system.cpu.commit.committed_per_cycle::0 275479046 37.25% 37.25% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::1 172073402 23.27% 60.52% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::2 55823940 7.55% 68.07% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::3 86367064 11.68% 79.75% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::4 25894199 3.50% 83.25% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::5 26482728 3.58% 86.83% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::6 9848964 1.33% 88.17% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::7 9023113 1.22% 89.39% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::8 78490027 10.61% 100.00% # Number of insts commited each cycle |
| 530system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 530system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 533system.cpu.commit.committed_per_cycle::total 740134628 # Number of insts commited each cycle | 533system.cpu.commit.committed_per_cycle::total 739482483 # Number of insts commited each cycle |
| 534system.cpu.commit.committedInsts 826877109 # Number of instructions committed 535system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 536system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 537system.cpu.commit.refs 533262343 # Number of memory references committed 538system.cpu.commit.loads 384102157 # Number of loads committed 539system.cpu.commit.membars 0 # Number of memory barriers committed 540system.cpu.commit.branches 149758583 # Number of branches committed 541system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 571system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 574system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 575system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 576system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction | 534system.cpu.commit.committedInsts 826877109 # Number of instructions committed 535system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 536system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 537system.cpu.commit.refs 533262343 # Number of memory references committed 538system.cpu.commit.loads 384102157 # Number of loads committed 539system.cpu.commit.membars 0 # Number of memory barriers committed 540system.cpu.commit.branches 149758583 # Number of branches committed 541system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 571system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 574system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 575system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 576system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction |
| 579system.cpu.commit.bw_lim_events 78540676 # number cycles where commit BW limit reached 580system.cpu.rob.rob_reads 2684768656 # The number of ROB reads 581system.cpu.rob.rob_writes 4113734804 # The number of ROB writes 582system.cpu.timesIdled 1976 # Number of times that the entire CPU went into an idle state and unscheduled itself 583system.cpu.idleCycles 154318 # Total number of cycles that the CPU has spent unscheduled due to idling | 579system.cpu.commit.bw_lim_events 78490027 # number cycles where commit BW limit reached 580system.cpu.rob.rob_reads 2684246538 # The number of ROB reads 581system.cpu.rob.rob_writes 4113897788 # The number of ROB writes 582system.cpu.timesIdled 1953 # Number of times that the entire CPU went into an idle state and unscheduled itself 583system.cpu.idleCycles 156296 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 584system.cpu.committedInsts 826877109 # Number of Instructions Simulated 585system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated | 584system.cpu.committedInsts 826877109 # Number of Instructions Simulated 585system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated |
| 586system.cpu.cpi 0.976566 # CPI: Cycles Per Instruction 587system.cpu.cpi_total 0.976566 # CPI: Total CPI of All Threads 588system.cpu.ipc 1.023996 # IPC: Instructions Per Cycle 589system.cpu.ipc_total 1.023996 # IPC: Total IPC of All Threads 590system.cpu.int_regfile_reads 2722734844 # number of integer regfile reads 591system.cpu.int_regfile_writes 1435842493 # number of integer regfile writes 592system.cpu.fp_regfile_reads 5827 # number of floating regfile reads 593system.cpu.fp_regfile_writes 544 # number of floating regfile writes 594system.cpu.cc_regfile_reads 596643147 # number of cc regfile reads 595system.cpu.cc_regfile_writes 405466657 # number of cc regfile writes 596system.cpu.misc_regfile_reads 971667313 # number of misc regfile reads | 586system.cpu.cpi 0.975785 # CPI: Cycles Per Instruction 587system.cpu.cpi_total 0.975785 # CPI: Total CPI of All Threads 588system.cpu.ipc 1.024816 # IPC: Instructions Per Cycle 589system.cpu.ipc_total 1.024816 # IPC: Total IPC of All Threads 590system.cpu.int_regfile_reads 2722631435 # number of integer regfile reads 591system.cpu.int_regfile_writes 1435841734 # number of integer regfile writes 592system.cpu.fp_regfile_reads 5845 # number of floating regfile reads 593system.cpu.fp_regfile_writes 533 # number of floating regfile writes 594system.cpu.cc_regfile_reads 596631944 # number of cc regfile reads 595system.cpu.cc_regfile_writes 405465564 # number of cc regfile writes 596system.cpu.misc_regfile_reads 971632310 # number of misc regfile reads |
| 597system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 597system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 598system.cpu.dcache.tags.replacements 2531012 # number of replacements 599system.cpu.dcache.tags.tagsinuse 4087.814248 # Cycle average of tags in use 600system.cpu.dcache.tags.total_refs 381842819 # Total number of references to valid blocks. 601system.cpu.dcache.tags.sampled_refs 2535108 # Sample count of references to valid blocks. 602system.cpu.dcache.tags.avg_refs 150.621914 # Average number of references to valid blocks. | 598system.cpu.dcache.tags.replacements 2530979 # number of replacements 599system.cpu.dcache.tags.tagsinuse 4087.807694 # Cycle average of tags in use 600system.cpu.dcache.tags.total_refs 381987598 # Total number of references to valid blocks. 601system.cpu.dcache.tags.sampled_refs 2535075 # Sample count of references to valid blocks. 602system.cpu.dcache.tags.avg_refs 150.680985 # Average number of references to valid blocks. |
| 603system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. | 603system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. |
| 604system.cpu.dcache.tags.occ_blocks::cpu.data 4087.814248 # Average occupied blocks per requestor 605system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy 606system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy | 604system.cpu.dcache.tags.occ_blocks::cpu.data 4087.807694 # Average occupied blocks per requestor 605system.cpu.dcache.tags.occ_percent::cpu.data 0.998000 # Average percentage of cache occupancy 606system.cpu.dcache.tags.occ_percent::total 0.998000 # Average percentage of cache occupancy |
| 607system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 608system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id | 607system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 608system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id |
| 609system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id | 609system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::2 866 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::3 3174 # Occupied blocks per task id |
| 612system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 612system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 613system.cpu.dcache.tags.tag_accesses 772778472 # Number of tag accesses 614system.cpu.dcache.tags.data_accesses 772778472 # Number of data accesses 615system.cpu.dcache.ReadReq_hits::cpu.data 233189012 # number of ReadReq hits 616system.cpu.dcache.ReadReq_hits::total 233189012 # number of ReadReq hits 617system.cpu.dcache.WriteReq_hits::cpu.data 148175395 # number of WriteReq hits 618system.cpu.dcache.WriteReq_hits::total 148175395 # number of WriteReq hits 619system.cpu.dcache.demand_hits::cpu.data 381364407 # number of demand (read+write) hits 620system.cpu.dcache.demand_hits::total 381364407 # number of demand (read+write) hits 621system.cpu.dcache.overall_hits::cpu.data 381364407 # number of overall hits 622system.cpu.dcache.overall_hits::total 381364407 # number of overall hits 623system.cpu.dcache.ReadReq_misses::cpu.data 2772468 # number of ReadReq misses 624system.cpu.dcache.ReadReq_misses::total 2772468 # number of ReadReq misses 625system.cpu.dcache.WriteReq_misses::cpu.data 984807 # number of WriteReq misses 626system.cpu.dcache.WriteReq_misses::total 984807 # number of WriteReq misses 627system.cpu.dcache.demand_misses::cpu.data 3757275 # number of demand (read+write) misses 628system.cpu.dcache.demand_misses::total 3757275 # number of demand (read+write) misses 629system.cpu.dcache.overall_misses::cpu.data 3757275 # number of overall misses 630system.cpu.dcache.overall_misses::total 3757275 # number of overall misses 631system.cpu.dcache.ReadReq_miss_latency::cpu.data 59137035000 # number of ReadReq miss cycles 632system.cpu.dcache.ReadReq_miss_latency::total 59137035000 # number of ReadReq miss cycles 633system.cpu.dcache.WriteReq_miss_latency::cpu.data 31243406496 # number of WriteReq miss cycles 634system.cpu.dcache.WriteReq_miss_latency::total 31243406496 # number of WriteReq miss cycles 635system.cpu.dcache.demand_miss_latency::cpu.data 90380441496 # number of demand (read+write) miss cycles 636system.cpu.dcache.demand_miss_latency::total 90380441496 # number of demand (read+write) miss cycles 637system.cpu.dcache.overall_miss_latency::cpu.data 90380441496 # number of overall miss cycles 638system.cpu.dcache.overall_miss_latency::total 90380441496 # number of overall miss cycles 639system.cpu.dcache.ReadReq_accesses::cpu.data 235961480 # number of ReadReq accesses(hits+misses) 640system.cpu.dcache.ReadReq_accesses::total 235961480 # number of ReadReq accesses(hits+misses) | 613system.cpu.dcache.tags.tag_accesses 773071261 # Number of tag accesses 614system.cpu.dcache.tags.data_accesses 773071261 # Number of data accesses 615system.cpu.dcache.ReadReq_hits::cpu.data 233342532 # number of ReadReq hits 616system.cpu.dcache.ReadReq_hits::total 233342532 # number of ReadReq hits 617system.cpu.dcache.WriteReq_hits::cpu.data 148176085 # number of WriteReq hits 618system.cpu.dcache.WriteReq_hits::total 148176085 # number of WriteReq hits 619system.cpu.dcache.demand_hits::cpu.data 381518617 # number of demand (read+write) hits 620system.cpu.dcache.demand_hits::total 381518617 # number of demand (read+write) hits 621system.cpu.dcache.overall_hits::cpu.data 381518617 # number of overall hits 622system.cpu.dcache.overall_hits::total 381518617 # number of overall hits 623system.cpu.dcache.ReadReq_misses::cpu.data 2765359 # number of ReadReq misses 624system.cpu.dcache.ReadReq_misses::total 2765359 # number of ReadReq misses 625system.cpu.dcache.WriteReq_misses::cpu.data 984117 # number of WriteReq misses 626system.cpu.dcache.WriteReq_misses::total 984117 # number of WriteReq misses 627system.cpu.dcache.demand_misses::cpu.data 3749476 # number of demand (read+write) misses 628system.cpu.dcache.demand_misses::total 3749476 # number of demand (read+write) misses 629system.cpu.dcache.overall_misses::cpu.data 3749476 # number of overall misses 630system.cpu.dcache.overall_misses::total 3749476 # number of overall misses 631system.cpu.dcache.ReadReq_miss_latency::cpu.data 58561335000 # number of ReadReq miss cycles 632system.cpu.dcache.ReadReq_miss_latency::total 58561335000 # number of ReadReq miss cycles 633system.cpu.dcache.WriteReq_miss_latency::cpu.data 30709347495 # number of WriteReq miss cycles 634system.cpu.dcache.WriteReq_miss_latency::total 30709347495 # number of WriteReq miss cycles 635system.cpu.dcache.demand_miss_latency::cpu.data 89270682495 # number of demand (read+write) miss cycles 636system.cpu.dcache.demand_miss_latency::total 89270682495 # number of demand (read+write) miss cycles 637system.cpu.dcache.overall_miss_latency::cpu.data 89270682495 # number of overall miss cycles 638system.cpu.dcache.overall_miss_latency::total 89270682495 # number of overall miss cycles 639system.cpu.dcache.ReadReq_accesses::cpu.data 236107891 # number of ReadReq accesses(hits+misses) 640system.cpu.dcache.ReadReq_accesses::total 236107891 # number of ReadReq accesses(hits+misses) |
| 641system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 642system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) | 641system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 642system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) |
| 643system.cpu.dcache.demand_accesses::cpu.data 385121682 # number of demand (read+write) accesses 644system.cpu.dcache.demand_accesses::total 385121682 # number of demand (read+write) accesses 645system.cpu.dcache.overall_accesses::cpu.data 385121682 # number of overall (read+write) accesses 646system.cpu.dcache.overall_accesses::total 385121682 # number of overall (read+write) accesses 647system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses 648system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses 649system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006602 # miss rate for WriteReq accesses 650system.cpu.dcache.WriteReq_miss_rate::total 0.006602 # miss rate for WriteReq accesses 651system.cpu.dcache.demand_miss_rate::cpu.data 0.009756 # miss rate for demand accesses 652system.cpu.dcache.demand_miss_rate::total 0.009756 # miss rate for demand accesses 653system.cpu.dcache.overall_miss_rate::cpu.data 0.009756 # miss rate for overall accesses 654system.cpu.dcache.overall_miss_rate::total 0.009756 # miss rate for overall accesses 655system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21330.105523 # average ReadReq miss latency 656system.cpu.dcache.ReadReq_avg_miss_latency::total 21330.105523 # average ReadReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31725.410660 # average WriteReq miss latency 658system.cpu.dcache.WriteReq_avg_miss_latency::total 31725.410660 # average WriteReq miss latency 659system.cpu.dcache.demand_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency 660system.cpu.dcache.demand_avg_miss_latency::total 24054.784783 # average overall miss latency 661system.cpu.dcache.overall_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::total 24054.784783 # average overall miss latency 663system.cpu.dcache.blocked_cycles::no_mshrs 9718 # number of cycles access was blocked 664system.cpu.dcache.blocked_cycles::no_targets 22 # number of cycles access was blocked 665system.cpu.dcache.blocked::no_mshrs 1069 # number of cycles access was blocked | 643system.cpu.dcache.demand_accesses::cpu.data 385268093 # number of demand (read+write) accesses 644system.cpu.dcache.demand_accesses::total 385268093 # number of demand (read+write) accesses 645system.cpu.dcache.overall_accesses::cpu.data 385268093 # number of overall (read+write) accesses 646system.cpu.dcache.overall_accesses::total 385268093 # number of overall (read+write) accesses 647system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011712 # miss rate for ReadReq accesses 648system.cpu.dcache.ReadReq_miss_rate::total 0.011712 # miss rate for ReadReq accesses 649system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006598 # miss rate for WriteReq accesses 650system.cpu.dcache.WriteReq_miss_rate::total 0.006598 # miss rate for WriteReq accesses 651system.cpu.dcache.demand_miss_rate::cpu.data 0.009732 # miss rate for demand accesses 652system.cpu.dcache.demand_miss_rate::total 0.009732 # miss rate for demand accesses 653system.cpu.dcache.overall_miss_rate::cpu.data 0.009732 # miss rate for overall accesses 654system.cpu.dcache.overall_miss_rate::total 0.009732 # miss rate for overall accesses 655system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21176.756797 # average ReadReq miss latency 656system.cpu.dcache.ReadReq_avg_miss_latency::total 21176.756797 # average ReadReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31204.976131 # average WriteReq miss latency 658system.cpu.dcache.WriteReq_avg_miss_latency::total 31204.976131 # average WriteReq miss latency 659system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency 660system.cpu.dcache.demand_avg_miss_latency::total 23808.842221 # average overall miss latency 661system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::total 23808.842221 # average overall miss latency 663system.cpu.dcache.blocked_cycles::no_mshrs 9995 # number of cycles access was blocked 664system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked 665system.cpu.dcache.blocked::no_mshrs 1075 # number of cycles access was blocked |
| 666system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked | 666system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| 667system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.090739 # average number of cycles each access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_targets 11 # average number of cycles each access was blocked | 667system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.297674 # average number of cycles each access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked |
| 669system.cpu.dcache.fast_writes 0 # number of fast writes performed 670system.cpu.dcache.cache_copies 0 # number of cache copies performed | 669system.cpu.dcache.fast_writes 0 # number of fast writes performed 670system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 671system.cpu.dcache.writebacks::writebacks 2330580 # number of writebacks 672system.cpu.dcache.writebacks::total 2330580 # number of writebacks 673system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007465 # number of ReadReq MSHR hits 674system.cpu.dcache.ReadReq_mshr_hits::total 1007465 # number of ReadReq MSHR hits 675system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19412 # number of WriteReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::total 19412 # number of WriteReq MSHR hits 677system.cpu.dcache.demand_mshr_hits::cpu.data 1026877 # number of demand (read+write) MSHR hits 678system.cpu.dcache.demand_mshr_hits::total 1026877 # number of demand (read+write) MSHR hits 679system.cpu.dcache.overall_mshr_hits::cpu.data 1026877 # number of overall MSHR hits 680system.cpu.dcache.overall_mshr_hits::total 1026877 # number of overall MSHR hits 681system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765003 # number of ReadReq MSHR misses 682system.cpu.dcache.ReadReq_mshr_misses::total 1765003 # number of ReadReq MSHR misses 683system.cpu.dcache.WriteReq_mshr_misses::cpu.data 965395 # number of WriteReq MSHR misses 684system.cpu.dcache.WriteReq_mshr_misses::total 965395 # number of WriteReq MSHR misses 685system.cpu.dcache.demand_mshr_misses::cpu.data 2730398 # number of demand (read+write) MSHR misses 686system.cpu.dcache.demand_mshr_misses::total 2730398 # number of demand (read+write) MSHR misses 687system.cpu.dcache.overall_mshr_misses::cpu.data 2730398 # number of overall MSHR misses 688system.cpu.dcache.overall_mshr_misses::total 2730398 # number of overall MSHR misses 689system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33567375500 # number of ReadReq MSHR miss cycles 690system.cpu.dcache.ReadReq_mshr_miss_latency::total 33567375500 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30021732998 # number of WriteReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::total 30021732998 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63589108498 # number of demand (read+write) MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::total 63589108498 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63589108498 # number of overall MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::total 63589108498 # number of overall MSHR miss cycles 697system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses 698system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006472 # mshr miss rate for WriteReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006472 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses 702system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses 703system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses 704system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses 705system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.310734 # average ReadReq mshr miss latency 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.310734 # average ReadReq mshr miss latency 707system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31097.874961 # average WriteReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31097.874961 # average WriteReq mshr miss latency 709system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency 711system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency | 671system.cpu.dcache.writebacks::writebacks 2330614 # number of writebacks 672system.cpu.dcache.writebacks::total 2330614 # number of writebacks 673system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000418 # number of ReadReq MSHR hits 674system.cpu.dcache.ReadReq_mshr_hits::total 1000418 # number of ReadReq MSHR hits 675system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19400 # number of WriteReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::total 19400 # number of WriteReq MSHR hits 677system.cpu.dcache.demand_mshr_hits::cpu.data 1019818 # number of demand (read+write) MSHR hits 678system.cpu.dcache.demand_mshr_hits::total 1019818 # number of demand (read+write) MSHR hits 679system.cpu.dcache.overall_mshr_hits::cpu.data 1019818 # number of overall MSHR hits 680system.cpu.dcache.overall_mshr_hits::total 1019818 # number of overall MSHR hits 681system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764941 # number of ReadReq MSHR misses 682system.cpu.dcache.ReadReq_mshr_misses::total 1764941 # number of ReadReq MSHR misses 683system.cpu.dcache.WriteReq_mshr_misses::cpu.data 964717 # number of WriteReq MSHR misses 684system.cpu.dcache.WriteReq_mshr_misses::total 964717 # number of WriteReq MSHR misses 685system.cpu.dcache.demand_mshr_misses::cpu.data 2729658 # number of demand (read+write) MSHR misses 686system.cpu.dcache.demand_mshr_misses::total 2729658 # number of demand (read+write) MSHR misses 687system.cpu.dcache.overall_mshr_misses::cpu.data 2729658 # number of overall MSHR misses 688system.cpu.dcache.overall_mshr_misses::total 2729658 # number of overall MSHR misses 689system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33563285500 # number of ReadReq MSHR miss cycles 690system.cpu.dcache.ReadReq_mshr_miss_latency::total 33563285500 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29489872497 # number of WriteReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::total 29489872497 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63053157997 # number of demand (read+write) MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::total 63053157997 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63053157997 # number of overall MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::total 63053157997 # number of overall MSHR miss cycles 697system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses 698system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007475 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006468 # mshr miss rate for WriteReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006468 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007085 # mshr miss rate for demand accesses 702system.cpu.dcache.demand_mshr_miss_rate::total 0.007085 # mshr miss rate for demand accesses 703system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007085 # mshr miss rate for overall accesses 704system.cpu.dcache.overall_mshr_miss_rate::total 0.007085 # mshr miss rate for overall accesses 705system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19016.661463 # average ReadReq mshr miss latency 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19016.661463 # average ReadReq mshr miss latency 707system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30568.417989 # average WriteReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30568.417989 # average WriteReq mshr miss latency 709system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23099.288628 # average overall mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::total 23099.288628 # average overall mshr miss latency 711system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23099.288628 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::total 23099.288628 # average overall mshr miss latency |
| 713system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 713system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 714system.cpu.icache.tags.replacements 6646 # number of replacements 715system.cpu.icache.tags.tagsinuse 1037.831951 # Cycle average of tags in use 716system.cpu.icache.tags.total_refs 170556730 # Total number of references to valid blocks. 717system.cpu.icache.tags.sampled_refs 8257 # Sample count of references to valid blocks. 718system.cpu.icache.tags.avg_refs 20656.016713 # Average number of references to valid blocks. | 714system.cpu.icache.tags.replacements 6598 # number of replacements 715system.cpu.icache.tags.tagsinuse 1037.931814 # Cycle average of tags in use 716system.cpu.icache.tags.total_refs 170560002 # Total number of references to valid blocks. 717system.cpu.icache.tags.sampled_refs 8206 # Sample count of references to valid blocks. 718system.cpu.icache.tags.avg_refs 20784.791860 # Average number of references to valid blocks. |
| 719system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 719system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 720system.cpu.icache.tags.occ_blocks::cpu.inst 1037.831951 # Average occupied blocks per requestor 721system.cpu.icache.tags.occ_percent::cpu.inst 0.506754 # Average percentage of cache occupancy 722system.cpu.icache.tags.occ_percent::total 0.506754 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id 724system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id | 720system.cpu.icache.tags.occ_blocks::cpu.inst 1037.931814 # Average occupied blocks per requestor 721system.cpu.icache.tags.occ_percent::cpu.inst 0.506803 # Average percentage of cache occupancy 722system.cpu.icache.tags.occ_percent::total 0.506803 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id 724system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id |
| 725system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id | 725system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id |
| 726system.cpu.icache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id 729system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id 730system.cpu.icache.tags.tag_accesses 341735047 # Number of tag accesses 731system.cpu.icache.tags.data_accesses 341735047 # Number of data accesses 732system.cpu.icache.ReadReq_hits::cpu.inst 170559843 # number of ReadReq hits 733system.cpu.icache.ReadReq_hits::total 170559843 # number of ReadReq hits 734system.cpu.icache.demand_hits::cpu.inst 170559843 # number of demand (read+write) hits 735system.cpu.icache.demand_hits::total 170559843 # number of demand (read+write) hits 736system.cpu.icache.overall_hits::cpu.inst 170559843 # number of overall hits 737system.cpu.icache.overall_hits::total 170559843 # number of overall hits 738system.cpu.icache.ReadReq_misses::cpu.inst 205853 # number of ReadReq misses 739system.cpu.icache.ReadReq_misses::total 205853 # number of ReadReq misses 740system.cpu.icache.demand_misses::cpu.inst 205853 # number of demand (read+write) misses 741system.cpu.icache.demand_misses::total 205853 # number of demand (read+write) misses 742system.cpu.icache.overall_misses::cpu.inst 205853 # number of overall misses 743system.cpu.icache.overall_misses::total 205853 # number of overall misses 744system.cpu.icache.ReadReq_miss_latency::cpu.inst 1200128500 # number of ReadReq miss cycles 745system.cpu.icache.ReadReq_miss_latency::total 1200128500 # number of ReadReq miss cycles 746system.cpu.icache.demand_miss_latency::cpu.inst 1200128500 # number of demand (read+write) miss cycles 747system.cpu.icache.demand_miss_latency::total 1200128500 # number of demand (read+write) miss cycles 748system.cpu.icache.overall_miss_latency::cpu.inst 1200128500 # number of overall miss cycles 749system.cpu.icache.overall_miss_latency::total 1200128500 # number of overall miss cycles 750system.cpu.icache.ReadReq_accesses::cpu.inst 170765696 # number of ReadReq accesses(hits+misses) 751system.cpu.icache.ReadReq_accesses::total 170765696 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.demand_accesses::cpu.inst 170765696 # number of demand (read+write) accesses 753system.cpu.icache.demand_accesses::total 170765696 # number of demand (read+write) accesses 754system.cpu.icache.overall_accesses::cpu.inst 170765696 # number of overall (read+write) accesses 755system.cpu.icache.overall_accesses::total 170765696 # number of overall (read+write) accesses 756system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001205 # miss rate for ReadReq accesses 757system.cpu.icache.ReadReq_miss_rate::total 0.001205 # miss rate for ReadReq accesses 758system.cpu.icache.demand_miss_rate::cpu.inst 0.001205 # miss rate for demand accesses 759system.cpu.icache.demand_miss_rate::total 0.001205 # miss rate for demand accesses 760system.cpu.icache.overall_miss_rate::cpu.inst 0.001205 # miss rate for overall accesses 761system.cpu.icache.overall_miss_rate::total 0.001205 # miss rate for overall accesses 762system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5830.026767 # average ReadReq miss latency 763system.cpu.icache.ReadReq_avg_miss_latency::total 5830.026767 # average ReadReq miss latency 764system.cpu.icache.demand_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency 765system.cpu.icache.demand_avg_miss_latency::total 5830.026767 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::total 5830.026767 # average overall miss latency 768system.cpu.icache.blocked_cycles::no_mshrs 1227 # number of cycles access was blocked | 726system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::3 316 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::4 1161 # Occupied blocks per task id 729system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id 730system.cpu.icache.tags.tag_accesses 341739287 # Number of tag accesses 731system.cpu.icache.tags.data_accesses 341739287 # Number of data accesses 732system.cpu.icache.ReadReq_hits::cpu.inst 170563080 # number of ReadReq hits 733system.cpu.icache.ReadReq_hits::total 170563080 # number of ReadReq hits 734system.cpu.icache.demand_hits::cpu.inst 170563080 # number of demand (read+write) hits 735system.cpu.icache.demand_hits::total 170563080 # number of demand (read+write) hits 736system.cpu.icache.overall_hits::cpu.inst 170563080 # number of overall hits 737system.cpu.icache.overall_hits::total 170563080 # number of overall hits 738system.cpu.icache.ReadReq_misses::cpu.inst 205114 # number of ReadReq misses 739system.cpu.icache.ReadReq_misses::total 205114 # number of ReadReq misses 740system.cpu.icache.demand_misses::cpu.inst 205114 # number of demand (read+write) misses 741system.cpu.icache.demand_misses::total 205114 # number of demand (read+write) misses 742system.cpu.icache.overall_misses::cpu.inst 205114 # number of overall misses 743system.cpu.icache.overall_misses::total 205114 # number of overall misses 744system.cpu.icache.ReadReq_miss_latency::cpu.inst 1195791500 # number of ReadReq miss cycles 745system.cpu.icache.ReadReq_miss_latency::total 1195791500 # number of ReadReq miss cycles 746system.cpu.icache.demand_miss_latency::cpu.inst 1195791500 # number of demand (read+write) miss cycles 747system.cpu.icache.demand_miss_latency::total 1195791500 # number of demand (read+write) miss cycles 748system.cpu.icache.overall_miss_latency::cpu.inst 1195791500 # number of overall miss cycles 749system.cpu.icache.overall_miss_latency::total 1195791500 # number of overall miss cycles 750system.cpu.icache.ReadReq_accesses::cpu.inst 170768194 # number of ReadReq accesses(hits+misses) 751system.cpu.icache.ReadReq_accesses::total 170768194 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.demand_accesses::cpu.inst 170768194 # number of demand (read+write) accesses 753system.cpu.icache.demand_accesses::total 170768194 # number of demand (read+write) accesses 754system.cpu.icache.overall_accesses::cpu.inst 170768194 # number of overall (read+write) accesses 755system.cpu.icache.overall_accesses::total 170768194 # number of overall (read+write) accesses 756system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001201 # miss rate for ReadReq accesses 757system.cpu.icache.ReadReq_miss_rate::total 0.001201 # miss rate for ReadReq accesses 758system.cpu.icache.demand_miss_rate::cpu.inst 0.001201 # miss rate for demand accesses 759system.cpu.icache.demand_miss_rate::total 0.001201 # miss rate for demand accesses 760system.cpu.icache.overall_miss_rate::cpu.inst 0.001201 # miss rate for overall accesses 761system.cpu.icache.overall_miss_rate::total 0.001201 # miss rate for overall accesses 762system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5829.887282 # average ReadReq miss latency 763system.cpu.icache.ReadReq_avg_miss_latency::total 5829.887282 # average ReadReq miss latency 764system.cpu.icache.demand_avg_miss_latency::cpu.inst 5829.887282 # average overall miss latency 765system.cpu.icache.demand_avg_miss_latency::total 5829.887282 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::cpu.inst 5829.887282 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::total 5829.887282 # average overall miss latency 768system.cpu.icache.blocked_cycles::no_mshrs 766 # number of cycles access was blocked |
| 769system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 769system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 770system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked | 770system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked |
| 771system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 771system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 772system.cpu.icache.avg_blocked_cycles::no_mshrs 94.384615 # average number of cycles each access was blocked | 772system.cpu.icache.avg_blocked_cycles::no_mshrs 76.600000 # average number of cycles each access was blocked |
| 773system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu.icache.fast_writes 0 # number of fast writes performed 775system.cpu.icache.cache_copies 0 # number of cache copies performed | 773system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu.icache.fast_writes 0 # number of fast writes performed 775system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 776system.cpu.icache.writebacks::writebacks 6646 # number of writebacks 777system.cpu.icache.writebacks::total 6646 # number of writebacks 778system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2196 # number of ReadReq MSHR hits 779system.cpu.icache.ReadReq_mshr_hits::total 2196 # number of ReadReq MSHR hits 780system.cpu.icache.demand_mshr_hits::cpu.inst 2196 # number of demand (read+write) MSHR hits 781system.cpu.icache.demand_mshr_hits::total 2196 # number of demand (read+write) MSHR hits 782system.cpu.icache.overall_mshr_hits::cpu.inst 2196 # number of overall MSHR hits 783system.cpu.icache.overall_mshr_hits::total 2196 # number of overall MSHR hits 784system.cpu.icache.ReadReq_mshr_misses::cpu.inst 203657 # number of ReadReq MSHR misses 785system.cpu.icache.ReadReq_mshr_misses::total 203657 # number of ReadReq MSHR misses 786system.cpu.icache.demand_mshr_misses::cpu.inst 203657 # number of demand (read+write) MSHR misses 787system.cpu.icache.demand_mshr_misses::total 203657 # number of demand (read+write) MSHR misses 788system.cpu.icache.overall_mshr_misses::cpu.inst 203657 # number of overall MSHR misses 789system.cpu.icache.overall_mshr_misses::total 203657 # number of overall MSHR misses 790system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915942000 # number of ReadReq MSHR miss cycles 791system.cpu.icache.ReadReq_mshr_miss_latency::total 915942000 # number of ReadReq MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915942000 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::total 915942000 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915942000 # number of overall MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::total 915942000 # number of overall MSHR miss cycles 796system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for ReadReq accesses 797system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001193 # mshr miss rate for ReadReq accesses 798system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for demand accesses 799system.cpu.icache.demand_mshr_miss_rate::total 0.001193 # mshr miss rate for demand accesses 800system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for overall accesses 801system.cpu.icache.overall_mshr_miss_rate::total 0.001193 # mshr miss rate for overall accesses 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4497.473694 # average ReadReq mshr miss latency 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4497.473694 # average ReadReq mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4497.473694 # average overall mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::total 4497.473694 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4497.473694 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::total 4497.473694 # average overall mshr miss latency | 776system.cpu.icache.writebacks::writebacks 6598 # number of writebacks 777system.cpu.icache.writebacks::total 6598 # number of writebacks 778system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2213 # number of ReadReq MSHR hits 779system.cpu.icache.ReadReq_mshr_hits::total 2213 # number of ReadReq MSHR hits 780system.cpu.icache.demand_mshr_hits::cpu.inst 2213 # number of demand (read+write) MSHR hits 781system.cpu.icache.demand_mshr_hits::total 2213 # number of demand (read+write) MSHR hits 782system.cpu.icache.overall_mshr_hits::cpu.inst 2213 # number of overall MSHR hits 783system.cpu.icache.overall_mshr_hits::total 2213 # number of overall MSHR hits 784system.cpu.icache.ReadReq_mshr_misses::cpu.inst 202901 # number of ReadReq MSHR misses 785system.cpu.icache.ReadReq_mshr_misses::total 202901 # number of ReadReq MSHR misses 786system.cpu.icache.demand_mshr_misses::cpu.inst 202901 # number of demand (read+write) MSHR misses 787system.cpu.icache.demand_mshr_misses::total 202901 # number of demand (read+write) MSHR misses 788system.cpu.icache.overall_mshr_misses::cpu.inst 202901 # number of overall MSHR misses 789system.cpu.icache.overall_mshr_misses::total 202901 # number of overall MSHR misses 790system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 903987500 # number of ReadReq MSHR miss cycles 791system.cpu.icache.ReadReq_mshr_miss_latency::total 903987500 # number of ReadReq MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::cpu.inst 903987500 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::total 903987500 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::cpu.inst 903987500 # number of overall MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::total 903987500 # number of overall MSHR miss cycles 796system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001188 # mshr miss rate for ReadReq accesses 797system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001188 # mshr miss rate for ReadReq accesses 798system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001188 # mshr miss rate for demand accesses 799system.cpu.icache.demand_mshr_miss_rate::total 0.001188 # mshr miss rate for demand accesses 800system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001188 # mshr miss rate for overall accesses 801system.cpu.icache.overall_mshr_miss_rate::total 0.001188 # mshr miss rate for overall accesses 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4455.313182 # average ReadReq mshr miss latency 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4455.313182 # average ReadReq mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4455.313182 # average overall mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::total 4455.313182 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4455.313182 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::total 4455.313182 # average overall mshr miss latency |
| 808system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 808system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 809system.cpu.l2cache.tags.replacements 355353 # number of replacements 810system.cpu.l2cache.tags.tagsinuse 29622.360261 # Cycle average of tags in use 811system.cpu.l2cache.tags.total_refs 3892845 # Total number of references to valid blocks. 812system.cpu.l2cache.tags.sampled_refs 387686 # Sample count of references to valid blocks. 813system.cpu.l2cache.tags.avg_refs 10.041232 # Average number of references to valid blocks. 814system.cpu.l2cache.tags.warmup_cycle 189329679500 # Cycle when the warmup percentage was hit. 815system.cpu.l2cache.tags.occ_blocks::writebacks 21025.083247 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.619745 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.657269 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_percent::writebacks 0.641635 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005695 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.data 0.256673 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::total 0.904003 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_task_id_blocks::1024 32333 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id | 809system.cpu.l2cache.tags.replacements 355236 # number of replacements 810system.cpu.l2cache.tags.tagsinuse 29620.195049 # Cycle average of tags in use 811system.cpu.l2cache.tags.total_refs 3892684 # Total number of references to valid blocks. 812system.cpu.l2cache.tags.sampled_refs 387566 # Sample count of references to valid blocks. 813system.cpu.l2cache.tags.avg_refs 10.043925 # Average number of references to valid blocks. 814system.cpu.l2cache.tags.warmup_cycle 189331361500 # Cycle when the warmup percentage was hit. 815system.cpu.l2cache.tags.occ_blocks::writebacks 21023.013022 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.931576 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.250450 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_percent::writebacks 0.641571 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005705 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.data 0.256660 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::total 0.903937 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id |
| 824system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id | 824system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id |
| 825system.cpu.l2cache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id | 825system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id |
| 826system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13404 # Occupied blocks per task id | 826system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13404 # Occupied blocks per task id |
| 827system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18612 # Occupied blocks per task id 828system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986725 # Percentage of cache occupancy per task id 829system.cpu.l2cache.tags.tag_accesses 43282239 # Number of tag accesses 830system.cpu.l2cache.tags.data_accesses 43282239 # Number of data accesses 831system.cpu.l2cache.WritebackDirty_hits::writebacks 2330580 # number of WritebackDirty hits 832system.cpu.l2cache.WritebackDirty_hits::total 2330580 # number of WritebackDirty hits 833system.cpu.l2cache.WritebackClean_hits::writebacks 6244 # number of WritebackClean hits 834system.cpu.l2cache.WritebackClean_hits::total 6244 # number of WritebackClean hits 835system.cpu.l2cache.UpgradeReq_hits::cpu.data 1851 # number of UpgradeReq hits 836system.cpu.l2cache.UpgradeReq_hits::total 1851 # number of UpgradeReq hits 837system.cpu.l2cache.ReadExReq_hits::cpu.data 563583 # number of ReadExReq hits 838system.cpu.l2cache.ReadExReq_hits::total 563583 # number of ReadExReq hits 839system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5681 # number of ReadCleanReq hits 840system.cpu.l2cache.ReadCleanReq_hits::total 5681 # number of ReadCleanReq hits 841system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587941 # number of ReadSharedReq hits 842system.cpu.l2cache.ReadSharedReq_hits::total 1587941 # number of ReadSharedReq hits 843system.cpu.l2cache.demand_hits::cpu.inst 5681 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::cpu.data 2151524 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::total 2157205 # number of demand (read+write) hits 846system.cpu.l2cache.overall_hits::cpu.inst 5681 # number of overall hits 847system.cpu.l2cache.overall_hits::cpu.data 2151524 # number of overall hits 848system.cpu.l2cache.overall_hits::total 2157205 # number of overall hits 849system.cpu.l2cache.UpgradeReq_misses::cpu.data 193439 # number of UpgradeReq misses 850system.cpu.l2cache.UpgradeReq_misses::total 193439 # number of UpgradeReq misses 851system.cpu.l2cache.ReadExReq_misses::cpu.data 206924 # number of ReadExReq misses 852system.cpu.l2cache.ReadExReq_misses::total 206924 # number of ReadExReq misses 853system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2558 # number of ReadCleanReq misses 854system.cpu.l2cache.ReadCleanReq_misses::total 2558 # number of ReadCleanReq misses 855system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176660 # number of ReadSharedReq misses 856system.cpu.l2cache.ReadSharedReq_misses::total 176660 # number of ReadSharedReq misses 857system.cpu.l2cache.demand_misses::cpu.inst 2558 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::cpu.data 383584 # number of demand (read+write) misses 859system.cpu.l2cache.demand_misses::total 386142 # number of demand (read+write) misses 860system.cpu.l2cache.overall_misses::cpu.inst 2558 # number of overall misses 861system.cpu.l2cache.overall_misses::cpu.data 383584 # number of overall misses 862system.cpu.l2cache.overall_misses::total 386142 # number of overall misses 863system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13992500 # number of UpgradeReq miss cycles 864system.cpu.l2cache.UpgradeReq_miss_latency::total 13992500 # number of UpgradeReq miss cycles 865system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16415552000 # number of ReadExReq miss cycles 866system.cpu.l2cache.ReadExReq_miss_latency::total 16415552000 # number of ReadExReq miss cycles 867system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 208018000 # number of ReadCleanReq miss cycles 868system.cpu.l2cache.ReadCleanReq_miss_latency::total 208018000 # number of ReadCleanReq miss cycles 869system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14197973500 # number of ReadSharedReq miss cycles 870system.cpu.l2cache.ReadSharedReq_miss_latency::total 14197973500 # number of ReadSharedReq miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.inst 208018000 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::cpu.data 30613525500 # number of demand (read+write) miss cycles 873system.cpu.l2cache.demand_miss_latency::total 30821543500 # number of demand (read+write) miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.inst 208018000 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::cpu.data 30613525500 # number of overall miss cycles 876system.cpu.l2cache.overall_miss_latency::total 30821543500 # number of overall miss cycles 877system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330580 # number of WritebackDirty accesses(hits+misses) 878system.cpu.l2cache.WritebackDirty_accesses::total 2330580 # number of WritebackDirty accesses(hits+misses) 879system.cpu.l2cache.WritebackClean_accesses::writebacks 6244 # number of WritebackClean accesses(hits+misses) 880system.cpu.l2cache.WritebackClean_accesses::total 6244 # number of WritebackClean accesses(hits+misses) 881system.cpu.l2cache.UpgradeReq_accesses::cpu.data 195290 # number of UpgradeReq accesses(hits+misses) 882system.cpu.l2cache.UpgradeReq_accesses::total 195290 # number of UpgradeReq accesses(hits+misses) 883system.cpu.l2cache.ReadExReq_accesses::cpu.data 770507 # number of ReadExReq accesses(hits+misses) 884system.cpu.l2cache.ReadExReq_accesses::total 770507 # number of ReadExReq accesses(hits+misses) 885system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8239 # number of ReadCleanReq accesses(hits+misses) 886system.cpu.l2cache.ReadCleanReq_accesses::total 8239 # number of ReadCleanReq accesses(hits+misses) 887system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764601 # number of ReadSharedReq accesses(hits+misses) 888system.cpu.l2cache.ReadSharedReq_accesses::total 1764601 # number of ReadSharedReq accesses(hits+misses) 889system.cpu.l2cache.demand_accesses::cpu.inst 8239 # number of demand (read+write) accesses 890system.cpu.l2cache.demand_accesses::cpu.data 2535108 # number of demand (read+write) accesses 891system.cpu.l2cache.demand_accesses::total 2543347 # number of demand (read+write) accesses 892system.cpu.l2cache.overall_accesses::cpu.inst 8239 # number of overall (read+write) accesses 893system.cpu.l2cache.overall_accesses::cpu.data 2535108 # number of overall (read+write) accesses 894system.cpu.l2cache.overall_accesses::total 2543347 # number of overall (read+write) accesses 895system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990522 # miss rate for UpgradeReq accesses 896system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990522 # miss rate for UpgradeReq accesses 897system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268556 # miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadExReq_miss_rate::total 0.268556 # miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.310475 # miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.310475 # miss rate for ReadCleanReq accesses 901system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100113 # miss rate for ReadSharedReq accesses 902system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100113 # miss rate for ReadSharedReq accesses 903system.cpu.l2cache.demand_miss_rate::cpu.inst 0.310475 # miss rate for demand accesses 904system.cpu.l2cache.demand_miss_rate::cpu.data 0.151309 # miss rate for demand accesses 905system.cpu.l2cache.demand_miss_rate::total 0.151824 # miss rate for demand accesses 906system.cpu.l2cache.overall_miss_rate::cpu.inst 0.310475 # miss rate for overall accesses 907system.cpu.l2cache.overall_miss_rate::cpu.data 0.151309 # miss rate for overall accesses 908system.cpu.l2cache.overall_miss_rate::total 0.151824 # miss rate for overall accesses 909system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.335465 # average UpgradeReq miss latency 910system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.335465 # average UpgradeReq miss latency 911system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79331.310046 # average ReadExReq miss latency 912system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79331.310046 # average ReadExReq miss latency 913system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.562940 # average ReadCleanReq miss latency 914system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.562940 # average ReadCleanReq miss latency 915system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80368.920525 # average ReadSharedReq miss latency 916system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80368.920525 # average ReadSharedReq miss latency 917system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.562940 # average overall miss latency 918system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79809.182604 # average overall miss latency 919system.cpu.l2cache.demand_avg_miss_latency::total 79819.194752 # average overall miss latency 920system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.562940 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79809.182604 # average overall miss latency 922system.cpu.l2cache.overall_avg_miss_latency::total 79819.194752 # average overall miss latency | 827system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18615 # Occupied blocks per task id 828system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986633 # Percentage of cache occupancy per task id 829system.cpu.l2cache.tags.tag_accesses 43275096 # Number of tag accesses 830system.cpu.l2cache.tags.data_accesses 43275096 # Number of data accesses 831system.cpu.l2cache.WritebackDirty_hits::writebacks 2330614 # number of WritebackDirty hits 832system.cpu.l2cache.WritebackDirty_hits::total 2330614 # number of WritebackDirty hits 833system.cpu.l2cache.WritebackClean_hits::writebacks 6188 # number of WritebackClean hits 834system.cpu.l2cache.WritebackClean_hits::total 6188 # number of WritebackClean hits 835system.cpu.l2cache.UpgradeReq_hits::cpu.data 1825 # number of UpgradeReq hits 836system.cpu.l2cache.UpgradeReq_hits::total 1825 # number of UpgradeReq hits 837system.cpu.l2cache.ReadExReq_hits::cpu.data 563621 # number of ReadExReq hits 838system.cpu.l2cache.ReadExReq_hits::total 563621 # number of ReadExReq hits 839system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5638 # number of ReadCleanReq hits 840system.cpu.l2cache.ReadCleanReq_hits::total 5638 # number of ReadCleanReq hits 841system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587969 # number of ReadSharedReq hits 842system.cpu.l2cache.ReadSharedReq_hits::total 1587969 # number of ReadSharedReq hits 843system.cpu.l2cache.demand_hits::cpu.inst 5638 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::cpu.data 2151590 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::total 2157228 # number of demand (read+write) hits 846system.cpu.l2cache.overall_hits::cpu.inst 5638 # number of overall hits 847system.cpu.l2cache.overall_hits::cpu.data 2151590 # number of overall hits 848system.cpu.l2cache.overall_hits::total 2157228 # number of overall hits 849system.cpu.l2cache.UpgradeReq_misses::cpu.data 192758 # number of UpgradeReq misses 850system.cpu.l2cache.UpgradeReq_misses::total 192758 # number of UpgradeReq misses 851system.cpu.l2cache.ReadExReq_misses::cpu.data 206906 # number of ReadExReq misses 852system.cpu.l2cache.ReadExReq_misses::total 206906 # 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number of UpgradeReq miss cycles 865system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16413935500 # number of ReadExReq miss cycles 866system.cpu.l2cache.ReadExReq_miss_latency::total 16413935500 # number of ReadExReq miss cycles 867system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 209752500 # number of ReadCleanReq miss cycles 868system.cpu.l2cache.ReadCleanReq_miss_latency::total 209752500 # number of ReadCleanReq miss cycles 869system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14193739500 # number of ReadSharedReq miss cycles 870system.cpu.l2cache.ReadSharedReq_miss_latency::total 14193739500 # number of ReadSharedReq miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.inst 209752500 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::cpu.data 30607675000 # number of demand (read+write) miss cycles 873system.cpu.l2cache.demand_miss_latency::total 30817427500 # number of demand (read+write) miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.inst 209752500 # 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number of ReadExReq accesses(hits+misses) 885system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8192 # number of ReadCleanReq accesses(hits+misses) 886system.cpu.l2cache.ReadCleanReq_accesses::total 8192 # number of ReadCleanReq accesses(hits+misses) 887system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764548 # number of ReadSharedReq accesses(hits+misses) 888system.cpu.l2cache.ReadSharedReq_accesses::total 1764548 # number of ReadSharedReq accesses(hits+misses) 889system.cpu.l2cache.demand_accesses::cpu.inst 8192 # number of demand (read+write) accesses 890system.cpu.l2cache.demand_accesses::cpu.data 2535075 # number of demand (read+write) accesses 891system.cpu.l2cache.demand_accesses::total 2543267 # number of demand (read+write) accesses 892system.cpu.l2cache.overall_accesses::cpu.inst 8192 # number of overall (read+write) accesses 893system.cpu.l2cache.overall_accesses::cpu.data 2535075 # number of overall (read+write) accesses 894system.cpu.l2cache.overall_accesses::total 2543267 # number of overall (read+write) accesses 895system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990621 # miss rate for UpgradeReq accesses 896system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990621 # miss rate for UpgradeReq accesses 897system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268525 # miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadExReq_miss_rate::total 0.268525 # miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.311768 # miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.311768 # miss rate for ReadCleanReq accesses 901system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100070 # miss rate for ReadSharedReq accesses 902system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100070 # miss rate for ReadSharedReq accesses 903system.cpu.l2cache.demand_miss_rate::cpu.inst 0.311768 # miss rate for demand accesses 904system.cpu.l2cache.demand_miss_rate::cpu.data 0.151272 # miss rate for demand accesses 905system.cpu.l2cache.demand_miss_rate::total 0.151789 # miss rate for demand accesses 906system.cpu.l2cache.overall_miss_rate::cpu.inst 0.311768 # miss rate for overall accesses 907system.cpu.l2cache.overall_miss_rate::cpu.data 0.151272 # miss rate for overall accesses 908system.cpu.l2cache.overall_miss_rate::total 0.151789 # miss rate for overall accesses 909system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 66.158084 # average UpgradeReq miss latency 910system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 66.158084 # average UpgradeReq miss latency 911system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79330.398828 # average ReadExReq miss latency 912system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79330.398828 # average ReadExReq miss latency 913system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82127.055599 # average ReadCleanReq miss latency 914system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82127.055599 # average ReadCleanReq miss latency 915system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80381.809275 # average ReadSharedReq miss latency 916system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80381.809275 # average ReadSharedReq miss latency 917system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82127.055599 # average overall miss latency 918system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79814.529903 # average overall miss latency 919system.cpu.l2cache.demand_avg_miss_latency::total 79829.829370 # average overall miss latency 920system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82127.055599 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79814.529903 # average overall miss latency 922system.cpu.l2cache.overall_avg_miss_latency::total 79829.829370 # average overall miss latency |
| 923system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 924system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 925system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 926system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 927system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 928system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 929system.cpu.l2cache.fast_writes 0 # number of fast writes performed 930system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 923system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 924system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 925system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 926system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 927system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 928system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 929system.cpu.l2cache.fast_writes 0 # number of fast writes performed 930system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 931system.cpu.l2cache.writebacks::writebacks 295163 # number of writebacks 932system.cpu.l2cache.writebacks::total 295163 # number of writebacks | 931system.cpu.l2cache.writebacks::writebacks 295111 # number of writebacks 932system.cpu.l2cache.writebacks::total 295111 # number of writebacks |
| 933system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 934system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 935system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 936system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 937system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 938system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 933system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 934system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 935system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 936system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 937system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 938system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
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number of demand (read+write) MSHR misses 950system.cpu.l2cache.demand_mshr_misses::cpu.data 383485 # number of demand (read+write) MSHR misses 951system.cpu.l2cache.demand_mshr_misses::total 386038 # number of demand (read+write) MSHR misses 952system.cpu.l2cache.overall_mshr_misses::cpu.inst 2553 # number of overall MSHR misses 953system.cpu.l2cache.overall_mshr_misses::cpu.data 383485 # number of overall MSHR misses 954system.cpu.l2cache.overall_mshr_misses::total 386038 # number of overall MSHR misses 955system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3718916993 # number of UpgradeReq MSHR miss cycles 956system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3718916993 # number of UpgradeReq MSHR miss cycles 957system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14344875500 # number of ReadExReq MSHR miss cycles 958system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14344875500 # number of ReadExReq MSHR miss cycles 959system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184165500 # number of ReadCleanReq MSHR miss cycles 960system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184165500 # number of ReadCleanReq MSHR miss cycles 961system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12427929541 # number of ReadSharedReq MSHR miss cycles 962system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12427929541 # number of ReadSharedReq MSHR miss cycles 963system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184165500 # number of demand (read+write) MSHR miss cycles 964system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26772805041 # number of demand (read+write) MSHR miss cycles 965system.cpu.l2cache.demand_mshr_miss_latency::total 26956970541 # number of demand (read+write) MSHR miss cycles 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184165500 # number of overall MSHR miss cycles 967system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26772805041 # number of overall MSHR miss cycles 968system.cpu.l2cache.overall_mshr_miss_latency::total 26956970541 # number of overall MSHR miss cycles |
| 969system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 970system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 969system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 970system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 971system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990522 # mshr miss rate for UpgradeReq accesses 972system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990522 # mshr miss rate for UpgradeReq accesses 973system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268556 # mshr miss rate for ReadExReq accesses 974system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268556 # mshr miss rate for ReadExReq accesses 975system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for ReadCleanReq accesses 976system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310353 # mshr miss rate for ReadCleanReq accesses 977system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100113 # mshr miss rate for ReadSharedReq accesses 978system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100113 # mshr miss rate for ReadSharedReq accesses 979system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for demand accesses 980system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for demand accesses 981system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses 982system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for overall accesses 983system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for overall accesses 984system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses 985system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22064.304546 # average UpgradeReq mshr miss latency 986system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22064.304546 # average UpgradeReq mshr miss latency 987system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69331.310046 # average ReadExReq mshr miss latency 988system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69331.310046 # average ReadExReq mshr miss latency 989system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71330.269847 # average ReadCleanReq mshr miss latency 990system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71330.269847 # average ReadCleanReq mshr miss latency 991system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70368.920525 # average ReadSharedReq mshr miss latency 992system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70368.920525 # average ReadSharedReq mshr miss latency 993system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency 994system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency 995system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency 996system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency 997system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency 998system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency | 971system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990621 # mshr miss rate for UpgradeReq accesses 972system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990621 # mshr miss rate for UpgradeReq accesses 973system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268525 # mshr miss rate for ReadExReq accesses 974system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268525 # mshr miss rate for ReadExReq accesses 975system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for ReadCleanReq accesses 976system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.311646 # mshr miss rate for ReadCleanReq accesses 977system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100070 # mshr miss rate for ReadSharedReq accesses 978system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100070 # mshr miss rate for ReadSharedReq accesses 979system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for demand accesses 980system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for demand accesses 981system.cpu.l2cache.demand_mshr_miss_rate::total 0.151788 # mshr miss rate for demand accesses 982system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for overall accesses 983system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for overall accesses 984system.cpu.l2cache.overall_mshr_miss_rate::total 0.151788 # mshr miss rate for overall accesses 985system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19293.191427 # average UpgradeReq mshr miss latency 986system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19293.191427 # average UpgradeReq mshr miss latency 987system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69330.398828 # average ReadExReq mshr miss latency 988system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69330.398828 # average ReadExReq mshr miss latency 989system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72136.897767 # average ReadCleanReq mshr miss latency 990system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72136.897767 # average ReadCleanReq mshr miss latency 991system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70381.696244 # average ReadSharedReq mshr miss latency 992system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70381.696244 # average ReadSharedReq mshr miss latency 993system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency 994system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency 995system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency 996system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency 997system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency 998system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency |
| 999system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 999system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1000system.cpu.toL2Bus.snoop_filter.tot_requests 5471713 # Total number of requests made to the snoop filter. 1001system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729811 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1002system.cpu.toL2Bus.snoop_filter.hit_multi_requests 210473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1003system.cpu.toL2Bus.snoop_filter.tot_snoops 3600 # Total number of snoops made to the snoop filter. 1004system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3600 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1000system.cpu.toL2Bus.snoop_filter.tot_requests 5470136 # Total number of requests made to the snoop filter. 1001system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729158 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1002system.cpu.toL2Bus.snoop_filter.hit_multi_requests 209637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1003system.cpu.toL2Bus.snoop_filter.tot_snoops 3579 # Total number of snoops made to the snoop filter. 1004system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3579 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1005system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1005system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1006system.cpu.toL2Bus.trans_dist::ReadResp 1968256 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::WritebackDirty 2625743 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::WritebackClean 6244 # Transaction distribution 1009system.cpu.toL2Bus.trans_dist::CleanEvict 249948 # Transaction distribution 1010system.cpu.toL2Bus.trans_dist::UpgradeReq 195290 # Transaction distribution 1011system.cpu.toL2Bus.trans_dist::UpgradeResp 195290 # Transaction distribution 1012system.cpu.toL2Bus.trans_dist::ReadExReq 770507 # Transaction distribution 1013system.cpu.toL2Bus.trans_dist::ReadExResp 770507 # Transaction distribution 1014system.cpu.toL2Bus.trans_dist::ReadCleanReq 203657 # Transaction distribution 1015system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764601 # Transaction distribution 1016system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 218138 # Packet count per connected master and slave (bytes) 1017system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7981134 # Packet count per connected master and slave (bytes) 1018system.cpu.toL2Bus.pkt_count::total 8199272 # Packet count per connected master and slave (bytes) 1019system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 926784 # Cumulative packet size per connected master and slave (bytes) 1020system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404032 # Cumulative packet size per connected master and slave (bytes) 1021system.cpu.toL2Bus.pkt_size::total 312330816 # Cumulative packet size per connected master and slave (bytes) 1022system.cpu.toL2Bus.snoops 550771 # Total snoops (count) 1023system.cpu.toL2Bus.snoop_fanout::samples 3289408 # Request fanout histogram 1024system.cpu.toL2Bus.snoop_fanout::mean 0.123462 # Request fanout histogram 1025system.cpu.toL2Bus.snoop_fanout::stdev 0.328967 # Request fanout histogram | 1006system.cpu.toL2Bus.trans_dist::ReadResp 1967447 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::WritebackDirty 2625725 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::WritebackClean 6598 # Transaction distribution 1009system.cpu.toL2Bus.trans_dist::CleanEvict 260490 # Transaction distribution 1010system.cpu.toL2Bus.trans_dist::UpgradeReq 194583 # Transaction distribution 1011system.cpu.toL2Bus.trans_dist::UpgradeResp 194583 # Transaction distribution 1012system.cpu.toL2Bus.trans_dist::ReadExReq 770527 # Transaction distribution 1013system.cpu.toL2Bus.trans_dist::ReadExResp 770527 # Transaction distribution 1014system.cpu.toL2Bus.trans_dist::ReadCleanReq 202901 # Transaction distribution 1015system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764548 # Transaction distribution 1016system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217689 # Packet count per connected master and slave (bytes) 1017system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7990295 # Packet count per connected master and slave (bytes) 1018system.cpu.toL2Bus.pkt_count::total 8207984 # Packet count per connected master and slave (bytes) 1019system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 946432 # Cumulative packet size per connected master and slave (bytes) 1020system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404096 # Cumulative packet size per connected master and slave (bytes) 1021system.cpu.toL2Bus.pkt_size::total 312350528 # Cumulative packet size per connected master and slave (bytes) 1022system.cpu.toL2Bus.snoops 549945 # Total snoops (count) 1023system.cpu.toL2Bus.snoop_fanout::samples 3287795 # Request fanout histogram 1024system.cpu.toL2Bus.snoop_fanout::mean 0.123088 # Request fanout histogram 1025system.cpu.toL2Bus.snoop_fanout::stdev 0.328538 # Request fanout histogram |
| 1026system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1026system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1027system.cpu.toL2Bus.snoop_fanout::0 2883292 87.65% 87.65% # Request fanout histogram 1028system.cpu.toL2Bus.snoop_fanout::1 406116 12.35% 100.00% # Request fanout histogram | 1027system.cpu.toL2Bus.snoop_fanout::0 2883107 87.69% 87.69% # Request fanout histogram 1028system.cpu.toL2Bus.snoop_fanout::1 404688 12.31% 100.00% # Request fanout histogram |
| 1029system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1030system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1031system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1032system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1029system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1030system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1031system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1032system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1033system.cpu.toL2Bus.snoop_fanout::total 3289408 # Request fanout histogram 1034system.cpu.toL2Bus.reqLayer0.occupancy 5101560430 # Layer occupancy (ticks) | 1033system.cpu.toL2Bus.snoop_fanout::total 3287795 # Request fanout histogram 1034system.cpu.toL2Bus.reqLayer0.occupancy 5100517412 # Layer occupancy (ticks) |
| 1035system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) | 1035system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) |
| 1036system.cpu.toL2Bus.respLayer0.occupancy 305490983 # Layer occupancy (ticks) | 1036system.cpu.toL2Bus.respLayer0.occupancy 304355486 # Layer occupancy (ticks) |
| 1037system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1037system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1038system.cpu.toL2Bus.respLayer1.occupancy 3900309572 # Layer occupancy (ticks) | 1038system.cpu.toL2Bus.respLayer1.occupancy 3899906073 # Layer occupancy (ticks) |
| 1039system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) | 1039system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 1040system.membus.trans_dist::ReadResp 179215 # Transaction distribution 1041system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution 1042system.membus.trans_dist::CleanEvict 56660 # Transaction distribution 1043system.membus.trans_dist::UpgradeReq 193490 # Transaction distribution 1044system.membus.trans_dist::UpgradeResp 193490 # Transaction distribution 1045system.membus.trans_dist::ReadExReq 206873 # Transaction distribution 1046system.membus.trans_dist::ReadExResp 206873 # Transaction distribution 1047system.membus.trans_dist::ReadSharedReq 179216 # Transaction distribution 1048system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1510980 # Packet count per connected master and slave (bytes) 1049system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1510980 # Packet count per connected master and slave (bytes) 1050system.membus.pkt_count::total 1510980 # Packet count per connected master and slave (bytes) 1051system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43600064 # Cumulative packet size per connected master and slave (bytes) 1052system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43600064 # Cumulative packet size per connected master and slave (bytes) 1053system.membus.pkt_size::total 43600064 # Cumulative packet size per connected master and slave (bytes) | 1040system.membus.trans_dist::ReadResp 179130 # Transaction distribution 1041system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution 1042system.membus.trans_dist::CleanEvict 56614 # Transaction distribution 1043system.membus.trans_dist::UpgradeReq 192805 # Transaction distribution 1044system.membus.trans_dist::ReadExReq 206859 # Transaction distribution 1045system.membus.trans_dist::ReadExResp 206859 # Transaction distribution 1046system.membus.trans_dist::ReadSharedReq 179131 # Transaction distribution 1047system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1316509 # Packet count per connected master and slave (bytes) 1048system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1316509 # Packet count per connected master and slave (bytes) 1049system.membus.pkt_count::total 1316509 # Packet count per connected master and slave (bytes) 1050system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43590400 # Cumulative packet size per connected master and slave (bytes) 1051system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43590400 # Cumulative packet size per connected master and slave (bytes) 1052system.membus.pkt_size::total 43590400 # Cumulative packet size per connected master and slave (bytes) |
| 1054system.membus.snoops 0 # Total snoops (count) | 1053system.membus.snoops 0 # Total snoops (count) |
| 1055system.membus.snoop_fanout::samples 931402 # Request fanout histogram | 1054system.membus.snoop_fanout::samples 930520 # Request fanout histogram |
| 1056system.membus.snoop_fanout::mean 0 # Request fanout histogram 1057system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1058system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1055system.membus.snoop_fanout::mean 0 # Request fanout histogram 1056system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1057system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1059system.membus.snoop_fanout::0 931402 100.00% 100.00% # Request fanout histogram | 1058system.membus.snoop_fanout::0 930520 100.00% 100.00% # Request fanout histogram |
| 1060system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1061system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1062system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1063system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1059system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1060system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1061system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1062system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1064system.membus.snoop_fanout::total 931402 # Request fanout histogram 1065system.membus.reqLayer0.occupancy 2242581485 # Layer occupancy (ticks) | 1063system.membus.snoop_fanout::total 930520 # Request fanout histogram 1064system.membus.reqLayer0.occupancy 2239434504 # Layer occupancy (ticks) |
| 1066system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) | 1065system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 1067system.membus.respLayer1.occupancy 2429056686 # Layer occupancy (ticks) 1068system.membus.respLayer1.utilization 0.6 # Layer utilization (%) | 1066system.membus.respLayer1.occupancy 2041939000 # Layer occupancy (ticks) 1067system.membus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 1069 1070---------- End Simulation Statistics ---------- | 1068 1069---------- End Simulation Statistics ---------- |