| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.403707 # Number of seconds simulated 4sim_ticks 403706643500 # Number of ticks simulated 5final_tick 403706643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.403931 # Number of seconds simulated 4sim_ticks 403931323500 # Number of ticks simulated 5final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 76271 # Simulator instruction rate (inst/s) 8host_op_rate 141034 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37237827 # Simulator tick rate (ticks/s) 10host_mem_usage 423672 # Number of bytes of host memory used 11host_seconds 10841.31 # Real time elapsed on the host | 7host_inst_rate 95186 # Simulator instruction rate (inst/s) 8host_op_rate 176009 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46498470 # Simulator tick rate (ticks/s) 10host_mem_usage 433064 # Number of bytes of host memory used 11host_seconds 8686.98 # Real time elapsed on the host |
| 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 216320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24497408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24713728 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 216320 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 216320 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18869312 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18869312 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3380 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 382772 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386152 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 294833 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 294833 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 535835 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 60681211 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 61217046 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 535835 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 535835 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 46740157 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 46740157 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 46740157 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 535835 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 60681211 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 107957203 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386152 # Number of read requests accepted 40system.physmem.writeReqs 294833 # Number of write requests accepted 41system.physmem.readBursts 386152 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 294833 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24695616 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18867776 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24713728 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18869312 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386228 # Number of read requests accepted 40system.physmem.writeReqs 294838 # Number of write requests accepted 41system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 50system.physmem.neitherReadNorWriteReqs 195189 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24028 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26400 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24980 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24600 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23395 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23728 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24595 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24357 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23707 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23543 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24760 # Per bank write bursts 62system.physmem.perBankRdBursts::11 23969 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23156 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22899 # Per bank write bursts 65system.physmem.perBankRdBursts::14 23872 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23880 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18605 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19929 # Per bank write bursts 69system.physmem.perBankWrBursts::2 19196 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18982 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18144 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18488 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19136 # Per bank write bursts 74system.physmem.perBankWrBursts::7 19077 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18672 # Per bank write bursts 76system.physmem.perBankWrBursts::9 17940 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18886 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17736 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17372 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16987 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17811 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17848 # Per bank write bursts | 50system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24062 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26430 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24903 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24577 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23181 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23704 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24550 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24303 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23663 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23568 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24789 # Per bank write bursts 62system.physmem.perBankRdBursts::11 23975 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23330 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22932 # Per bank write bursts 65system.physmem.perBankRdBursts::14 24089 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23873 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18604 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19922 # Per bank write bursts 69system.physmem.perBankWrBursts::2 19191 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18985 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18090 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18485 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19138 # Per bank write bursts 74system.physmem.perBankWrBursts::7 19082 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18642 # Per bank write bursts 76system.physmem.perBankWrBursts::9 17946 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18887 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17737 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17398 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16988 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17875 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17843 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 403706602500 # Total gap between requests | 85system.physmem.totGap 403931308500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 386152 # Read request sizes (log2) | 92system.physmem.readPktSize::6 386228 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 294833 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 380965 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4554 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 304 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 294838 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 6120 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6530 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16981 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17547 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17622 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17651 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17636 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17673 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17680 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17702 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17653 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17736 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17738 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17711 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17905 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17556 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see |
| 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 146765 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 296.814963 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 175.408246 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 322.979648 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54126 36.88% 36.88% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 39824 27.13% 64.01% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13787 9.39% 73.41% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7512 5.12% 78.53% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5608 3.82% 82.35% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3872 2.64% 84.99% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3087 2.10% 87.09% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2794 1.90% 88.99% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16155 11.01% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 146765 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17509 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.037923 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 218.270562 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17499 99.94% 99.94% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes |
| 215system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes | 215system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 17509 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17509 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.837569 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.769084 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.527211 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17319 98.91% 98.91% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 139 0.79% 99.71% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 19 0.11% 99.82% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 11 0.06% 99.88% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-35 2 0.01% 99.89% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::36-39 2 0.01% 99.90% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-43 2 0.01% 99.91% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::44-47 5 0.03% 99.94% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::76-79 2 0.01% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::80-83 1 0.01% 99.99% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::136-139 1 0.01% 99.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::total 17509 # Writes before turning the bus around for reads 241system.physmem.totQLat 4289653250 # Total ticks spent queuing 242system.physmem.totMemAccLat 11524697000 # Total ticks spent from burst creation until serviced by the DRAM 243system.physmem.totBusLat 1929345000 # Total ticks spent in databus transfers 244system.physmem.avgQLat 11116.86 # Average queueing delay per DRAM burst | 218system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads 243system.physmem.totQLat 4291077750 # Total ticks spent queuing 244system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst |
| 245system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 246system.physmem.avgMemAccLat 29866.86 # Average memory access latency per DRAM burst 247system.physmem.avgRdBW 61.17 # Average DRAM read bandwidth in MiByte/s 248system.physmem.avgWrBW 46.74 # Average achieved write bandwidth in MiByte/s 249system.physmem.avgRdBWSys 61.22 # Average system read bandwidth in MiByte/s 250system.physmem.avgWrBWSys 46.74 # Average system write bandwidth in MiByte/s | 248system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s |
| 251system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 252system.physmem.busUtil 0.84 # Data bus utilization in percentage 253system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads | 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 0.84 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads |
| 254system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes | 256system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes |
| 255system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 257system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 256system.physmem.avgWrQLen 20.93 # Average write queue length when enqueuing 257system.physmem.readRowHits 317973 # Number of row buffer hits during reads 258system.physmem.writeRowHits 215927 # Number of row buffer hits during writes | 258system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing 259system.physmem.readRowHits 317989 # Number of row buffer hits during reads 260system.physmem.writeRowHits 215873 # Number of row buffer hits during writes |
| 259system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads | 261system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads |
| 260system.physmem.writeRowHitRate 73.24 # Row buffer hit rate for writes 261system.physmem.avgGap 592827.45 # Average gap between requests 262system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined 263system.physmem_0.actEnergy 569094120 # Energy for activate commands per rank (pJ) 264system.physmem_0.preEnergy 310517625 # Energy for precharge commands per rank (pJ) 265system.physmem_0.readEnergy 1529307000 # Energy for read commands per rank (pJ) 266system.physmem_0.writeEnergy 981933840 # Energy for write commands per rank (pJ) 267system.physmem_0.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) 268system.physmem_0.actBackEnergy 62417540205 # Energy for active background per rank (pJ) 269system.physmem_0.preBackEnergy 187468813500 # Energy for precharge background per rank (pJ) 270system.physmem_0.totalEnergy 279645025170 # Total energy per rank (pJ) 271system.physmem_0.averagePower 692.702062 # Core power per rank (mW) 272system.physmem_0.memoryStateTime::IDLE 311319479750 # Time in different power states 273system.physmem_0.memoryStateTime::REF 13480480000 # Time in different power states | 262system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes 263system.physmem.avgGap 593086.88 # Average gap between requests 264system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined 265system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ) 272system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ) 273system.physmem_0.averagePower 692.623817 # Core power per rank (mW) 274system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states 275system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states |
| 274system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 276system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 275system.physmem_0.memoryStateTime::ACT 78902125750 # Time in different power states | 277system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states |
| 276system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 278system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 277system.physmem_1.actEnergy 540041040 # Energy for activate commands per rank (pJ) 278system.physmem_1.preEnergy 294665250 # Energy for precharge commands per rank (pJ) 279system.physmem_1.readEnergy 1479816000 # Energy for read commands per rank (pJ) 280system.physmem_1.writeEnergy 928013760 # Energy for write commands per rank (pJ) 281system.physmem_1.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) 282system.physmem_1.actBackEnergy 60324869565 # Energy for active background per rank (pJ) 283system.physmem_1.preBackEnergy 189304489500 # Energy for precharge background per rank (pJ) 284system.physmem_1.totalEnergy 279239713995 # Total energy per rank (pJ) 285system.physmem_1.averagePower 691.698075 # Core power per rank (mW) 286system.physmem_1.memoryStateTime::IDLE 314381404750 # Time in different power states 287system.physmem_1.memoryStateTime::REF 13480480000 # Time in different power states | 279system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ) 280system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ) 281system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ) 282system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ) 283system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) 284system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ) 285system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ) 286system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ) 287system.physmem_1.averagePower 691.740141 # Core power per rank (mW) 288system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states 289system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states |
| 288system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 290system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 289system.physmem_1.memoryStateTime::ACT 75839865250 # Time in different power states | 291system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states |
| 290system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 292system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 291system.cpu.branchPred.lookups 219316547 # Number of BP lookups 292system.cpu.branchPred.condPredicted 219316547 # Number of conditional branches predicted 293system.cpu.branchPred.condIncorrect 8533340 # Number of conditional branches incorrect 294system.cpu.branchPred.BTBLookups 124021938 # Number of BTB lookups 295system.cpu.branchPred.BTBHits 121820147 # Number of BTB hits | 293system.cpu.branchPred.lookups 219314839 # Number of BP lookups 294system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted 295system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect 296system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups 297system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits |
| 296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 298system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 297system.cpu.branchPred.BTBHitPct 98.224676 # BTB Hit Percentage 298system.cpu.branchPred.usedRAS 27066490 # Number of times the RAS was used to get a target. 299system.cpu.branchPred.RASInCorrect 1406992 # Number of incorrect RAS predictions. | 299system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage 300system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target. 301system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions. |
| 300system.cpu_clk_domain.clock 500 # Clock period in ticks 301system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 302system.cpu.workload.num_syscalls 551 # Number of system calls | 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 304system.cpu.workload.num_syscalls 551 # Number of system calls |
| 303system.cpu.numCycles 807413288 # number of cpu cycles simulated | 305system.cpu.numCycles 807862648 # number of cpu cycles simulated |
| 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 306system.cpu.fetch.icacheStallCycles 175921222 # Number of cycles fetch is stalled on an Icache miss 307system.cpu.fetch.Insts 1208610344 # Number of instructions fetch has processed 308system.cpu.fetch.Branches 219316547 # Number of branches that fetch encountered 309system.cpu.fetch.predictedBranches 148886637 # Number of branches that fetch has predicted taken 310system.cpu.fetch.Cycles 621541997 # Number of cycles fetch has run and was not squashing or blocked 311system.cpu.fetch.SquashCycles 17781141 # Number of cycles fetch has spent squashing 312system.cpu.fetch.TlbCycles 241 # Number of cycles fetch has spent waiting for tlb 313system.cpu.fetch.MiscStallCycles 95442 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 314system.cpu.fetch.PendingTrapStallCycles 760366 # Number of stall cycles due to pending traps 315system.cpu.fetch.PendingQuiesceStallCycles 1422 # Number of stall cycles due to pending quiesce instructions 316system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR 317system.cpu.fetch.CacheLines 170776115 # Number of cache lines fetched 318system.cpu.fetch.IcacheSquashes 2324492 # Number of outstanding Icache misses that were squashed 319system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed 320system.cpu.fetch.rateDist::samples 807211301 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::mean 2.786075 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::stdev 3.367353 # Number of instructions fetched each cycle (Total) | 308system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 316system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps 317system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions 318system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total) |
| 323system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 324system.cpu.fetch.rateDist::0 417064653 51.67% 51.67% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::1 32628603 4.04% 55.71% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::2 31895320 3.95% 59.66% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::3 32734486 4.06% 63.72% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::4 26590994 3.29% 67.01% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::5 26897855 3.33% 70.34% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::6 35141039 4.35% 74.70% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::7 31437377 3.89% 78.59% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::8 172820974 21.41% 100.00% # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total) |
| 333system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 336system.cpu.fetch.rateDist::total 807211301 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.branchRate 0.271629 # Number of branch fetches per cycle 338system.cpu.fetch.rate 1.496892 # Number of inst fetches per cycle 339system.cpu.decode.IdleCycles 120518152 # Number of cycles decode is idle 340system.cpu.decode.BlockedCycles 370503139 # Number of cycles decode is blocked 341system.cpu.decode.RunCycles 225214950 # Number of cycles decode is running 342system.cpu.decode.UnblockCycles 82084490 # Number of cycles decode is unblocking 343system.cpu.decode.SquashCycles 8890570 # Number of cycles decode is squashing 344system.cpu.decode.DecodedInsts 2132165876 # Number of instructions handled by decode 345system.cpu.rename.SquashCycles 8890570 # Number of cycles rename is squashing 346system.cpu.rename.IdleCycles 152539883 # Number of cycles rename is idle 347system.cpu.rename.BlockCycles 150620560 # Number of cycles rename is blocking 348system.cpu.rename.serializeStallCycles 39985 # count of cycles rename stalled for serializing inst 349system.cpu.rename.RunCycles 271567858 # Number of cycles rename is running 350system.cpu.rename.UnblockCycles 223552445 # Number of cycles rename is unblocking 351system.cpu.rename.RenamedInsts 2088589695 # Number of instructions processed by rename 352system.cpu.rename.ROBFullEvents 134600 # Number of times rename has blocked due to ROB full 353system.cpu.rename.IQFullEvents 138169190 # Number of times rename has blocked due to IQ full 354system.cpu.rename.LQFullEvents 24839349 # Number of times rename has blocked due to LQ full 355system.cpu.rename.SQFullEvents 50537004 # Number of times rename has blocked due to SQ full 356system.cpu.rename.RenamedOperands 2190785289 # Number of destination operands rename has renamed 357system.cpu.rename.RenameLookups 5278493147 # Number of register rename lookups that rename has made 358system.cpu.rename.int_rename_lookups 3357262511 # Number of integer rename lookups 359system.cpu.rename.fp_rename_lookups 59407 # Number of floating rename lookups | 338system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle 340system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode 347system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing 348system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle 349system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking 350system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst 351system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running 352system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking 353system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename 354system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full 355system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full 356system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full 357system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full 358system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed 359system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made 360system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups 361system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups |
| 360system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed | 362system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed |
| 361system.cpu.rename.UndoneMaps 576744435 # Number of HB maps that are undone due to squashing 362system.cpu.rename.serializingInsts 3185 # count of serializing insts renamed 363system.cpu.rename.tempSerializingInsts 2908 # count of temporary serializing insts renamed 364system.cpu.rename.skidInsts 421985771 # count of insts added to the skid buffer 365system.cpu.memDep0.insertedLoads 507135954 # Number of loads inserted to the mem dependence unit. 366system.cpu.memDep0.insertedStores 200817604 # Number of stores inserted to the mem dependence unit. 367system.cpu.memDep0.conflictingLoads 229019753 # Number of conflicting loads. 368system.cpu.memDep0.conflictingStores 68232285 # Number of conflicting stores. 369system.cpu.iq.iqInstsAdded 2023164418 # Number of instructions added to the IQ (excludes non-spec) 370system.cpu.iq.iqNonSpecInstsAdded 22990 # Number of non-speculative instructions added to the IQ 371system.cpu.iq.iqInstsIssued 1789038207 # Number of instructions issued 372system.cpu.iq.iqSquashedInstsIssued 420221 # Number of squashed instructions issued 373system.cpu.iq.iqSquashedInstsExamined 494198707 # Number of squashed instructions iterated over during squash; mainly for profiling 374system.cpu.iq.iqSquashedOperandsExamined 833041498 # Number of squashed operands that are examined and possibly removed from graph 375system.cpu.iq.iqSquashedNonSpecRemoved 22438 # Number of squashed non-spec instructions that were removed 376system.cpu.iq.issued_per_cycle::samples 807211301 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::mean 2.216320 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::stdev 2.070566 # Number of insts issued each cycle | 363system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing 364system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed 365system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed 366system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer 367system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit. 368system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit. 369system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads. 370system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores. 371system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec) 372system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ 373system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued 374system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued 375system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling 376system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph 377system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed 378system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle |
| 379system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 381system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 380system.cpu.iq.issued_per_cycle::0 238530872 29.55% 29.55% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::1 123621910 15.31% 44.86% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::2 118898033 14.73% 59.59% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::3 107819129 13.36% 72.95% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::4 89545218 11.09% 84.04% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::5 60296093 7.47% 91.51% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::6 42279085 5.24% 96.75% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::7 18940691 2.35% 99.10% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::8 7280270 0.90% 100.00% # Number of insts issued each cycle | 382system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle |
| 389system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 391system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::total 807211301 # Number of insts issued each cycle | 394system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle |
| 393system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 395system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 394system.cpu.iq.fu_full::IntAlu 11520759 42.69% 42.69% # attempts to use FU when none available 395system.cpu.iq.fu_full::IntMult 0 0.00% 42.69% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntDiv 0 0.00% 42.69% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.69% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.69% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.69% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMult 0 0.00% 42.69% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.69% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.69% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.69% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.69% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.69% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.69% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.69% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.69% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMult 0 0.00% 42.69% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.69% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdShift 0 0.00% 42.69% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.69% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.69% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.69% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.69% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.69% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.69% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.69% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.69% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.69% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.69% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.69% # attempts to use FU when none available 423system.cpu.iq.fu_full::MemRead 12368193 45.83% 88.52% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemWrite 3098262 11.48% 100.00% # attempts to use FU when none available | 396system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available |
| 425system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 427system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 427system.cpu.iq.FU_type_0::No_OpClass 2718353 0.15% 0.15% # Type of FU issued 428system.cpu.iq.FU_type_0::IntAlu 1183132640 66.13% 66.28% # Type of FU issued 429system.cpu.iq.FU_type_0::IntMult 368609 0.02% 66.30% # Type of FU issued 430system.cpu.iq.FU_type_0::IntDiv 3881115 0.22% 66.52% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued | 429system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued 430system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued 431system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued 432system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued |
| 432system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued | 434system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued |
| 434system.cpu.iq.FU_type_0::FloatMult 64 0.00% 66.52% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 344 0.00% 66.52% # Type of FU issued | 436system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued |
| 436system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 449system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued | 438system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 451system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued |
| 457system.cpu.iq.FU_type_0::MemRead 428541213 23.95% 90.48% # Type of FU issued 458system.cpu.iq.FU_type_0::MemWrite 170395732 9.52% 100.00% # Type of FU issued | 459system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued 460system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued |
| 459system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 461system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 461system.cpu.iq.FU_type_0::total 1789038207 # Type of FU issued 462system.cpu.iq.rate 2.215765 # Inst issue rate 463system.cpu.iq.fu_busy_cnt 26987214 # FU busy when requested 464system.cpu.iq.fu_busy_rate 0.015085 # FU busy rate (busy events/executed inst) 465system.cpu.iq.int_inst_queue_reads 4412665624 # Number of integer instruction queue reads 466system.cpu.iq.int_inst_queue_writes 2517635859 # Number of integer instruction queue writes 467system.cpu.iq.int_inst_queue_wakeup_accesses 1762385104 # Number of integer instruction queue wakeup accesses 468system.cpu.iq.fp_inst_queue_reads 29526 # Number of floating instruction queue reads 469system.cpu.iq.fp_inst_queue_writes 68682 # Number of floating instruction queue writes 470system.cpu.iq.fp_inst_queue_wakeup_accesses 5548 # Number of floating instruction queue wakeup accesses 471system.cpu.iq.int_alu_accesses 1813294148 # Number of integer alu accesses 472system.cpu.iq.fp_alu_accesses 12920 # Number of floating point alu accesses 473system.cpu.iew.lsq.thread0.forwLoads 186084957 # Number of loads that had data forwarded from stores | 463system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued 464system.cpu.iq.rate 2.214396 # Inst issue rate 465system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested 466system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst) 467system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads 468system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes 469system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses 470system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads 471system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes 472system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses 473system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses 474system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses 475system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores |
| 474system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 476system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 475system.cpu.iew.lsq.thread0.squashedLoads 123036250 # Number of loads squashed 476system.cpu.iew.lsq.thread0.ignoredResponses 211434 # Number of memory responses ignored because the instruction is squashed 477system.cpu.iew.lsq.thread0.memOrderViolation 371907 # Number of memory ordering violations 478system.cpu.iew.lsq.thread0.squashedStores 51657418 # Number of stores squashed | 477system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed 478system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed 479system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations 480system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed |
| 479system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 480system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 481system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 482system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 481system.cpu.iew.lsq.thread0.rescheduledLoads 23176 # Number of loads that were rescheduled 482system.cpu.iew.lsq.thread0.cacheBlocked 1099 # Number of times an access to memory failed due to the cache being blocked | 483system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled 484system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked |
| 483system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 485system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 484system.cpu.iew.iewSquashCycles 8890570 # Number of cycles IEW is squashing 485system.cpu.iew.iewBlockCycles 97719419 # Number of cycles IEW is blocking 486system.cpu.iew.iewUnblockCycles 6134161 # Number of cycles IEW is unblocking 487system.cpu.iew.iewDispatchedInsts 2023187408 # Number of instructions dispatched to IQ 488system.cpu.iew.iewDispSquashedInsts 375929 # Number of squashed instructions skipped by dispatch 489system.cpu.iew.iewDispLoadInsts 507138407 # Number of dispatched load instructions 490system.cpu.iew.iewDispStoreInsts 200817604 # Number of dispatched store instructions 491system.cpu.iew.iewDispNonSpecInsts 7250 # Number of dispatched non-speculative instructions 492system.cpu.iew.iewIQFullEvents 1817237 # Number of times the IQ has become full, causing a stall 493system.cpu.iew.iewLSQFullEvents 3413935 # Number of times the LSQ has become full, causing a stall 494system.cpu.iew.memOrderViolationEvents 371907 # Number of memory order violations 495system.cpu.iew.predictedTakenIncorrect 4848104 # Number of branches that were predicted taken incorrectly 496system.cpu.iew.predictedNotTakenIncorrect 4143061 # Number of branches that were predicted not taken incorrectly 497system.cpu.iew.branchMispredicts 8991165 # Number of branch mispredicts detected at execute 498system.cpu.iew.iewExecutedInsts 1770021029 # Number of executed instructions 499system.cpu.iew.iewExecLoadInsts 423153321 # Number of load instructions executed 500system.cpu.iew.iewExecSquashedInsts 19017178 # Number of squashed instructions skipped in execute | 486system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing 487system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking 488system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking 489system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ 490system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch 491system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions 492system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions 493system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions 494system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall 495system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall 496system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations 497system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly 498system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly 499system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute 500system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions 501system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed 502system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute |
| 501system.cpu.iew.exec_swp 0 # number of swp insts executed 502system.cpu.iew.exec_nop 0 # number of nop insts executed | 503system.cpu.iew.exec_swp 0 # number of swp insts executed 504system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 503system.cpu.iew.exec_refs 590346194 # number of memory reference insts executed 504system.cpu.iew.exec_branches 168990321 # Number of branches executed 505system.cpu.iew.exec_stores 167192873 # Number of stores executed 506system.cpu.iew.exec_rate 2.192212 # Inst execution rate 507system.cpu.iew.wb_sent 1766892997 # cumulative count of insts sent to commit 508system.cpu.iew.wb_count 1762390652 # cumulative count of insts written-back 509system.cpu.iew.wb_producers 1339756908 # num instructions producing a value 510system.cpu.iew.wb_consumers 2049972766 # num instructions consuming a value | 505system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed 506system.cpu.iew.exec_branches 168980249 # Number of branches executed 507system.cpu.iew.exec_stores 167188538 # Number of stores executed 508system.cpu.iew.exec_rate 2.190883 # Inst execution rate 509system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit 510system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back 511system.cpu.iew.wb_producers 1339663552 # num instructions producing a value 512system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value |
| 511system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 513system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 512system.cpu.iew.wb_rate 2.182762 # insts written-back per cycle 513system.cpu.iew.wb_fanout 0.653549 # average fanout of values written-back | 514system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back |
| 514system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 516system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 515system.cpu.commit.commitSquashedInsts 494260386 # The number of squashed insts skipped by commit | 517system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit |
| 516system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 518system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 517system.cpu.commit.branchMispredicts 8618895 # The number of times a branch was mispredicted 518system.cpu.commit.committed_per_cycle::samples 739988037 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::mean 2.066234 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::stdev 2.575521 # Number of insts commited each cycle | 519system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted 520system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle |
| 521system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 523system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 522system.cpu.commit.committed_per_cycle::0 275878158 37.28% 37.28% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::1 172126899 23.26% 60.54% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::2 55937459 7.56% 68.10% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::3 86300571 11.66% 79.76% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::4 25876597 3.50% 83.26% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::5 26568843 3.59% 86.85% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::6 9870767 1.33% 88.19% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::7 8919978 1.21% 89.39% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::8 78508765 10.61% 100.00% # Number of insts commited each cycle | 524system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle |
| 531system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 533system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 534system.cpu.commit.committed_per_cycle::total 739988037 # Number of insts commited each cycle | 536system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle |
| 535system.cpu.commit.committedInsts 826877109 # Number of instructions committed 536system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 537system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 538system.cpu.commit.refs 533262343 # Number of memory references committed 539system.cpu.commit.loads 384102157 # Number of loads committed 540system.cpu.commit.membars 0 # Number of memory barriers committed 541system.cpu.commit.branches 149758583 # Number of branches committed 542system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 572system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 576system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction | 537system.cpu.commit.committedInsts 826877109 # Number of instructions committed 538system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 539system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 540system.cpu.commit.refs 533262343 # Number of memory references committed 541system.cpu.commit.loads 384102157 # Number of loads committed 542system.cpu.commit.membars 0 # Number of memory barriers committed 543system.cpu.commit.branches 149758583 # Number of branches committed 544system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 574system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 577system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 578system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 581system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction |
| 580system.cpu.commit.bw_lim_events 78508765 # number cycles where commit BW limit reached 581system.cpu.rob.rob_reads 2684728359 # The number of ROB reads 582system.cpu.rob.rob_writes 4113896609 # The number of ROB writes 583system.cpu.timesIdled 2328 # Number of times that the entire CPU went into an idle state and unscheduled itself 584system.cpu.idleCycles 201987 # Total number of cycles that the CPU has spent unscheduled due to idling | 582system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached 583system.cpu.rob.rob_reads 2685200393 # The number of ROB reads 584system.cpu.rob.rob_writes 4113829657 # The number of ROB writes 585system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself 586system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 585system.cpu.committedInsts 826877109 # Number of Instructions Simulated 586system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated | 587system.cpu.committedInsts 826877109 # Number of Instructions Simulated 588system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated |
| 587system.cpu.cpi 0.976461 # CPI: Cycles Per Instruction 588system.cpu.cpi_total 0.976461 # CPI: Total CPI of All Threads 589system.cpu.ipc 1.024106 # IPC: Instructions Per Cycle 590system.cpu.ipc_total 1.024106 # IPC: Total IPC of All Threads 591system.cpu.int_regfile_reads 2722667059 # number of integer regfile reads 592system.cpu.int_regfile_writes 1435857659 # number of integer regfile writes 593system.cpu.fp_regfile_reads 5817 # number of floating regfile reads 594system.cpu.fp_regfile_writes 496 # number of floating regfile writes 595system.cpu.cc_regfile_reads 596670071 # number of cc regfile reads 596system.cpu.cc_regfile_writes 405476387 # number of cc regfile writes 597system.cpu.misc_regfile_reads 971632449 # number of misc regfile reads | 589system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction 590system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads 591system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle 592system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads 593system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads 594system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes 595system.cpu.fp_regfile_reads 5969 # number of floating regfile reads 596system.cpu.fp_regfile_writes 521 # number of floating regfile writes 597system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads 598system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes 599system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads |
| 598system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 600system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 599system.cpu.dcache.tags.replacements 2530789 # number of replacements 600system.cpu.dcache.tags.tagsinuse 4087.813367 # Cycle average of tags in use 601system.cpu.dcache.tags.total_refs 381875640 # Total number of references to valid blocks. 602system.cpu.dcache.tags.sampled_refs 2534885 # Sample count of references to valid blocks. 603system.cpu.dcache.tags.avg_refs 150.648112 # Average number of references to valid blocks. | 601system.cpu.dcache.tags.replacements 2530897 # number of replacements 602system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks. 604system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks. 605system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks. |
| 604system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. | 606system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. |
| 605system.cpu.dcache.tags.occ_blocks::cpu.data 4087.813367 # Average occupied blocks per requestor 606system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy 607system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy | 607system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor 608system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy |
| 608system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 610system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 609system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::3 3172 # Occupied blocks per task id | 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 613system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id 614system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id |
| 613system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 615system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 614system.cpu.dcache.tags.tag_accesses 772839713 # Number of tag accesses 615system.cpu.dcache.tags.data_accesses 772839713 # Number of data accesses 616system.cpu.dcache.ReadReq_hits::cpu.data 233227342 # number of ReadReq hits 617system.cpu.dcache.ReadReq_hits::total 233227342 # number of ReadReq hits 618system.cpu.dcache.WriteReq_hits::cpu.data 148173773 # number of WriteReq hits 619system.cpu.dcache.WriteReq_hits::total 148173773 # number of WriteReq hits 620system.cpu.dcache.demand_hits::cpu.data 381401115 # number of demand (read+write) hits 621system.cpu.dcache.demand_hits::total 381401115 # number of demand (read+write) hits 622system.cpu.dcache.overall_hits::cpu.data 381401115 # number of overall hits 623system.cpu.dcache.overall_hits::total 381401115 # number of overall hits 624system.cpu.dcache.ReadReq_misses::cpu.data 2764870 # number of ReadReq misses 625system.cpu.dcache.ReadReq_misses::total 2764870 # number of ReadReq misses 626system.cpu.dcache.WriteReq_misses::cpu.data 986429 # number of WriteReq misses 627system.cpu.dcache.WriteReq_misses::total 986429 # number of WriteReq misses 628system.cpu.dcache.demand_misses::cpu.data 3751299 # number of demand (read+write) misses 629system.cpu.dcache.demand_misses::total 3751299 # number of demand (read+write) misses 630system.cpu.dcache.overall_misses::cpu.data 3751299 # number of overall misses 631system.cpu.dcache.overall_misses::total 3751299 # number of overall misses 632system.cpu.dcache.ReadReq_miss_latency::cpu.data 58802289500 # number of ReadReq miss cycles 633system.cpu.dcache.ReadReq_miss_latency::total 58802289500 # number of ReadReq miss cycles 634system.cpu.dcache.WriteReq_miss_latency::cpu.data 31059853996 # number of WriteReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::total 31059853996 # number of WriteReq miss cycles 636system.cpu.dcache.demand_miss_latency::cpu.data 89862143496 # number of demand (read+write) miss cycles 637system.cpu.dcache.demand_miss_latency::total 89862143496 # number of demand (read+write) miss cycles 638system.cpu.dcache.overall_miss_latency::cpu.data 89862143496 # number of overall miss cycles 639system.cpu.dcache.overall_miss_latency::total 89862143496 # number of overall miss cycles 640system.cpu.dcache.ReadReq_accesses::cpu.data 235992212 # number of ReadReq accesses(hits+misses) 641system.cpu.dcache.ReadReq_accesses::total 235992212 # number of ReadReq accesses(hits+misses) | 616system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses 617system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses 618system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits 619system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits 620system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits 621system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits 622system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits 623system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits 624system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits 625system.cpu.dcache.overall_hits::total 381356978 # number of overall hits 626system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses 627system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses 628system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses 629system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses 630system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses 631system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses 632system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses 633system.cpu.dcache.overall_misses::total 3761732 # number of overall misses 634system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles 635system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles 637system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles 638system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles 639system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles 640system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles 641system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles 642system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses) |
| 642system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) | 644system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) |
| 644system.cpu.dcache.demand_accesses::cpu.data 385152414 # number of demand (read+write) accesses 645system.cpu.dcache.demand_accesses::total 385152414 # number of demand (read+write) accesses 646system.cpu.dcache.overall_accesses::cpu.data 385152414 # number of overall (read+write) accesses 647system.cpu.dcache.overall_accesses::total 385152414 # number of overall (read+write) accesses 648system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011716 # miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_miss_rate::total 0.011716 # miss rate for ReadReq accesses 650system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses 652system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses 653system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses 654system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses 655system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses 656system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21267.650739 # average ReadReq miss latency 657system.cpu.dcache.ReadReq_avg_miss_latency::total 21267.650739 # average ReadReq miss latency 658system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31487.166330 # average WriteReq miss latency 659system.cpu.dcache.WriteReq_avg_miss_latency::total 31487.166330 # average WriteReq miss latency 660system.cpu.dcache.demand_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency 661system.cpu.dcache.demand_avg_miss_latency::total 23954.940274 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::total 23954.940274 # average overall miss latency 664system.cpu.dcache.blocked_cycles::no_mshrs 9795 # number of cycles access was blocked 665system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_mshrs 1045 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.373206 # average number of cycles each access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked | 646system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses 647system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses 648system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses 649system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses 650system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses 654system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses 655system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses 656system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses 657system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency 659system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency 661system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency 662system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency 663system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency 665system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency 666system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked 667system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked 668system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked 669system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 670system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked 671system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked |
| 670system.cpu.dcache.fast_writes 0 # number of fast writes performed 671system.cpu.dcache.cache_copies 0 # number of cache copies performed | 672system.cpu.dcache.fast_writes 0 # number of fast writes performed 673system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 672system.cpu.dcache.writebacks::writebacks 2330774 # number of writebacks 673system.cpu.dcache.writebacks::total 2330774 # number of writebacks 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000095 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 1000095 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19339 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 19339 # number of WriteReq MSHR hits 678system.cpu.dcache.demand_mshr_hits::cpu.data 1019434 # number of demand (read+write) MSHR hits 679system.cpu.dcache.demand_mshr_hits::total 1019434 # number of demand (read+write) MSHR hits 680system.cpu.dcache.overall_mshr_hits::cpu.data 1019434 # number of overall MSHR hits 681system.cpu.dcache.overall_mshr_hits::total 1019434 # number of overall MSHR hits 682system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764775 # number of ReadReq MSHR misses 683system.cpu.dcache.ReadReq_mshr_misses::total 1764775 # number of ReadReq MSHR misses 684system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967090 # number of WriteReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::total 967090 # number of WriteReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.data 2731865 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 2731865 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 2731865 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 2731865 # number of overall MSHR misses 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33541518000 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 33541518000 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29840523997 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 29840523997 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63382041997 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::total 63382041997 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63382041997 # number of overall MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::total 63382041997 # number of overall MSHR miss cycles 698system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007478 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007478 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19006.115794 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19006.115794 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30855.994785 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30855.994785 # average WriteReq mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency | 674system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks 675system.cpu.dcache.writebacks::total 2330787 # number of writebacks 676system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits 677system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits 679system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits 680system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits 681system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits 682system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits 683system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits 684system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses 685system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses 688system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses 705system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses 706system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses 707system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency |
| 714system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 716system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 715system.cpu.icache.tags.replacements 6640 # number of replacements 716system.cpu.icache.tags.tagsinuse 1037.923261 # Cycle average of tags in use 717system.cpu.icache.tags.total_refs 170565267 # Total number of references to valid blocks. 718system.cpu.icache.tags.sampled_refs 8248 # Sample count of references to valid blocks. 719system.cpu.icache.tags.avg_refs 20679.591052 # Average number of references to valid blocks. | 717system.cpu.icache.tags.replacements 6655 # number of replacements 718system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use 719system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks. 720system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks. 721system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks. |
| 720system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 722system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 721system.cpu.icache.tags.occ_blocks::cpu.inst 1037.923261 # Average occupied blocks per requestor 722system.cpu.icache.tags.occ_percent::cpu.inst 0.506798 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_percent::total 0.506798 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id | 723system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor 724system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy 725system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy 726system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 730system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id |
| 729system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id | 731system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id |
| 730system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id 731system.cpu.icache.tags.tag_accesses 341757570 # Number of tag accesses 732system.cpu.icache.tags.data_accesses 341757570 # Number of data accesses 733system.cpu.icache.ReadReq_hits::cpu.inst 170568161 # number of ReadReq hits 734system.cpu.icache.ReadReq_hits::total 170568161 # number of ReadReq hits 735system.cpu.icache.demand_hits::cpu.inst 170568161 # number of demand (read+write) hits 736system.cpu.icache.demand_hits::total 170568161 # number of demand (read+write) hits 737system.cpu.icache.overall_hits::cpu.inst 170568161 # number of overall hits 738system.cpu.icache.overall_hits::total 170568161 # number of overall hits 739system.cpu.icache.ReadReq_misses::cpu.inst 207953 # number of ReadReq misses 740system.cpu.icache.ReadReq_misses::total 207953 # number of ReadReq misses 741system.cpu.icache.demand_misses::cpu.inst 207953 # number of demand (read+write) misses 742system.cpu.icache.demand_misses::total 207953 # number of demand (read+write) misses 743system.cpu.icache.overall_misses::cpu.inst 207953 # number of overall misses 744system.cpu.icache.overall_misses::total 207953 # number of overall misses 745system.cpu.icache.ReadReq_miss_latency::cpu.inst 1300977000 # number of ReadReq miss cycles 746system.cpu.icache.ReadReq_miss_latency::total 1300977000 # number of ReadReq miss cycles 747system.cpu.icache.demand_miss_latency::cpu.inst 1300977000 # number of demand (read+write) miss cycles 748system.cpu.icache.demand_miss_latency::total 1300977000 # number of demand (read+write) miss cycles 749system.cpu.icache.overall_miss_latency::cpu.inst 1300977000 # number of overall miss cycles 750system.cpu.icache.overall_miss_latency::total 1300977000 # number of overall miss cycles 751system.cpu.icache.ReadReq_accesses::cpu.inst 170776114 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.ReadReq_accesses::total 170776114 # number of ReadReq accesses(hits+misses) 753system.cpu.icache.demand_accesses::cpu.inst 170776114 # number of demand (read+write) accesses 754system.cpu.icache.demand_accesses::total 170776114 # number of demand (read+write) accesses 755system.cpu.icache.overall_accesses::cpu.inst 170776114 # number of overall (read+write) accesses 756system.cpu.icache.overall_accesses::total 170776114 # number of overall (read+write) accesses 757system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001218 # miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_miss_rate::total 0.001218 # miss rate for ReadReq accesses 759system.cpu.icache.demand_miss_rate::cpu.inst 0.001218 # miss rate for demand accesses 760system.cpu.icache.demand_miss_rate::total 0.001218 # miss rate for demand accesses 761system.cpu.icache.overall_miss_rate::cpu.inst 0.001218 # miss rate for overall accesses 762system.cpu.icache.overall_miss_rate::total 0.001218 # miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6256.110756 # average ReadReq miss latency 764system.cpu.icache.ReadReq_avg_miss_latency::total 6256.110756 # average ReadReq miss latency 765system.cpu.icache.demand_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency 766system.cpu.icache.demand_avg_miss_latency::total 6256.110756 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency 768system.cpu.icache.overall_avg_miss_latency::total 6256.110756 # average overall miss latency 769system.cpu.icache.blocked_cycles::no_mshrs 718 # number of cycles access was blocked | 732system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id 733system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses 734system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses 735system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits 736system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits 737system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits 738system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits 739system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits 740system.cpu.icache.overall_hits::total 170580521 # number of overall hits 741system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses 742system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses 743system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses 744system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses 745system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses 746system.cpu.icache.overall_misses::total 208882 # number of overall misses 747system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles 748system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles 749system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles 750system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles 751system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles 752system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles 753system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses) 754system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses) 755system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses 756system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses 757system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses 758system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses 759system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses 761system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses 762system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses 763system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses 764system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency 766system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency 767system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency 768system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency 769system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency 770system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency 771system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked |
| 770system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked 772system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 772system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 773system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked 774system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 773system.cpu.icache.avg_blocked_cycles::no_mshrs 59.833333 # average number of cycles each access was blocked | 775system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked |
| 774system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.icache.fast_writes 0 # number of fast writes performed 776system.cpu.icache.cache_copies 0 # number of cache copies performed | 776system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 777system.cpu.icache.fast_writes 0 # number of fast writes performed 778system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 777system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2609 # number of ReadReq MSHR hits 778system.cpu.icache.ReadReq_mshr_hits::total 2609 # number of ReadReq MSHR hits 779system.cpu.icache.demand_mshr_hits::cpu.inst 2609 # number of demand (read+write) MSHR hits 780system.cpu.icache.demand_mshr_hits::total 2609 # number of demand (read+write) MSHR hits 781system.cpu.icache.overall_mshr_hits::cpu.inst 2609 # number of overall MSHR hits 782system.cpu.icache.overall_mshr_hits::total 2609 # number of overall MSHR hits 783system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205344 # number of ReadReq MSHR misses 784system.cpu.icache.ReadReq_mshr_misses::total 205344 # number of ReadReq MSHR misses 785system.cpu.icache.demand_mshr_misses::cpu.inst 205344 # number of demand (read+write) MSHR misses 786system.cpu.icache.demand_mshr_misses::total 205344 # number of demand (read+write) MSHR misses 787system.cpu.icache.overall_mshr_misses::cpu.inst 205344 # number of overall MSHR misses 788system.cpu.icache.overall_mshr_misses::total 205344 # number of overall MSHR misses 789system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 976991000 # number of ReadReq MSHR miss cycles 790system.cpu.icache.ReadReq_mshr_miss_latency::total 976991000 # number of ReadReq MSHR miss cycles 791system.cpu.icache.demand_mshr_miss_latency::cpu.inst 976991000 # number of demand (read+write) MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::total 976991000 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.overall_mshr_miss_latency::cpu.inst 976991000 # number of overall MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::total 976991000 # number of overall MSHR miss cycles 795system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses 796system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses 797system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses 798system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses 799system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses 800system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses 801system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4757.825892 # average ReadReq mshr miss latency 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4757.825892 # average ReadReq mshr miss latency 803system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency 805system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency | 779system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits 780system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits 781system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits 782system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits 783system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits 784system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits 785system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses 786system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses 787system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses 788system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses 789system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses 790system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses 791system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles 792system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles 796system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles 797system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses 798system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses 799system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses 800system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses 801system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses 802system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency 804system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency 806system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency 808system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency |
| 807system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 809system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 808system.cpu.l2cache.tags.replacements 353471 # number of replacements 809system.cpu.l2cache.tags.tagsinuse 29618.497788 # Cycle average of tags in use 810system.cpu.l2cache.tags.total_refs 3892615 # Total number of references to valid blocks. 811system.cpu.l2cache.tags.sampled_refs 385807 # Sample count of references to valid blocks. 812system.cpu.l2cache.tags.avg_refs 10.089540 # Average number of references to valid blocks. 813system.cpu.l2cache.tags.warmup_cycle 189374171500 # Cycle when the warmup percentage was hit. 814system.cpu.l2cache.tags.occ_blocks::writebacks 20946.463818 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.310071 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.data 8431.723899 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_percent::writebacks 0.639235 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007334 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.data 0.257316 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::total 0.903885 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_task_id_blocks::1024 32336 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id | 810system.cpu.l2cache.tags.replacements 353544 # number of replacements 811system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use 812system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks. 813system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks. 814system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks. 815system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit. 816system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor 819system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_percent::total 0.903914 # Average percentage of cache occupancy 823system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id |
| 823system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id | 825system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id |
| 824system.cpu.l2cache.tags.age_task_id_blocks_1024::2 218 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13380 # Occupied blocks per task id | 826system.cpu.l2cache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13379 # Occupied blocks per task id |
| 826system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18648 # Occupied blocks per task id | 828system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18648 # Occupied blocks per task id |
| 827system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986816 # Percentage of cache occupancy per task id 828system.cpu.l2cache.tags.tag_accesses 43290247 # Number of tag accesses 829system.cpu.l2cache.tags.data_accesses 43290247 # Number of data accesses 830system.cpu.l2cache.Writeback_hits::writebacks 2330774 # number of Writeback hits 831system.cpu.l2cache.Writeback_hits::total 2330774 # number of Writeback hits 832system.cpu.l2cache.UpgradeReq_hits::cpu.data 1839 # number of UpgradeReq hits 833system.cpu.l2cache.UpgradeReq_hits::total 1839 # number of UpgradeReq hits 834system.cpu.l2cache.ReadExReq_hits::cpu.data 563945 # number of ReadExReq hits 835system.cpu.l2cache.ReadExReq_hits::total 563945 # number of ReadExReq hits 836system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4854 # number of ReadCleanReq hits 837system.cpu.l2cache.ReadCleanReq_hits::total 4854 # number of ReadCleanReq hits 838system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588121 # number of ReadSharedReq hits 839system.cpu.l2cache.ReadSharedReq_hits::total 1588121 # number of ReadSharedReq hits 840system.cpu.l2cache.demand_hits::cpu.inst 4854 # number of demand (read+write) hits 841system.cpu.l2cache.demand_hits::cpu.data 2152066 # number of demand (read+write) hits 842system.cpu.l2cache.demand_hits::total 2156920 # number of demand (read+write) hits 843system.cpu.l2cache.overall_hits::cpu.inst 4854 # number of overall hits 844system.cpu.l2cache.overall_hits::cpu.data 2152066 # number of overall hits 845system.cpu.l2cache.overall_hits::total 2156920 # number of overall hits 846system.cpu.l2cache.UpgradeReq_misses::cpu.data 195142 # number of UpgradeReq misses 847system.cpu.l2cache.UpgradeReq_misses::total 195142 # number of UpgradeReq misses 848system.cpu.l2cache.ReadExReq_misses::cpu.data 206554 # number of ReadExReq misses 849system.cpu.l2cache.ReadExReq_misses::total 206554 # number of ReadExReq misses 850system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3382 # number of ReadCleanReq misses 851system.cpu.l2cache.ReadCleanReq_misses::total 3382 # number of ReadCleanReq misses 852system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176265 # number of ReadSharedReq misses 853system.cpu.l2cache.ReadSharedReq_misses::total 176265 # number of ReadSharedReq misses 854system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses 855system.cpu.l2cache.demand_misses::cpu.data 382819 # number of demand (read+write) misses 856system.cpu.l2cache.demand_misses::total 386201 # number of demand (read+write) misses 857system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses 858system.cpu.l2cache.overall_misses::cpu.data 382819 # number of overall misses 859system.cpu.l2cache.overall_misses::total 386201 # number of overall misses 860system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13466000 # number of UpgradeReq miss cycles 861system.cpu.l2cache.UpgradeReq_miss_latency::total 13466000 # number of UpgradeReq miss cycles 862system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16374024500 # number of ReadExReq miss cycles 863system.cpu.l2cache.ReadExReq_miss_latency::total 16374024500 # number of ReadExReq miss cycles 864system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275872500 # number of ReadCleanReq miss cycles 865system.cpu.l2cache.ReadCleanReq_miss_latency::total 275872500 # number of ReadCleanReq miss cycles 866system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14180580000 # number of ReadSharedReq miss cycles 867system.cpu.l2cache.ReadSharedReq_miss_latency::total 14180580000 # number of ReadSharedReq miss cycles 868system.cpu.l2cache.demand_miss_latency::cpu.inst 275872500 # number of demand (read+write) miss cycles 869system.cpu.l2cache.demand_miss_latency::cpu.data 30554604500 # number of demand (read+write) miss cycles 870system.cpu.l2cache.demand_miss_latency::total 30830477000 # number of demand (read+write) miss cycles 871system.cpu.l2cache.overall_miss_latency::cpu.inst 275872500 # number of overall miss cycles 872system.cpu.l2cache.overall_miss_latency::cpu.data 30554604500 # number of overall miss cycles 873system.cpu.l2cache.overall_miss_latency::total 30830477000 # number of overall miss cycles 874system.cpu.l2cache.Writeback_accesses::writebacks 2330774 # number of Writeback accesses(hits+misses) 875system.cpu.l2cache.Writeback_accesses::total 2330774 # number of Writeback accesses(hits+misses) 876system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196981 # number of UpgradeReq accesses(hits+misses) 877system.cpu.l2cache.UpgradeReq_accesses::total 196981 # number of UpgradeReq accesses(hits+misses) 878system.cpu.l2cache.ReadExReq_accesses::cpu.data 770499 # number of ReadExReq accesses(hits+misses) 879system.cpu.l2cache.ReadExReq_accesses::total 770499 # number of ReadExReq accesses(hits+misses) 880system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8236 # number of ReadCleanReq accesses(hits+misses) 881system.cpu.l2cache.ReadCleanReq_accesses::total 8236 # number of ReadCleanReq accesses(hits+misses) 882system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764386 # number of ReadSharedReq accesses(hits+misses) 883system.cpu.l2cache.ReadSharedReq_accesses::total 1764386 # number of ReadSharedReq accesses(hits+misses) 884system.cpu.l2cache.demand_accesses::cpu.inst 8236 # number of demand (read+write) accesses 885system.cpu.l2cache.demand_accesses::cpu.data 2534885 # number of demand (read+write) accesses 886system.cpu.l2cache.demand_accesses::total 2543121 # number of demand (read+write) accesses 887system.cpu.l2cache.overall_accesses::cpu.inst 8236 # number of overall (read+write) accesses 888system.cpu.l2cache.overall_accesses::cpu.data 2534885 # number of overall (read+write) accesses 889system.cpu.l2cache.overall_accesses::total 2543121 # number of overall (read+write) accesses 890system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990664 # miss rate for UpgradeReq accesses 891system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990664 # miss rate for UpgradeReq accesses 892system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268078 # miss rate for ReadExReq accesses 893system.cpu.l2cache.ReadExReq_miss_rate::total 0.268078 # miss rate for ReadExReq accesses 894system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.410636 # miss rate for ReadCleanReq accesses 895system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.410636 # miss rate for ReadCleanReq accesses 896system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099902 # miss rate for ReadSharedReq accesses 897system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099902 # miss rate for ReadSharedReq accesses 898system.cpu.l2cache.demand_miss_rate::cpu.inst 0.410636 # miss rate for demand accesses 899system.cpu.l2cache.demand_miss_rate::cpu.data 0.151020 # miss rate for demand accesses 900system.cpu.l2cache.demand_miss_rate::total 0.151861 # miss rate for demand accesses 901system.cpu.l2cache.overall_miss_rate::cpu.inst 0.410636 # miss rate for overall accesses 902system.cpu.l2cache.overall_miss_rate::cpu.data 0.151020 # miss rate for overall accesses 903system.cpu.l2cache.overall_miss_rate::total 0.151861 # miss rate for overall accesses 904system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.006160 # average UpgradeReq miss latency 905system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.006160 # average UpgradeReq miss latency 906system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79272.367032 # average ReadExReq miss latency 907system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79272.367032 # average ReadExReq miss latency 908system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81570.816085 # average ReadCleanReq miss latency 909system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81570.816085 # average ReadCleanReq miss latency 910system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80450.344652 # average ReadSharedReq miss latency 911system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80450.344652 # average ReadSharedReq miss latency 912system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81570.816085 # average overall miss latency 913system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79814.754492 # average overall miss latency 914system.cpu.l2cache.demand_avg_miss_latency::total 79830.132496 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81570.816085 # average overall miss latency 916system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79814.754492 # average overall miss latency 917system.cpu.l2cache.overall_avg_miss_latency::total 79830.132496 # average overall miss latency | 829system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986633 # Percentage of cache occupancy per task id 830system.cpu.l2cache.tags.tag_accesses 43295860 # Number of tag accesses 831system.cpu.l2cache.tags.data_accesses 43295860 # Number of data accesses 832system.cpu.l2cache.Writeback_hits::writebacks 2330787 # number of Writeback hits 833system.cpu.l2cache.Writeback_hits::total 2330787 # number of Writeback hits 834system.cpu.l2cache.UpgradeReq_hits::cpu.data 1834 # number of UpgradeReq hits 835system.cpu.l2cache.UpgradeReq_hits::total 1834 # number of UpgradeReq hits 836system.cpu.l2cache.ReadExReq_hits::cpu.data 563915 # number of ReadExReq hits 837system.cpu.l2cache.ReadExReq_hits::total 563915 # number of ReadExReq hits 838system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4843 # number of ReadCleanReq hits 839system.cpu.l2cache.ReadCleanReq_hits::total 4843 # number of ReadCleanReq hits 840system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588207 # number of ReadSharedReq hits 841system.cpu.l2cache.ReadSharedReq_hits::total 1588207 # number of ReadSharedReq hits 842system.cpu.l2cache.demand_hits::cpu.inst 4843 # number of demand (read+write) hits 843system.cpu.l2cache.demand_hits::cpu.data 2152122 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::total 2156965 # number of demand (read+write) hits 845system.cpu.l2cache.overall_hits::cpu.inst 4843 # number of overall hits 846system.cpu.l2cache.overall_hits::cpu.data 2152122 # number of overall hits 847system.cpu.l2cache.overall_hits::total 2156965 # number of overall hits 848system.cpu.l2cache.UpgradeReq_misses::cpu.data 196078 # number of UpgradeReq misses 849system.cpu.l2cache.UpgradeReq_misses::total 196078 # number of UpgradeReq misses 850system.cpu.l2cache.ReadExReq_misses::cpu.data 206573 # number of ReadExReq misses 851system.cpu.l2cache.ReadExReq_misses::total 206573 # number of ReadExReq misses 852system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3410 # number of ReadCleanReq misses 853system.cpu.l2cache.ReadCleanReq_misses::total 3410 # number of ReadCleanReq misses 854system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176298 # number of ReadSharedReq misses 855system.cpu.l2cache.ReadSharedReq_misses::total 176298 # number of ReadSharedReq misses 856system.cpu.l2cache.demand_misses::cpu.inst 3410 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.data 382871 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::total 386281 # number of demand (read+write) misses 859system.cpu.l2cache.overall_misses::cpu.inst 3410 # number of overall misses 860system.cpu.l2cache.overall_misses::cpu.data 382871 # number of overall misses 861system.cpu.l2cache.overall_misses::total 386281 # number of overall misses 862system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13890000 # number of UpgradeReq miss cycles 863system.cpu.l2cache.UpgradeReq_miss_latency::total 13890000 # number of UpgradeReq miss cycles 864system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16378927500 # number of ReadExReq miss cycles 865system.cpu.l2cache.ReadExReq_miss_latency::total 16378927500 # number of ReadExReq miss cycles 866system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 280136500 # number of ReadCleanReq miss cycles 867system.cpu.l2cache.ReadCleanReq_miss_latency::total 280136500 # number of ReadCleanReq miss cycles 868system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14178823000 # number of ReadSharedReq miss cycles 869system.cpu.l2cache.ReadSharedReq_miss_latency::total 14178823000 # number of ReadSharedReq miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.inst 280136500 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.data 30557750500 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::total 30837887000 # number of demand (read+write) miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.inst 280136500 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.data 30557750500 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::total 30837887000 # number of overall miss cycles 876system.cpu.l2cache.Writeback_accesses::writebacks 2330787 # number of Writeback accesses(hits+misses) 877system.cpu.l2cache.Writeback_accesses::total 2330787 # number of Writeback accesses(hits+misses) 878system.cpu.l2cache.UpgradeReq_accesses::cpu.data 197912 # number of UpgradeReq accesses(hits+misses) 879system.cpu.l2cache.UpgradeReq_accesses::total 197912 # number of UpgradeReq accesses(hits+misses) 880system.cpu.l2cache.ReadExReq_accesses::cpu.data 770488 # number of ReadExReq accesses(hits+misses) 881system.cpu.l2cache.ReadExReq_accesses::total 770488 # number of ReadExReq accesses(hits+misses) 882system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8253 # number of ReadCleanReq accesses(hits+misses) 883system.cpu.l2cache.ReadCleanReq_accesses::total 8253 # number of ReadCleanReq accesses(hits+misses) 884system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764505 # number of ReadSharedReq accesses(hits+misses) 885system.cpu.l2cache.ReadSharedReq_accesses::total 1764505 # number of ReadSharedReq accesses(hits+misses) 886system.cpu.l2cache.demand_accesses::cpu.inst 8253 # number of demand (read+write) accesses 887system.cpu.l2cache.demand_accesses::cpu.data 2534993 # number of demand (read+write) accesses 888system.cpu.l2cache.demand_accesses::total 2543246 # number of demand (read+write) accesses 889system.cpu.l2cache.overall_accesses::cpu.inst 8253 # number of overall (read+write) accesses 890system.cpu.l2cache.overall_accesses::cpu.data 2534993 # number of overall (read+write) accesses 891system.cpu.l2cache.overall_accesses::total 2543246 # number of overall (read+write) accesses 892system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990733 # miss rate for UpgradeReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990733 # miss rate for UpgradeReq accesses 894system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268107 # miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::total 0.268107 # miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.413183 # miss rate for ReadCleanReq accesses 897system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.413183 # miss rate for ReadCleanReq accesses 898system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099914 # miss rate for ReadSharedReq accesses 899system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099914 # miss rate for ReadSharedReq accesses 900system.cpu.l2cache.demand_miss_rate::cpu.inst 0.413183 # miss rate for demand accesses 901system.cpu.l2cache.demand_miss_rate::cpu.data 0.151034 # miss rate for demand accesses 902system.cpu.l2cache.demand_miss_rate::total 0.151885 # miss rate for demand accesses 903system.cpu.l2cache.overall_miss_rate::cpu.inst 0.413183 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::cpu.data 0.151034 # miss rate for overall accesses 905system.cpu.l2cache.overall_miss_rate::total 0.151885 # miss rate for overall accesses 906system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 70.839156 # average UpgradeReq miss latency 907system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 70.839156 # average UpgradeReq miss latency 908system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79288.810735 # average ReadExReq miss latency 909system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79288.810735 # average ReadExReq miss latency 910system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82151.466276 # average ReadCleanReq miss latency 911system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82151.466276 # average ReadCleanReq miss latency 912system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80425.319629 # average ReadSharedReq miss latency 913system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80425.319629 # average ReadSharedReq miss latency 914system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82151.466276 # average overall miss latency 915system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79812.131240 # average overall miss latency 916system.cpu.l2cache.demand_avg_miss_latency::total 79832.782353 # average overall miss latency 917system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82151.466276 # average overall miss latency 918system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79812.131240 # average overall miss latency 919system.cpu.l2cache.overall_avg_miss_latency::total 79832.782353 # average overall miss latency |
| 918system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu.l2cache.fast_writes 0 # number of fast writes performed 925system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 920system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 925system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu.l2cache.fast_writes 0 # number of fast writes performed 927system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 926system.cpu.l2cache.writebacks::writebacks 294833 # number of writebacks 927system.cpu.l2cache.writebacks::total 294833 # number of writebacks 928system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 929system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 930system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 931system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 932system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 933system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 934system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1941 # number of CleanEvict MSHR misses 935system.cpu.l2cache.CleanEvict_mshr_misses::total 1941 # number of CleanEvict MSHR misses 936system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195142 # number of UpgradeReq MSHR misses 937system.cpu.l2cache.UpgradeReq_mshr_misses::total 195142 # number of UpgradeReq MSHR misses 938system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206554 # number of ReadExReq MSHR misses 939system.cpu.l2cache.ReadExReq_mshr_misses::total 206554 # number of ReadExReq MSHR misses 940system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3381 # number of ReadCleanReq MSHR misses 941system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3381 # number of ReadCleanReq MSHR misses 942system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176265 # number of ReadSharedReq MSHR misses 943system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176265 # number of ReadSharedReq MSHR misses 944system.cpu.l2cache.demand_mshr_misses::cpu.inst 3381 # number of demand (read+write) MSHR misses 945system.cpu.l2cache.demand_mshr_misses::cpu.data 382819 # number of demand (read+write) MSHR misses 946system.cpu.l2cache.demand_mshr_misses::total 386200 # number of demand (read+write) MSHR misses 947system.cpu.l2cache.overall_mshr_misses::cpu.inst 3381 # number of overall MSHR misses 948system.cpu.l2cache.overall_mshr_misses::cpu.data 382819 # number of overall MSHR misses 949system.cpu.l2cache.overall_mshr_misses::total 386200 # number of overall MSHR misses 950system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4107801604 # number of UpgradeReq MSHR miss cycles 951system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4107801604 # number of UpgradeReq MSHR miss cycles 952system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14308484500 # number of ReadExReq MSHR miss cycles 953system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14308484500 # number of ReadExReq MSHR miss cycles 954system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 242006000 # number of ReadCleanReq MSHR miss cycles 955system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 242006000 # number of ReadCleanReq MSHR miss cycles 956system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12417930000 # number of ReadSharedReq MSHR miss cycles 957system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12417930000 # number of ReadSharedReq MSHR miss cycles 958system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 242006000 # number of demand (read+write) MSHR miss cycles 959system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26726414500 # number of demand (read+write) MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::total 26968420500 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 242006000 # number of overall MSHR miss cycles 962system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26726414500 # number of overall MSHR miss cycles 963system.cpu.l2cache.overall_mshr_miss_latency::total 26968420500 # number of overall MSHR miss cycles | 928system.cpu.l2cache.writebacks::writebacks 294838 # number of writebacks 929system.cpu.l2cache.writebacks::total 294838 # number of writebacks 930system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 931system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 932system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 933system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 934system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 935system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits 936system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1958 # number of CleanEvict MSHR misses 937system.cpu.l2cache.CleanEvict_mshr_misses::total 1958 # number of CleanEvict MSHR misses 938system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 196078 # number of UpgradeReq MSHR misses 939system.cpu.l2cache.UpgradeReq_mshr_misses::total 196078 # number of UpgradeReq MSHR misses 940system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206573 # number of ReadExReq MSHR misses 941system.cpu.l2cache.ReadExReq_mshr_misses::total 206573 # number of ReadExReq MSHR misses 942system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3408 # number of ReadCleanReq MSHR misses 943system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3408 # number of ReadCleanReq MSHR misses 944system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176298 # number of ReadSharedReq MSHR misses 945system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176298 # number of ReadSharedReq MSHR misses 946system.cpu.l2cache.demand_mshr_misses::cpu.inst 3408 # number of demand (read+write) MSHR misses 947system.cpu.l2cache.demand_mshr_misses::cpu.data 382871 # number of demand (read+write) MSHR misses 948system.cpu.l2cache.demand_mshr_misses::total 386279 # number of demand (read+write) MSHR misses 949system.cpu.l2cache.overall_mshr_misses::cpu.inst 3408 # number of overall MSHR misses 950system.cpu.l2cache.overall_mshr_misses::cpu.data 382871 # number of overall MSHR misses 951system.cpu.l2cache.overall_mshr_misses::total 386279 # number of overall MSHR misses 952system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4323708271 # number of UpgradeReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4323708271 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14313197500 # number of ReadExReq MSHR miss cycles 955system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14313197500 # number of ReadExReq MSHR miss cycles 956system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 245909500 # number of ReadCleanReq MSHR miss cycles 957system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 245909500 # number of ReadCleanReq MSHR miss cycles 958system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12415843000 # number of ReadSharedReq MSHR miss cycles 959system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12415843000 # number of ReadSharedReq MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245909500 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26729040500 # number of demand (read+write) MSHR miss cycles 962system.cpu.l2cache.demand_mshr_miss_latency::total 26974950000 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245909500 # number of overall MSHR miss cycles 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26729040500 # number of overall MSHR miss cycles 965system.cpu.l2cache.overall_mshr_miss_latency::total 26974950000 # number of overall MSHR miss cycles |
| 964system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 965system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 966system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 967system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 966system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990664 # mshr miss rate for UpgradeReq accesses 967system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990664 # mshr miss rate for UpgradeReq accesses 968system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268078 # mshr miss rate for ReadExReq accesses 969system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268078 # mshr miss rate for ReadExReq accesses 970system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for ReadCleanReq accesses 971system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.410515 # mshr miss rate for ReadCleanReq accesses 972system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099902 # mshr miss rate for ReadSharedReq accesses 973system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099902 # mshr miss rate for ReadSharedReq accesses 974system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for demand accesses 975system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for demand accesses 976system.cpu.l2cache.demand_mshr_miss_rate::total 0.151861 # mshr miss rate for demand accesses 977system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for overall accesses 978system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for overall accesses 979system.cpu.l2cache.overall_mshr_miss_rate::total 0.151861 # mshr miss rate for overall accesses 980system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21050.320300 # average UpgradeReq mshr miss latency 981system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21050.320300 # average UpgradeReq mshr miss latency 982system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69272.367032 # average ReadExReq mshr miss latency 983system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69272.367032 # average ReadExReq mshr miss latency 984system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71578.231293 # average ReadCleanReq mshr miss latency 985system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71578.231293 # average ReadCleanReq mshr miss latency 986system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70450.344652 # average ReadSharedReq mshr miss latency 987system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70450.344652 # average ReadSharedReq mshr miss latency 988system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency 989system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency 991system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency 992system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency | 968system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses 969system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses 970system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses 971system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses 972system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses 973system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses 974system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses 975system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses 976system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses 977system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses 978system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses 979system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses 980system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses 981system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency 983system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency 984system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency 986system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency 987system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency 988system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency 989system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency 991system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency 992system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency 994system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency 995system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency |
| 994system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 996system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 995system.cpu.toL2Bus.trans_dist::ReadResp 1969728 # Transaction distribution 996system.cpu.toL2Bus.trans_dist::Writeback 2625607 # Transaction distribution 997system.cpu.toL2Bus.trans_dist::CleanEvict 254220 # Transaction distribution 998system.cpu.toL2Bus.trans_dist::UpgradeReq 196981 # Transaction distribution 999system.cpu.toL2Bus.trans_dist::UpgradeResp 196981 # Transaction distribution 1000system.cpu.toL2Bus.trans_dist::ReadExReq 770499 # Transaction distribution 1001system.cpu.toL2Bus.trans_dist::ReadExResp 770499 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::ReadCleanReq 205344 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764386 # Transaction distribution 1004system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219812 # Packet count per connected master and slave (bytes) 1005system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7983854 # Packet count per connected master and slave (bytes) 1006system.cpu.toL2Bus.pkt_count::total 8203666 # Packet count per connected master and slave (bytes) 1007system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 526976 # Cumulative packet size per connected master and slave (bytes) 1008system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311402176 # Cumulative packet size per connected master and slave (bytes) 1009system.cpu.toL2Bus.pkt_size::total 311929152 # Cumulative packet size per connected master and slave (bytes) 1010system.cpu.toL2Bus.snoops 550579 # Total snoops (count) 1011system.cpu.toL2Bus.snoop_fanout::samples 5828110 # Request fanout histogram 1012system.cpu.toL2Bus.snoop_fanout::mean 1.060649 # Request fanout histogram 1013system.cpu.toL2Bus.snoop_fanout::stdev 0.238686 # Request fanout histogram | 997system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter. 998system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data. 999system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1000system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter. 1001system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1002system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1003system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution 1006system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution 1009system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution 1010system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution 1011system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution 1012system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes) 1013system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes) 1014system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes) 1015system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes) 1016system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes) 1017system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes) 1018system.cpu.toL2Bus.snoops 551588 # Total snoops (count) 1019system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram 1020system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram 1021system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram |
| 1014system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1022system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1015system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1016system.cpu.toL2Bus.snoop_fanout::1 5474639 93.94% 93.94% # Request fanout histogram 1017system.cpu.toL2Bus.snoop_fanout::2 353471 6.06% 100.00% # Request fanout histogram | 1023system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram 1024system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram 1025system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 1018system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1026system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1019system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1020system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1021system.cpu.toL2Bus.snoop_fanout::total 5828110 # Request fanout histogram 1022system.cpu.toL2Bus.reqLayer0.occupancy 5096523027 # Layer occupancy (ticks) | 1027system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1028system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1029system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram 1030system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks) |
| 1023system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) | 1031system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) |
| 1024system.cpu.toL2Bus.respLayer0.occupancy 308017990 # Layer occupancy (ticks) | 1032system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks) |
| 1025system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1033system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1026system.cpu.toL2Bus.respLayer1.occupancy 3900818077 # Layer occupancy (ticks) | 1034system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks) |
| 1027system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) | 1035system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 1028system.membus.trans_dist::ReadResp 179644 # Transaction distribution 1029system.membus.trans_dist::Writeback 294833 # Transaction distribution 1030system.membus.trans_dist::CleanEvict 57066 # Transaction distribution 1031system.membus.trans_dist::UpgradeReq 195189 # Transaction distribution 1032system.membus.trans_dist::UpgradeResp 195189 # Transaction distribution 1033system.membus.trans_dist::ReadExReq 206507 # Transaction distribution 1034system.membus.trans_dist::ReadExResp 206507 # Transaction distribution 1035system.membus.trans_dist::ReadSharedReq 179645 # Transaction distribution 1036system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514580 # Packet count per connected master and slave (bytes) 1037system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514580 # Packet count per connected master and slave (bytes) 1038system.membus.pkt_count::total 1514580 # Packet count per connected master and slave (bytes) 1039system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582976 # Cumulative packet size per connected master and slave (bytes) 1040system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43582976 # Cumulative packet size per connected master and slave (bytes) 1041system.membus.pkt_size::total 43582976 # Cumulative packet size per connected master and slave (bytes) | 1036system.membus.trans_dist::ReadResp 179703 # Transaction distribution 1037system.membus.trans_dist::Writeback 294838 # Transaction distribution 1038system.membus.trans_dist::CleanEvict 57117 # Transaction distribution 1039system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution 1040system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution 1041system.membus.trans_dist::ReadExReq 206523 # Transaction distribution 1042system.membus.trans_dist::ReadExResp 206523 # Transaction distribution 1043system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution 1044system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes) 1045system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes) 1046system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes) 1047system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes) 1048system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes) 1049system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes) |
| 1042system.membus.snoops 0 # Total snoops (count) | 1050system.membus.snoops 0 # Total snoops (count) |
| 1043system.membus.snoop_fanout::samples 933240 # Request fanout histogram | 1051system.membus.snoop_fanout::samples 934311 # Request fanout histogram |
| 1044system.membus.snoop_fanout::mean 0 # Request fanout histogram 1045system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1046system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1052system.membus.snoop_fanout::mean 0 # Request fanout histogram 1053system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1054system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1047system.membus.snoop_fanout::0 933240 100.00% 100.00% # Request fanout histogram | 1055system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram |
| 1048system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1049system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1050system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1051system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1056system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1057system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1058system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1059system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1052system.membus.snoop_fanout::total 933240 # Request fanout histogram 1053system.membus.reqLayer0.occupancy 2243803396 # Layer occupancy (ticks) | 1060system.membus.snoop_fanout::total 934311 # Request fanout histogram 1061system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks) |
| 1054system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) | 1062system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 1055system.membus.respLayer1.occupancy 2433027599 # Layer occupancy (ticks) | 1063system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks) |
| 1056system.membus.respLayer1.utilization 0.6 # Layer utilization (%) 1057 1058---------- End Simulation Statistics ---------- | 1064system.membus.respLayer1.utilization 0.6 # Layer utilization (%) 1065 1066---------- End Simulation Statistics ---------- |