| stats.txt (10892:bd37e25fb3b7) | stats.txt (10901:8cfa8dac39fe) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.417249 # Number of seconds simulated 4sim_ticks 417248608500 # Number of ticks simulated 5final_tick 417248608500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.417251 # Number of seconds simulated 4sim_ticks 417250627500 # Number of ticks simulated 5final_tick 417250627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 95567 # Simulator instruction rate (inst/s) 8host_op_rate 176715 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48224052 # Simulator tick rate (ticks/s) 10host_mem_usage 428536 # Number of bytes of host memory used 11host_seconds 8652.29 # Real time elapsed on the host | 7host_inst_rate 80283 # Simulator instruction rate (inst/s) 8host_op_rate 148451 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40511385 # Simulator tick rate (ticks/s) 10host_mem_usage 420456 # Number of bytes of host memory used 11host_seconds 10299.59 # Real time elapsed on the host |
| 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 222784 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24527040 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24749824 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 222784 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 222784 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18883520 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18883520 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3481 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 383235 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386716 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 295055 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 295055 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 533936 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 58782796 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 59316732 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 533936 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 533936 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 45257239 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 45257239 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 45257239 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 533936 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 58782796 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 104573971 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386716 # Number of read requests accepted 40system.physmem.writeReqs 295055 # Number of write requests accepted 41system.physmem.readBursts 386716 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 295055 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24729280 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18881664 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24749824 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18883520 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 222336 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24526912 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24749248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 222336 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 222336 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18882944 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18882944 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3474 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 383233 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386707 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 295046 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 295046 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 532860 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 58782205 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 59315065 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 532860 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 532860 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 45255640 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 45255640 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 45255640 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 532860 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 58782205 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 104570704 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386709 # Number of read requests accepted 40system.physmem.writeReqs 295046 # Number of write requests accepted 41system.physmem.readBursts 386709 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 295046 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24728384 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18881536 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24749376 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18882944 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 50system.physmem.neitherReadNorWriteReqs 188421 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24059 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26427 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24735 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24592 # Per bank write bursts | 50system.physmem.neitherReadNorWriteReqs 188175 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24066 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26415 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24733 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24594 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::4 23512 # Per bank write bursts | 55system.physmem.perBankRdBursts::4 23512 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::5 23783 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24571 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24367 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23708 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23929 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24776 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24016 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23246 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22935 # Per bank write bursts 65system.physmem.perBankRdBursts::14 23871 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23868 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18618 # Per bank write bursts | 56system.physmem.perBankRdBursts::5 23778 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24541 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24366 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23719 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23940 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24780 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24034 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23243 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22939 # Per bank write bursts 65system.physmem.perBankRdBursts::14 23855 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23866 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18622 # Per bank write bursts |
| 68system.physmem.perBankWrBursts::1 19926 # Per bank write bursts | 68system.physmem.perBankWrBursts::1 19926 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::2 18978 # Per bank write bursts 70system.physmem.perBankWrBursts::3 19008 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18159 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18511 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19142 # Per bank write bursts 74system.physmem.perBankWrBursts::7 19088 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18666 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18203 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18897 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17760 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17400 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16992 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17815 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17863 # Per bank write bursts | 69system.physmem.perBankWrBursts::2 18981 # Per bank write bursts 70system.physmem.perBankWrBursts::3 19010 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18166 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18514 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19130 # Per bank write bursts 74system.physmem.perBankWrBursts::7 19080 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18668 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18206 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18899 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17761 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17398 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16998 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17806 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17859 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 417248585500 # Total gap between requests | 85system.physmem.totGap 417250612500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 386716 # Read request sizes (log2) | 92system.physmem.readPktSize::6 386709 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 295055 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381306 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4710 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 295046 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381319 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4687 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 6180 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6571 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17600 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17661 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17665 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17728 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 6175 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6559 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16925 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17530 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17602 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17649 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17658 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17667 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17730 # What write queue length does an incoming req see |
| 156system.physmem.wrQLenPdf::24 17675 # What write queue length does an incoming req see | 156system.physmem.wrQLenPdf::24 17675 # What write queue length does an incoming req see |
| 157system.physmem.wrQLenPdf::25 17719 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17679 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17738 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17732 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17730 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17919 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17604 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17538 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see | 157system.physmem.wrQLenPdf::25 17721 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17676 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17739 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17735 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17731 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17918 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17608 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::34 23 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::34 23 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 147457 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 295.740616 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 174.463963 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 323.226581 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54784 37.15% 37.15% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 40098 27.19% 64.35% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13706 9.29% 73.64% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7465 5.06% 78.70% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5444 3.69% 82.39% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3767 2.55% 84.95% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3056 2.07% 87.02% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2830 1.92% 88.94% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16307 11.06% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 147457 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17513 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.062525 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 217.476315 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17502 99.94% 99.94% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 147516 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 295.624068 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 174.465729 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 322.989289 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54788 37.14% 37.14% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 40113 27.19% 64.33% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13739 9.31% 73.65% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7486 5.07% 78.72% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5440 3.69% 82.41% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3806 2.58% 84.99% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3042 2.06% 87.05% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2827 1.92% 88.97% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16275 11.03% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 147516 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17514 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.060866 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 217.469599 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17503 99.94% 99.94% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::total 17513 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17513 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.846114 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.774956 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 2.557273 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16-19 17320 98.90% 98.90% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20-23 139 0.79% 99.69% # Writes before turning the bus around for reads | 219system.physmem.rdPerTurnAround::total 17514 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17514 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.845038 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.773915 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 2.557012 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16-19 17326 98.93% 98.93% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20-23 134 0.77% 99.69% # Writes before turning the bus around for reads |
| 226system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-31 5 0.03% 99.90% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads | 226system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-31 5 0.03% 99.90% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads |
| 242system.physmem.wrPerTurnAround::total 17513 # Writes before turning the bus around for reads 243system.physmem.totQLat 4300099500 # Total ticks spent queuing 244system.physmem.totMemAccLat 11545005750 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 1931975000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 11128.77 # Average queueing delay per DRAM burst | 242system.physmem.wrPerTurnAround::total 17514 # Writes before turning the bus around for reads 243system.physmem.totQLat 4299952250 # Total ticks spent queuing 244system.physmem.totMemAccLat 11544596000 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 1931905000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 11128.79 # Average queueing delay per DRAM burst |
| 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 248system.physmem.avgMemAccLat 29878.77 # Average memory access latency per DRAM burst | 248system.physmem.avgMemAccLat 29878.79 # Average memory access latency per DRAM burst |
| 249system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 45.25 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 0.82 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads 256system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes 257system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing | 249system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 45.25 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 0.82 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads 256system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes 257system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing |
| 258system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing 259system.physmem.readRowHits 318002 # Number of row buffer hits during reads 260system.physmem.writeRowHits 215948 # Number of row buffer hits during writes 261system.physmem.readRowHitRate 82.30 # Row buffer hit rate for reads 262system.physmem.writeRowHitRate 73.19 # Row buffer hit rate for writes 263system.physmem.avgGap 612006.94 # Average gap between requests | 258system.physmem.avgWrQLen 21.85 # Average write queue length when enqueuing 259system.physmem.readRowHits 317964 # Number of row buffer hits during reads 260system.physmem.writeRowHits 215920 # Number of row buffer hits during writes 261system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads 262system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes 263system.physmem.avgGap 612024.28 # Average gap between requests |
| 264system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined | 264system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined |
| 265system.physmem_0.actEnergy 569698920 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 310847625 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 1529026200 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 981072000 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 63410789430 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 194721715500 # Energy for precharge background per rank (pJ) 272system.physmem_0.totalEnergy 288775354395 # Total energy per rank (pJ) 273system.physmem_0.averagePower 692.105150 # Core power per rank (mW) 274system.physmem_0.memoryStateTime::IDLE 323379971500 # Time in different power states 275system.physmem_0.memoryStateTime::REF 13932620000 # Time in different power states | 265system.physmem_0.actEnergy 570008880 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 311016750 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 1528831200 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 981214560 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 27252713280 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 63403052535 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 194733182250 # Energy for precharge background per rank (pJ) 272system.physmem_0.totalEnergy 288780019455 # Total energy per rank (pJ) 273system.physmem_0.averagePower 692.103393 # Core power per rank (mW) 274system.physmem_0.memoryStateTime::IDLE 323396501250 # Time in different power states 275system.physmem_0.memoryStateTime::REF 13932880000 # Time in different power states |
| 276system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 276system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 277system.physmem_0.memoryStateTime::ACT 79931501500 # Time in different power states | 277system.physmem_0.memoryStateTime::ACT 79920713750 # Time in different power states |
| 278system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 278system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 279system.physmem_1.actEnergy 544690440 # Energy for activate commands per rank (pJ) 280system.physmem_1.preEnergy 297202125 # Energy for precharge commands per rank (pJ) 281system.physmem_1.readEnergy 1484246400 # Energy for read commands per rank (pJ) 282system.physmem_1.writeEnergy 930262320 # Energy for write commands per rank (pJ) 283system.physmem_1.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) 284system.physmem_1.actBackEnergy 61581182625 # Energy for active background per rank (pJ) 285system.physmem_1.preBackEnergy 196326633750 # Energy for precharge background per rank (pJ) 286system.physmem_1.totalEnergy 288416422380 # Total energy per rank (pJ) 287system.physmem_1.averagePower 691.244901 # Core power per rank (mW) 288system.physmem_1.memoryStateTime::IDLE 326066613500 # Time in different power states 289system.physmem_1.memoryStateTime::REF 13932620000 # Time in different power states | 279system.physmem_1.actEnergy 545189400 # Energy for activate commands per rank (pJ) 280system.physmem_1.preEnergy 297474375 # Energy for precharge commands per rank (pJ) 281system.physmem_1.readEnergy 1484854800 # Energy for read commands per rank (pJ) 282system.physmem_1.writeEnergy 930437280 # Energy for write commands per rank (pJ) 283system.physmem_1.refreshEnergy 27252713280 # Energy for refresh commands per rank (pJ) 284system.physmem_1.actBackEnergy 61562082780 # Energy for active background per rank (pJ) 285system.physmem_1.preBackEnergy 196348068000 # Energy for precharge background per rank (pJ) 286system.physmem_1.totalEnergy 288420819915 # Total energy per rank (pJ) 287system.physmem_1.averagePower 691.242519 # Core power per rank (mW) 288system.physmem_1.memoryStateTime::IDLE 326101005500 # Time in different power states 289system.physmem_1.memoryStateTime::REF 13932880000 # Time in different power states |
| 290system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 290system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 291system.physmem_1.memoryStateTime::ACT 77244604500 # Time in different power states | 291system.physmem_1.memoryStateTime::ACT 77215953250 # Time in different power states |
| 292system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 292system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 293system.cpu.branchPred.lookups 230038764 # Number of BP lookups 294system.cpu.branchPred.condPredicted 230038764 # Number of conditional branches predicted 295system.cpu.branchPred.condIncorrect 9737010 # Number of conditional branches incorrect 296system.cpu.branchPred.BTBLookups 131438605 # Number of BTB lookups 297system.cpu.branchPred.BTBHits 128726788 # Number of BTB hits | 293system.cpu.branchPred.lookups 230048146 # Number of BP lookups 294system.cpu.branchPred.condPredicted 230048146 # Number of conditional branches predicted 295system.cpu.branchPred.condIncorrect 9737361 # Number of conditional branches incorrect 296system.cpu.branchPred.BTBLookups 131481620 # Number of BTB lookups 297system.cpu.branchPred.BTBHits 128745848 # Number of BTB hits |
| 298system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 298system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 299system.cpu.branchPred.BTBHitPct 97.936818 # BTB Hit Percentage 300system.cpu.branchPred.usedRAS 27748214 # Number of times the RAS was used to get a target. 301system.cpu.branchPred.RASInCorrect 1467706 # Number of incorrect RAS predictions. | 299system.cpu.branchPred.BTBHitPct 97.919274 # BTB Hit Percentage 300system.cpu.branchPred.usedRAS 27747759 # Number of times the RAS was used to get a target. 301system.cpu.branchPred.RASInCorrect 1468593 # Number of incorrect RAS predictions. |
| 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 304system.cpu.workload.num_syscalls 551 # Number of system calls | 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 304system.cpu.workload.num_syscalls 551 # Number of system calls |
| 305system.cpu.numCycles 834497218 # number of cpu cycles simulated | 305system.cpu.numCycles 834501256 # number of cpu cycles simulated |
| 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 308system.cpu.fetch.icacheStallCycles 185109509 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 1269285801 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 230038764 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 156475002 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 638168020 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 20207441 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 514 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.MiscStallCycles 99542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 316system.cpu.fetch.PendingTrapStallCycles 817516 # Number of stall cycles due to pending traps 317system.cpu.fetch.PendingQuiesceStallCycles 1330 # Number of stall cycles due to pending quiesce instructions 318system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 179424674 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 2717056 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 834300207 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 2.829871 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.382747 # Number of instructions fetched each cycle (Total) | 308system.cpu.fetch.icacheStallCycles 185122313 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 1269330935 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 230048146 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 156493607 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 638172933 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 20204179 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 520 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.MiscStallCycles 97554 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 316system.cpu.fetch.PendingTrapStallCycles 807935 # Number of stall cycles due to pending traps 317system.cpu.fetch.PendingQuiesceStallCycles 1425 # Number of stall cycles due to pending quiesce instructions 318system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 179438196 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 2717621 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 834304821 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 2.829912 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.382398 # Number of instructions fetched each cycle (Total) |
| 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 326system.cpu.fetch.rateDist::0 426804407 51.16% 51.16% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 33711236 4.04% 55.20% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 32817404 3.93% 59.13% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 33341418 4.00% 63.13% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 27188546 3.26% 66.39% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 27662073 3.32% 69.70% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 36987842 4.43% 74.14% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 33698291 4.04% 78.17% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 182088990 21.83% 100.00% # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::0 426682795 51.14% 51.14% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 33772943 4.05% 55.19% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 32839651 3.94% 59.13% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 33391032 4.00% 63.13% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 27218620 3.26% 66.39% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 27672975 3.32% 69.71% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 36987549 4.43% 74.14% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 33695145 4.04% 78.18% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 182044111 21.82% 100.00% # Number of instructions fetched each cycle (Total) |
| 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 338system.cpu.fetch.rateDist::total 834300207 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.275662 # Number of branch fetches per cycle 340system.cpu.fetch.rate 1.521019 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 127532754 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 374895763 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 240450543 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 81317427 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 10103720 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 2225154931 # Number of instructions handled by decode 347system.cpu.rename.SquashCycles 10103720 # Number of cycles rename is squashing 348system.cpu.rename.IdleCycles 159590885 # Number of cycles rename is idle 349system.cpu.rename.BlockCycles 159861387 # Number of cycles rename is blocking 350system.cpu.rename.serializeStallCycles 39705 # count of cycles rename stalled for serializing inst 351system.cpu.rename.RunCycles 285625371 # Number of cycles rename is running 352system.cpu.rename.UnblockCycles 219079139 # Number of cycles rename is unblocking 353system.cpu.rename.RenamedInsts 2175033402 # Number of instructions processed by rename 354system.cpu.rename.ROBFullEvents 169320 # Number of times rename has blocked due to ROB full 355system.cpu.rename.IQFullEvents 136042771 # Number of times rename has blocked due to IQ full 356system.cpu.rename.LQFullEvents 24241877 # Number of times rename has blocked due to LQ full 357system.cpu.rename.SQFullEvents 48673196 # Number of times rename has blocked due to SQ full 358system.cpu.rename.RenamedOperands 2279253847 # Number of destination operands rename has renamed 359system.cpu.rename.RenameLookups 5500789642 # Number of register rename lookups that rename has made 360system.cpu.rename.int_rename_lookups 3498971898 # Number of integer rename lookups 361system.cpu.rename.fp_rename_lookups 55892 # Number of floating rename lookups | 338system.cpu.fetch.rateDist::total 834304821 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.275671 # Number of branch fetches per cycle 340system.cpu.fetch.rate 1.521065 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 127569243 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 374855550 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 240395072 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 81382867 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 10102089 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 2225227906 # Number of instructions handled by decode 347system.cpu.rename.SquashCycles 10102089 # Number of cycles rename is squashing 348system.cpu.rename.IdleCycles 159580734 # Number of cycles rename is idle 349system.cpu.rename.BlockCycles 159860016 # Number of cycles rename is blocking 350system.cpu.rename.serializeStallCycles 39443 # count of cycles rename stalled for serializing inst 351system.cpu.rename.RunCycles 285688559 # Number of cycles rename is running 352system.cpu.rename.UnblockCycles 219033980 # Number of cycles rename is unblocking 353system.cpu.rename.RenamedInsts 2175097177 # Number of instructions processed by rename 354system.cpu.rename.ROBFullEvents 169662 # Number of times rename has blocked due to ROB full 355system.cpu.rename.IQFullEvents 136298138 # Number of times rename has blocked due to IQ full 356system.cpu.rename.LQFullEvents 24249327 # Number of times rename has blocked due to LQ full 357system.cpu.rename.SQFullEvents 48475339 # Number of times rename has blocked due to SQ full 358system.cpu.rename.RenamedOperands 2279313761 # Number of destination operands rename has renamed 359system.cpu.rename.RenameLookups 5500897024 # Number of register rename lookups that rename has made 360system.cpu.rename.int_rename_lookups 3499022597 # Number of integer rename lookups 361system.cpu.rename.fp_rename_lookups 55311 # Number of floating rename lookups |
| 362system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed | 362system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed |
| 363system.cpu.rename.UndoneMaps 665212993 # Number of HB maps that are undone due to squashing 364system.cpu.rename.serializingInsts 3161 # count of serializing insts renamed 365system.cpu.rename.tempSerializingInsts 2925 # count of temporary serializing insts renamed 366system.cpu.rename.skidInsts 415266866 # count of insts added to the skid buffer 367system.cpu.memDep0.insertedLoads 528334914 # Number of loads inserted to the mem dependence unit. 368system.cpu.memDep0.insertedStores 209874644 # Number of stores inserted to the mem dependence unit. 369system.cpu.memDep0.conflictingLoads 239338770 # Number of conflicting loads. 370system.cpu.memDep0.conflictingStores 72144908 # Number of conflicting stores. 371system.cpu.iq.iqInstsAdded 2101019043 # Number of instructions added to the IQ (excludes non-spec) 372system.cpu.iq.iqNonSpecInstsAdded 25133 # Number of non-speculative instructions added to the IQ 373system.cpu.iq.iqInstsIssued 1826920514 # Number of instructions issued 374system.cpu.iq.iqSquashedInstsIssued 398452 # Number of squashed instructions issued 375system.cpu.iq.iqSquashedInstsExamined 572055475 # Number of squashed instructions iterated over during squash; mainly for profiling 376system.cpu.iq.iqSquashedOperandsExamined 973771254 # Number of squashed operands that are examined and possibly removed from graph 377system.cpu.iq.iqSquashedNonSpecRemoved 24581 # Number of squashed non-spec instructions that were removed 378system.cpu.iq.issued_per_cycle::samples 834300207 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::mean 2.189764 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::stdev 2.073153 # Number of insts issued each cycle | 363system.cpu.rename.UndoneMaps 665272907 # Number of HB maps that are undone due to squashing 364system.cpu.rename.serializingInsts 3132 # count of serializing insts renamed 365system.cpu.rename.tempSerializingInsts 2892 # count of temporary serializing insts renamed 366system.cpu.rename.skidInsts 414765306 # count of insts added to the skid buffer 367system.cpu.memDep0.insertedLoads 528353068 # Number of loads inserted to the mem dependence unit. 368system.cpu.memDep0.insertedStores 209871702 # Number of stores inserted to the mem dependence unit. 369system.cpu.memDep0.conflictingLoads 239280350 # Number of conflicting loads. 370system.cpu.memDep0.conflictingStores 72161896 # Number of conflicting stores. 371system.cpu.iq.iqInstsAdded 2101070031 # Number of instructions added to the IQ (excludes non-spec) 372system.cpu.iq.iqNonSpecInstsAdded 24820 # Number of non-speculative instructions added to the IQ 373system.cpu.iq.iqInstsIssued 1826918488 # Number of instructions issued 374system.cpu.iq.iqSquashedInstsIssued 398350 # Number of squashed instructions issued 375system.cpu.iq.iqSquashedInstsExamined 572106150 # Number of squashed instructions iterated over during squash; mainly for profiling 376system.cpu.iq.iqSquashedOperandsExamined 973941611 # Number of squashed operands that are examined and possibly removed from graph 377system.cpu.iq.iqSquashedNonSpecRemoved 24268 # Number of squashed non-spec instructions that were removed 378system.cpu.iq.issued_per_cycle::samples 834304821 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::mean 2.189749 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::stdev 2.072611 # Number of insts issued each cycle |
| 381system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 381system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 382system.cpu.iq.issued_per_cycle::0 254789239 30.54% 30.54% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::1 125577373 15.05% 45.59% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::2 119153367 14.28% 59.87% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::3 111141032 13.32% 73.19% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::4 92244378 11.06% 84.25% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::5 61717114 7.40% 91.65% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::6 43107761 5.17% 96.82% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::7 19155881 2.30% 99.11% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::8 7414062 0.89% 100.00% # Number of insts issued each cycle | 382system.cpu.iq.issued_per_cycle::0 254655960 30.52% 30.52% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::1 125511852 15.04% 45.57% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::2 119464444 14.32% 59.89% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::3 111099885 13.32% 73.20% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::4 92302861 11.06% 84.27% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::5 61631743 7.39% 91.65% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::6 43068652 5.16% 96.82% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::7 19159370 2.30% 99.11% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::8 7410054 0.89% 100.00% # Number of insts issued each cycle |
| 391system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 391system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 394system.cpu.iq.issued_per_cycle::total 834300207 # Number of insts issued each cycle | 394system.cpu.iq.issued_per_cycle::total 834304821 # Number of insts issued each cycle |
| 395system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 395system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 396system.cpu.iq.fu_full::IntAlu 11334405 42.48% 42.48% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemRead 12275528 46.01% 88.49% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemWrite 3069676 11.51% 100.00% # attempts to use FU when none available | 396system.cpu.iq.fu_full::IntAlu 11329083 42.46% 42.46% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemRead 12292434 46.07% 88.53% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemWrite 3060904 11.47% 100.00% # attempts to use FU when none available |
| 427system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 427system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 429system.cpu.iq.FU_type_0::No_OpClass 2718617 0.15% 0.15% # Type of FU issued 430system.cpu.iq.FU_type_0::IntAlu 1211210104 66.30% 66.45% # Type of FU issued 431system.cpu.iq.FU_type_0::IntMult 389740 0.02% 66.47% # Type of FU issued 432system.cpu.iq.FU_type_0::IntDiv 3881078 0.21% 66.68% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatAdd 127 0.00% 66.68% # Type of FU issued | 429system.cpu.iq.FU_type_0::No_OpClass 2718358 0.15% 0.15% # Type of FU issued 430system.cpu.iq.FU_type_0::IntAlu 1211226700 66.30% 66.45% # Type of FU issued 431system.cpu.iq.FU_type_0::IntMult 389616 0.02% 66.47% # Type of FU issued 432system.cpu.iq.FU_type_0::IntDiv 3881120 0.21% 66.68% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.68% # Type of FU issued |
| 434system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCvt 2 0.00% 66.68% # Type of FU issued | 434system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCvt 2 0.00% 66.68% # Type of FU issued |
| 436system.cpu.iq.FU_type_0::FloatMult 27 0.00% 66.68% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatDiv 416 0.00% 66.68% # Type of FU issued | 436system.cpu.iq.FU_type_0::FloatMult 24 0.00% 66.68% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatDiv 414 0.00% 66.68% # Type of FU issued |
| 438system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 451system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued | 438system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 451system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued |
| 459system.cpu.iq.FU_type_0::MemRead 435004125 23.81% 90.49% # Type of FU issued 460system.cpu.iq.FU_type_0::MemWrite 173716278 9.51% 100.00% # Type of FU issued | 459system.cpu.iq.FU_type_0::MemRead 434992081 23.81% 90.49% # Type of FU issued 460system.cpu.iq.FU_type_0::MemWrite 173710042 9.51% 100.00% # Type of FU issued |
| 461system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 461system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 463system.cpu.iq.FU_type_0::total 1826920514 # Type of FU issued 464system.cpu.iq.rate 2.189247 # Inst issue rate 465system.cpu.iq.fu_busy_cnt 26679609 # FU busy when requested 466system.cpu.iq.fu_busy_rate 0.014604 # FU busy rate (busy events/executed inst) 467system.cpu.iq.int_inst_queue_reads 4515187521 # Number of integer instruction queue reads 468system.cpu.iq.int_inst_queue_writes 2673359658 # Number of integer instruction queue writes 469system.cpu.iq.int_inst_queue_wakeup_accesses 1796857140 # Number of integer instruction queue wakeup accesses 470system.cpu.iq.fp_inst_queue_reads 31775 # Number of floating instruction queue reads 471system.cpu.iq.fp_inst_queue_writes 70770 # Number of floating instruction queue writes 472system.cpu.iq.fp_inst_queue_wakeup_accesses 6885 # Number of floating instruction queue wakeup accesses 473system.cpu.iq.int_alu_accesses 1850866868 # Number of integer alu accesses 474system.cpu.iq.fp_alu_accesses 14638 # Number of floating point alu accesses 475system.cpu.iew.lsq.thread0.forwLoads 185770181 # Number of loads that had data forwarded from stores | 463system.cpu.iq.FU_type_0::total 1826918488 # Type of FU issued 464system.cpu.iq.rate 2.189234 # Inst issue rate 465system.cpu.iq.fu_busy_cnt 26682421 # FU busy when requested 466system.cpu.iq.fu_busy_rate 0.014605 # FU busy rate (busy events/executed inst) 467system.cpu.iq.int_inst_queue_reads 4515190603 # Number of integer instruction queue reads 468system.cpu.iq.int_inst_queue_writes 2673460892 # Number of integer instruction queue writes 469system.cpu.iq.int_inst_queue_wakeup_accesses 1796856978 # Number of integer instruction queue wakeup accesses 470system.cpu.iq.fp_inst_queue_reads 31965 # Number of floating instruction queue reads 471system.cpu.iq.fp_inst_queue_writes 70764 # Number of floating instruction queue writes 472system.cpu.iq.fp_inst_queue_wakeup_accesses 6893 # Number of floating instruction queue wakeup accesses 473system.cpu.iq.int_alu_accesses 1850867797 # Number of integer alu accesses 474system.cpu.iq.fp_alu_accesses 14754 # Number of floating point alu accesses 475system.cpu.iew.lsq.thread0.forwLoads 185700457 # Number of loads that had data forwarded from stores |
| 476system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 476system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 477system.cpu.iew.lsq.thread0.squashedLoads 144235066 # Number of loads squashed 478system.cpu.iew.lsq.thread0.ignoredResponses 213448 # Number of memory responses ignored because the instruction is squashed 479system.cpu.iew.lsq.thread0.memOrderViolation 384677 # Number of memory ordering violations 480system.cpu.iew.lsq.thread0.squashedStores 60714458 # Number of stores squashed | 477system.cpu.iew.lsq.thread0.squashedLoads 144253147 # Number of loads squashed 478system.cpu.iew.lsq.thread0.ignoredResponses 213808 # Number of memory responses ignored because the instruction is squashed 479system.cpu.iew.lsq.thread0.memOrderViolation 384332 # Number of memory ordering violations 480system.cpu.iew.lsq.thread0.squashedStores 60711516 # Number of stores squashed |
| 481system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 482system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 481system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 482system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 483system.cpu.iew.lsq.thread0.rescheduledLoads 19450 # Number of loads that were rescheduled 484system.cpu.iew.lsq.thread0.cacheBlocked 994 # Number of times an access to memory failed due to the cache being blocked | 483system.cpu.iew.lsq.thread0.rescheduledLoads 18958 # Number of loads that were rescheduled 484system.cpu.iew.lsq.thread0.cacheBlocked 979 # Number of times an access to memory failed due to the cache being blocked |
| 485system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 485system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 486system.cpu.iew.iewSquashCycles 10103720 # Number of cycles IEW is squashing 487system.cpu.iew.iewBlockCycles 107027275 # Number of cycles IEW is blocking 488system.cpu.iew.iewUnblockCycles 6171947 # Number of cycles IEW is unblocking 489system.cpu.iew.iewDispatchedInsts 2101044176 # Number of instructions dispatched to IQ 490system.cpu.iew.iewDispSquashedInsts 397040 # Number of squashed instructions skipped by dispatch 491system.cpu.iew.iewDispLoadInsts 528337223 # Number of dispatched load instructions 492system.cpu.iew.iewDispStoreInsts 209874644 # Number of dispatched store instructions 493system.cpu.iew.iewDispNonSpecInsts 7154 # Number of dispatched non-speculative instructions 494system.cpu.iew.iewIQFullEvents 1885059 # Number of times the IQ has become full, causing a stall 495system.cpu.iew.iewLSQFullEvents 3390398 # Number of times the LSQ has become full, causing a stall 496system.cpu.iew.memOrderViolationEvents 384677 # Number of memory order violations 497system.cpu.iew.predictedTakenIncorrect 5738634 # Number of branches that were predicted taken incorrectly 498system.cpu.iew.predictedNotTakenIncorrect 4563911 # Number of branches that were predicted not taken incorrectly 499system.cpu.iew.branchMispredicts 10302545 # Number of branch mispredicts detected at execute 500system.cpu.iew.iewExecutedInsts 1805509782 # Number of executed instructions 501system.cpu.iew.iewExecLoadInsts 428792858 # Number of load instructions executed 502system.cpu.iew.iewExecSquashedInsts 21410732 # Number of squashed instructions skipped in execute | 486system.cpu.iew.iewSquashCycles 10102089 # Number of cycles IEW is squashing 487system.cpu.iew.iewBlockCycles 107041835 # Number of cycles IEW is blocking 488system.cpu.iew.iewUnblockCycles 6156081 # Number of cycles IEW is unblocking 489system.cpu.iew.iewDispatchedInsts 2101094851 # Number of instructions dispatched to IQ 490system.cpu.iew.iewDispSquashedInsts 396815 # Number of squashed instructions skipped by dispatch 491system.cpu.iew.iewDispLoadInsts 528355304 # Number of dispatched load instructions 492system.cpu.iew.iewDispStoreInsts 209871702 # Number of dispatched store instructions 493system.cpu.iew.iewDispNonSpecInsts 6976 # Number of dispatched non-speculative instructions 494system.cpu.iew.iewIQFullEvents 1865462 # Number of times the IQ has become full, causing a stall 495system.cpu.iew.iewLSQFullEvents 3396504 # Number of times the LSQ has become full, causing a stall 496system.cpu.iew.memOrderViolationEvents 384332 # Number of memory order violations 497system.cpu.iew.predictedTakenIncorrect 5739761 # Number of branches that were predicted taken incorrectly 498system.cpu.iew.predictedNotTakenIncorrect 4560590 # Number of branches that were predicted not taken incorrectly 499system.cpu.iew.branchMispredicts 10300351 # Number of branch mispredicts detected at execute 500system.cpu.iew.iewExecutedInsts 1805510192 # Number of executed instructions 501system.cpu.iew.iewExecLoadInsts 428784370 # Number of load instructions executed 502system.cpu.iew.iewExecSquashedInsts 21408296 # Number of squashed instructions skipped in execute |
| 503system.cpu.iew.exec_swp 0 # number of swp insts executed 504system.cpu.iew.exec_nop 0 # number of nop insts executed | 503system.cpu.iew.exec_swp 0 # number of swp insts executed 504system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 505system.cpu.iew.exec_refs 598991015 # number of memory reference insts executed 506system.cpu.iew.exec_branches 171766085 # Number of branches executed 507system.cpu.iew.exec_stores 170198157 # Number of stores executed 508system.cpu.iew.exec_rate 2.163590 # Inst execution rate 509system.cpu.iew.wb_sent 1802110409 # cumulative count of insts sent to commit 510system.cpu.iew.wb_count 1796864025 # cumulative count of insts written-back 511system.cpu.iew.wb_producers 1368049337 # num instructions producing a value 512system.cpu.iew.wb_consumers 2090115063 # num instructions consuming a value | 505system.cpu.iew.exec_refs 598976056 # number of memory reference insts executed 506system.cpu.iew.exec_branches 171763411 # Number of branches executed 507system.cpu.iew.exec_stores 170191686 # Number of stores executed 508system.cpu.iew.exec_rate 2.163580 # Inst execution rate 509system.cpu.iew.wb_sent 1802107285 # cumulative count of insts sent to commit 510system.cpu.iew.wb_count 1796863871 # cumulative count of insts written-back 511system.cpu.iew.wb_producers 1368034303 # num instructions producing a value 512system.cpu.iew.wb_consumers 2090148534 # num instructions consuming a value |
| 513system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 513system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 514system.cpu.iew.wb_rate 2.153229 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.654533 # average fanout of values written-back | 514system.cpu.iew.wb_rate 2.153219 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.654515 # average fanout of values written-back |
| 516system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 516system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 517system.cpu.commit.commitSquashedInsts 572135204 # The number of squashed insts skipped by commit | 517system.cpu.commit.commitSquashedInsts 572186286 # The number of squashed insts skipped by commit |
| 518system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 518system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 519system.cpu.commit.branchMispredicts 9825001 # The number of times a branch was mispredicted 520system.cpu.commit.committed_per_cycle::samples 756651956 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::mean 2.020729 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::stdev 2.548081 # Number of insts commited each cycle | 519system.cpu.commit.branchMispredicts 9823371 # The number of times a branch was mispredicted 520system.cpu.commit.committed_per_cycle::samples 756648341 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::mean 2.020739 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::stdev 2.547802 # Number of insts commited each cycle |
| 523system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 523system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 524system.cpu.commit.committed_per_cycle::0 287953386 38.06% 38.06% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::1 175292333 23.17% 61.22% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::2 57344837 7.58% 68.80% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::3 86221937 11.40% 80.20% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::4 27113369 3.58% 83.78% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::5 27107052 3.58% 87.36% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::6 9811804 1.30% 88.66% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::7 8976581 1.19% 89.85% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::8 76830657 10.15% 100.00% # Number of insts commited each cycle | 524system.cpu.commit.committed_per_cycle::0 287852257 38.04% 38.04% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::1 175420323 23.18% 61.23% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::2 57242279 7.57% 68.79% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::3 86327184 11.41% 80.20% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::4 27107734 3.58% 83.78% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::5 27120897 3.58% 87.37% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::6 9790292 1.29% 88.66% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::7 8973905 1.19% 89.85% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::8 76813470 10.15% 100.00% # Number of insts commited each cycle |
| 533system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 533system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 536system.cpu.commit.committed_per_cycle::total 756651956 # Number of insts commited each cycle | 536system.cpu.commit.committed_per_cycle::total 756648341 # Number of insts commited each cycle |
| 537system.cpu.commit.committedInsts 826877109 # Number of instructions committed 538system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 539system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 540system.cpu.commit.refs 533262343 # Number of memory references committed 541system.cpu.commit.loads 384102157 # Number of loads committed 542system.cpu.commit.membars 0 # Number of memory barriers committed 543system.cpu.commit.branches 149758583 # Number of branches committed 544system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 574system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 577system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 578system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 581system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction | 537system.cpu.commit.committedInsts 826877109 # Number of instructions committed 538system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 539system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 540system.cpu.commit.refs 533262343 # Number of memory references committed 541system.cpu.commit.loads 384102157 # Number of loads committed 542system.cpu.commit.membars 0 # Number of memory barriers committed 543system.cpu.commit.branches 149758583 # Number of branches committed 544system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 574system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 577system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 578system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 581system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction |
| 582system.cpu.commit.bw_lim_events 76830657 # number cycles where commit BW limit reached 583system.cpu.rob.rob_reads 2780945204 # The number of ROB reads 584system.cpu.rob.rob_writes 4280083493 # The number of ROB writes 585system.cpu.timesIdled 2292 # Number of times that the entire CPU went into an idle state and unscheduled itself 586system.cpu.idleCycles 197011 # Total number of cycles that the CPU has spent unscheduled due to idling | 582system.cpu.commit.bw_lim_events 76813470 # number cycles where commit BW limit reached 583system.cpu.rob.rob_reads 2781009858 # The number of ROB reads 584system.cpu.rob.rob_writes 4280193893 # The number of ROB writes 585system.cpu.timesIdled 2297 # Number of times that the entire CPU went into an idle state and unscheduled itself 586system.cpu.idleCycles 196435 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 587system.cpu.committedInsts 826877109 # Number of Instructions Simulated 588system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated | 587system.cpu.committedInsts 826877109 # Number of Instructions Simulated 588system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated |
| 589system.cpu.cpi 1.009216 # CPI: Cycles Per Instruction 590system.cpu.cpi_total 1.009216 # CPI: Total CPI of All Threads 591system.cpu.ipc 0.990869 # IPC: Instructions Per Cycle 592system.cpu.ipc_total 0.990869 # IPC: Total IPC of All Threads 593system.cpu.int_regfile_reads 2762017076 # number of integer regfile reads 594system.cpu.int_regfile_writes 1465005269 # number of integer regfile writes 595system.cpu.fp_regfile_reads 7183 # number of floating regfile reads 596system.cpu.fp_regfile_writes 481 # number of floating regfile writes 597system.cpu.cc_regfile_reads 600929280 # number of cc regfile reads 598system.cpu.cc_regfile_writes 409654003 # number of cc regfile writes 599system.cpu.misc_regfile_reads 990121594 # number of misc regfile reads | 589system.cpu.cpi 1.009220 # CPI: Cycles Per Instruction 590system.cpu.cpi_total 1.009220 # CPI: Total CPI of All Threads 591system.cpu.ipc 0.990864 # IPC: Instructions Per Cycle 592system.cpu.ipc_total 0.990864 # IPC: Total IPC of All Threads 593system.cpu.int_regfile_reads 2761953724 # number of integer regfile reads 594system.cpu.int_regfile_writes 1465013469 # number of integer regfile writes 595system.cpu.fp_regfile_reads 7172 # number of floating regfile reads 596system.cpu.fp_regfile_writes 467 # number of floating regfile writes 597system.cpu.cc_regfile_reads 600919347 # number of cc regfile reads 598system.cpu.cc_regfile_writes 409646269 # number of cc regfile writes 599system.cpu.misc_regfile_reads 990116456 # number of misc regfile reads |
| 600system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 600system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 601system.cpu.dcache.tags.replacements 2534273 # number of replacements 602system.cpu.dcache.tags.tagsinuse 4088.021333 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 387553004 # Total number of references to valid blocks. 604system.cpu.dcache.tags.sampled_refs 2538369 # Sample count of references to valid blocks. 605system.cpu.dcache.tags.avg_refs 152.677961 # Average number of references to valid blocks. | 601system.cpu.dcache.tags.replacements 2534268 # number of replacements 602system.cpu.dcache.tags.tagsinuse 4088.021372 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 387614743 # Total number of references to valid blocks. 604system.cpu.dcache.tags.sampled_refs 2538364 # Sample count of references to valid blocks. 605system.cpu.dcache.tags.avg_refs 152.702584 # Average number of references to valid blocks. |
| 606system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. | 606system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. |
| 607system.cpu.dcache.tags.occ_blocks::cpu.data 4088.021333 # Average occupied blocks per requestor | 607system.cpu.dcache.tags.occ_blocks::cpu.data 4088.021372 # Average occupied blocks per requestor |
| 608system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 608system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id | 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id |
| 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id | 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id |
| 613system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id 614system.cpu.dcache.tags.age_task_id_blocks_1024::3 3168 # Occupied blocks per task id | 613system.cpu.dcache.tags.age_task_id_blocks_1024::2 878 # Occupied blocks per task id 614system.cpu.dcache.tags.age_task_id_blocks_1024::3 3164 # Occupied blocks per task id |
| 615system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 615system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 616system.cpu.dcache.tags.tag_accesses 784232137 # Number of tag accesses 617system.cpu.dcache.tags.data_accesses 784232137 # Number of data accesses 618system.cpu.dcache.ReadReq_hits::cpu.data 238902536 # number of ReadReq hits 619system.cpu.dcache.ReadReq_hits::total 238902536 # number of ReadReq hits 620system.cpu.dcache.WriteReq_hits::cpu.data 148180257 # number of WriteReq hits 621system.cpu.dcache.WriteReq_hits::total 148180257 # number of WriteReq hits 622system.cpu.dcache.demand_hits::cpu.data 387082793 # number of demand (read+write) hits 623system.cpu.dcache.demand_hits::total 387082793 # number of demand (read+write) hits 624system.cpu.dcache.overall_hits::cpu.data 387082793 # number of overall hits 625system.cpu.dcache.overall_hits::total 387082793 # number of overall hits 626system.cpu.dcache.ReadReq_misses::cpu.data 2784146 # number of ReadReq misses 627system.cpu.dcache.ReadReq_misses::total 2784146 # number of ReadReq misses 628system.cpu.dcache.WriteReq_misses::cpu.data 979945 # number of WriteReq misses 629system.cpu.dcache.WriteReq_misses::total 979945 # number of WriteReq misses 630system.cpu.dcache.demand_misses::cpu.data 3764091 # number of demand (read+write) misses 631system.cpu.dcache.demand_misses::total 3764091 # number of demand (read+write) misses 632system.cpu.dcache.overall_misses::cpu.data 3764091 # number of overall misses 633system.cpu.dcache.overall_misses::total 3764091 # number of overall misses 634system.cpu.dcache.ReadReq_miss_latency::cpu.data 59451413500 # number of ReadReq miss cycles 635system.cpu.dcache.ReadReq_miss_latency::total 59451413500 # number of ReadReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::cpu.data 30841040499 # number of WriteReq miss cycles 637system.cpu.dcache.WriteReq_miss_latency::total 30841040499 # number of WriteReq miss cycles 638system.cpu.dcache.demand_miss_latency::cpu.data 90292453999 # number of demand (read+write) miss cycles 639system.cpu.dcache.demand_miss_latency::total 90292453999 # number of demand (read+write) miss cycles 640system.cpu.dcache.overall_miss_latency::cpu.data 90292453999 # number of overall miss cycles 641system.cpu.dcache.overall_miss_latency::total 90292453999 # number of overall miss cycles 642system.cpu.dcache.ReadReq_accesses::cpu.data 241686682 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.ReadReq_accesses::total 241686682 # number of ReadReq accesses(hits+misses) | 616system.cpu.dcache.tags.tag_accesses 784355902 # Number of tag accesses 617system.cpu.dcache.tags.data_accesses 784355902 # Number of data accesses 618system.cpu.dcache.ReadReq_hits::cpu.data 238963393 # number of ReadReq hits 619system.cpu.dcache.ReadReq_hits::total 238963393 # number of ReadReq hits 620system.cpu.dcache.WriteReq_hits::cpu.data 148180513 # number of WriteReq hits 621system.cpu.dcache.WriteReq_hits::total 148180513 # number of WriteReq hits 622system.cpu.dcache.demand_hits::cpu.data 387143906 # number of demand (read+write) hits 623system.cpu.dcache.demand_hits::total 387143906 # number of demand (read+write) hits 624system.cpu.dcache.overall_hits::cpu.data 387143906 # number of overall hits 625system.cpu.dcache.overall_hits::total 387143906 # number of overall hits 626system.cpu.dcache.ReadReq_misses::cpu.data 2785174 # number of ReadReq misses 627system.cpu.dcache.ReadReq_misses::total 2785174 # number of ReadReq misses 628system.cpu.dcache.WriteReq_misses::cpu.data 979689 # number of WriteReq misses 629system.cpu.dcache.WriteReq_misses::total 979689 # number of WriteReq misses 630system.cpu.dcache.demand_misses::cpu.data 3764863 # number of demand (read+write) misses 631system.cpu.dcache.demand_misses::total 3764863 # number of demand (read+write) misses 632system.cpu.dcache.overall_misses::cpu.data 3764863 # number of overall misses 633system.cpu.dcache.overall_misses::total 3764863 # number of overall misses 634system.cpu.dcache.ReadReq_miss_latency::cpu.data 59469395500 # number of ReadReq miss cycles 635system.cpu.dcache.ReadReq_miss_latency::total 59469395500 # number of ReadReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::cpu.data 30831236499 # number of WriteReq miss cycles 637system.cpu.dcache.WriteReq_miss_latency::total 30831236499 # number of WriteReq miss cycles 638system.cpu.dcache.demand_miss_latency::cpu.data 90300631999 # number of demand (read+write) miss cycles 639system.cpu.dcache.demand_miss_latency::total 90300631999 # number of demand (read+write) miss cycles 640system.cpu.dcache.overall_miss_latency::cpu.data 90300631999 # number of overall miss cycles 641system.cpu.dcache.overall_miss_latency::total 90300631999 # number of overall miss cycles 642system.cpu.dcache.ReadReq_accesses::cpu.data 241748567 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.ReadReq_accesses::total 241748567 # number of ReadReq accesses(hits+misses) |
| 644system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) | 644system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) |
| 646system.cpu.dcache.demand_accesses::cpu.data 390846884 # number of demand (read+write) accesses 647system.cpu.dcache.demand_accesses::total 390846884 # number of demand (read+write) accesses 648system.cpu.dcache.overall_accesses::cpu.data 390846884 # number of overall (read+write) accesses 649system.cpu.dcache.overall_accesses::total 390846884 # number of overall (read+write) accesses 650system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011520 # miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_miss_rate::total 0.011520 # miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006570 # miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_miss_rate::total 0.006570 # miss rate for WriteReq accesses | 646system.cpu.dcache.demand_accesses::cpu.data 390908769 # number of demand (read+write) accesses 647system.cpu.dcache.demand_accesses::total 390908769 # number of demand (read+write) accesses 648system.cpu.dcache.overall_accesses::cpu.data 390908769 # number of overall (read+write) accesses 649system.cpu.dcache.overall_accesses::total 390908769 # number of overall (read+write) accesses 650system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011521 # miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_miss_rate::total 0.011521 # miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses |
| 654system.cpu.dcache.demand_miss_rate::cpu.data 0.009631 # miss rate for demand accesses 655system.cpu.dcache.demand_miss_rate::total 0.009631 # miss rate for demand accesses 656system.cpu.dcache.overall_miss_rate::cpu.data 0.009631 # miss rate for overall accesses 657system.cpu.dcache.overall_miss_rate::total 0.009631 # miss rate for overall accesses | 654system.cpu.dcache.demand_miss_rate::cpu.data 0.009631 # miss rate for demand accesses 655system.cpu.dcache.demand_miss_rate::total 0.009631 # miss rate for demand accesses 656system.cpu.dcache.overall_miss_rate::cpu.data 0.009631 # miss rate for overall accesses 657system.cpu.dcache.overall_miss_rate::total 0.009631 # miss rate for overall accesses |
| 658system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21353.554555 # average ReadReq miss latency 659system.cpu.dcache.ReadReq_avg_miss_latency::total 21353.554555 # average ReadReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31472.215787 # average WriteReq miss latency 661system.cpu.dcache.WriteReq_avg_miss_latency::total 31472.215787 # average WriteReq miss latency 662system.cpu.dcache.demand_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency 663system.cpu.dcache.demand_avg_miss_latency::total 23987.850984 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency 665system.cpu.dcache.overall_avg_miss_latency::total 23987.850984 # average overall miss latency 666system.cpu.dcache.blocked_cycles::no_mshrs 10871 # number of cycles access was blocked | 658system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21352.129346 # average ReadReq miss latency 659system.cpu.dcache.ReadReq_avg_miss_latency::total 21352.129346 # average ReadReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31470.432453 # average WriteReq miss latency 661system.cpu.dcache.WriteReq_avg_miss_latency::total 31470.432453 # average WriteReq miss latency 662system.cpu.dcache.demand_avg_miss_latency::cpu.data 23985.104371 # average overall miss latency 663system.cpu.dcache.demand_avg_miss_latency::total 23985.104371 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::cpu.data 23985.104371 # average overall miss latency 665system.cpu.dcache.overall_avg_miss_latency::total 23985.104371 # average overall miss latency 666system.cpu.dcache.blocked_cycles::no_mshrs 10830 # number of cycles access was blocked |
| 667system.cpu.dcache.blocked_cycles::no_targets 28 # number of cycles access was blocked | 667system.cpu.dcache.blocked_cycles::no_targets 28 # number of cycles access was blocked |
| 668system.cpu.dcache.blocked::no_mshrs 1128 # number of cycles access was blocked | 668system.cpu.dcache.blocked::no_mshrs 1133 # number of cycles access was blocked |
| 669system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked | 669system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked |
| 670system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.637411 # average number of cycles each access was blocked | 670system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.558694 # average number of cycles each access was blocked |
| 671system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked 672system.cpu.dcache.fast_writes 0 # number of fast writes performed 673system.cpu.dcache.cache_copies 0 # number of cache copies performed | 671system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked 672system.cpu.dcache.fast_writes 0 # number of fast writes performed 673system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 674system.cpu.dcache.writebacks::writebacks 2332718 # number of writebacks 675system.cpu.dcache.writebacks::total 2332718 # number of writebacks 676system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1016180 # number of ReadReq MSHR hits 677system.cpu.dcache.ReadReq_mshr_hits::total 1016180 # number of ReadReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19269 # number of WriteReq MSHR hits 679system.cpu.dcache.WriteReq_mshr_hits::total 19269 # number of WriteReq MSHR hits 680system.cpu.dcache.demand_mshr_hits::cpu.data 1035449 # number of demand (read+write) MSHR hits 681system.cpu.dcache.demand_mshr_hits::total 1035449 # number of demand (read+write) MSHR hits 682system.cpu.dcache.overall_mshr_hits::cpu.data 1035449 # number of overall MSHR hits 683system.cpu.dcache.overall_mshr_hits::total 1035449 # number of overall MSHR hits 684system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767966 # number of ReadReq MSHR misses 685system.cpu.dcache.ReadReq_mshr_misses::total 1767966 # number of ReadReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960676 # number of WriteReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::total 960676 # number of WriteReq MSHR misses 688system.cpu.dcache.demand_mshr_misses::cpu.data 2728642 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 2728642 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 2728642 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 2728642 # number of overall MSHR misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33608501500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 33608501500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29628930000 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 29628930000 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63237431500 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 63237431500 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63237431500 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 63237431500 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007315 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007315 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006441 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006441 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for demand accesses 705system.cpu.dcache.demand_mshr_miss_rate::total 0.006981 # mshr miss rate for demand accesses 706system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for overall accesses 707system.cpu.dcache.overall_mshr_miss_rate::total 0.006981 # mshr miss rate for overall accesses 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19009.698999 # average ReadReq mshr miss latency 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19009.698999 # average ReadReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30841.751017 # average WriteReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30841.751017 # average WriteReq mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency | 674system.cpu.dcache.writebacks::writebacks 2332705 # number of writebacks 675system.cpu.dcache.writebacks::total 2332705 # number of writebacks 676system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017213 # number of ReadReq MSHR hits 677system.cpu.dcache.ReadReq_mshr_hits::total 1017213 # number of ReadReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19267 # number of WriteReq MSHR hits 679system.cpu.dcache.WriteReq_mshr_hits::total 19267 # number of WriteReq MSHR hits 680system.cpu.dcache.demand_mshr_hits::cpu.data 1036480 # number of demand (read+write) MSHR hits 681system.cpu.dcache.demand_mshr_hits::total 1036480 # number of demand (read+write) MSHR hits 682system.cpu.dcache.overall_mshr_hits::cpu.data 1036480 # number of overall MSHR hits 683system.cpu.dcache.overall_mshr_hits::total 1036480 # number of overall MSHR hits 684system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767961 # number of ReadReq MSHR misses 685system.cpu.dcache.ReadReq_mshr_misses::total 1767961 # number of ReadReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960422 # number of WriteReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::total 960422 # number of WriteReq MSHR misses 688system.cpu.dcache.demand_mshr_misses::cpu.data 2728383 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 2728383 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 2728383 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 2728383 # number of overall MSHR misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33609753000 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 33609753000 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29619647000 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 29619647000 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63229400000 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 63229400000 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63229400000 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 63229400000 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007313 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007313 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006439 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006439 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006980 # mshr miss rate for demand accesses 705system.cpu.dcache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses 706system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006980 # mshr miss rate for overall accesses 707system.cpu.dcache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.460638 # average ReadReq mshr miss latency 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.460638 # average ReadReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30840.242102 # average WriteReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30840.242102 # average WriteReq mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23174.678922 # average overall mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::total 23174.678922 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23174.678922 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::total 23174.678922 # average overall mshr miss latency |
| 716system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 716system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 717system.cpu.icache.tags.replacements 6996 # number of replacements 718system.cpu.icache.tags.tagsinuse 1051.094157 # Cycle average of tags in use 719system.cpu.icache.tags.total_refs 179219973 # Total number of references to valid blocks. 720system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. 721system.cpu.icache.tags.avg_refs 20825.002673 # Average number of references to valid blocks. | 717system.cpu.icache.tags.replacements 6976 # number of replacements 718system.cpu.icache.tags.tagsinuse 1050.495149 # Cycle average of tags in use 719system.cpu.icache.tags.total_refs 179233953 # Total number of references to valid blocks. 720system.cpu.icache.tags.sampled_refs 8576 # Sample count of references to valid blocks. 721system.cpu.icache.tags.avg_refs 20899.481460 # Average number of references to valid blocks. |
| 722system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 722system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 723system.cpu.icache.tags.occ_blocks::cpu.inst 1051.094157 # Average occupied blocks per requestor 724system.cpu.icache.tags.occ_percent::cpu.inst 0.513230 # Average percentage of cache occupancy 725system.cpu.icache.tags.occ_percent::total 0.513230 # Average percentage of cache occupancy 726system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id | 723system.cpu.icache.tags.occ_blocks::cpu.inst 1050.495149 # Average occupied blocks per requestor 724system.cpu.icache.tags.occ_percent::cpu.inst 0.512937 # Average percentage of cache occupancy 725system.cpu.icache.tags.occ_percent::total 0.512937 # Average percentage of cache occupancy 726system.cpu.icache.tags.occ_task_id_blocks::1024 1600 # Occupied blocks per task id |
| 727system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id | 727system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id |
| 728system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id 730system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id 731system.cpu.icache.tags.age_task_id_blocks_1024::4 1167 # Occupied blocks per task id 732system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id 733system.cpu.icache.tags.tag_accesses 359048380 # Number of tag accesses 734system.cpu.icache.tags.data_accesses 359048380 # Number of data accesses 735system.cpu.icache.ReadReq_hits::cpu.inst 179223042 # number of ReadReq hits 736system.cpu.icache.ReadReq_hits::total 179223042 # number of ReadReq hits 737system.cpu.icache.demand_hits::cpu.inst 179223042 # number of demand (read+write) hits 738system.cpu.icache.demand_hits::total 179223042 # number of demand (read+write) hits 739system.cpu.icache.overall_hits::cpu.inst 179223042 # number of overall hits 740system.cpu.icache.overall_hits::total 179223042 # number of overall hits 741system.cpu.icache.ReadReq_misses::cpu.inst 201632 # number of ReadReq misses 742system.cpu.icache.ReadReq_misses::total 201632 # number of ReadReq misses 743system.cpu.icache.demand_misses::cpu.inst 201632 # number of demand (read+write) misses 744system.cpu.icache.demand_misses::total 201632 # number of demand (read+write) misses 745system.cpu.icache.overall_misses::cpu.inst 201632 # number of overall misses 746system.cpu.icache.overall_misses::total 201632 # number of overall misses 747system.cpu.icache.ReadReq_miss_latency::cpu.inst 1282836497 # number of ReadReq miss cycles 748system.cpu.icache.ReadReq_miss_latency::total 1282836497 # number of ReadReq miss cycles 749system.cpu.icache.demand_miss_latency::cpu.inst 1282836497 # number of demand (read+write) miss cycles 750system.cpu.icache.demand_miss_latency::total 1282836497 # number of demand (read+write) miss cycles 751system.cpu.icache.overall_miss_latency::cpu.inst 1282836497 # number of overall miss cycles 752system.cpu.icache.overall_miss_latency::total 1282836497 # number of overall miss cycles 753system.cpu.icache.ReadReq_accesses::cpu.inst 179424674 # number of ReadReq accesses(hits+misses) 754system.cpu.icache.ReadReq_accesses::total 179424674 # number of ReadReq accesses(hits+misses) 755system.cpu.icache.demand_accesses::cpu.inst 179424674 # number of demand (read+write) accesses 756system.cpu.icache.demand_accesses::total 179424674 # number of demand (read+write) accesses 757system.cpu.icache.overall_accesses::cpu.inst 179424674 # number of overall (read+write) accesses 758system.cpu.icache.overall_accesses::total 179424674 # number of overall (read+write) accesses 759system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001124 # miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_miss_rate::total 0.001124 # miss rate for ReadReq accesses 761system.cpu.icache.demand_miss_rate::cpu.inst 0.001124 # miss rate for demand accesses 762system.cpu.icache.demand_miss_rate::total 0.001124 # miss rate for demand accesses 763system.cpu.icache.overall_miss_rate::cpu.inst 0.001124 # miss rate for overall accesses 764system.cpu.icache.overall_miss_rate::total 0.001124 # miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6362.266391 # average ReadReq miss latency 766system.cpu.icache.ReadReq_avg_miss_latency::total 6362.266391 # average ReadReq miss latency 767system.cpu.icache.demand_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency 768system.cpu.icache.demand_avg_miss_latency::total 6362.266391 # average overall miss latency 769system.cpu.icache.overall_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency 770system.cpu.icache.overall_avg_miss_latency::total 6362.266391 # average overall miss latency 771system.cpu.icache.blocked_cycles::no_mshrs 972 # number of cycles access was blocked 772system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 773system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked 774system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 775system.cpu.icache.avg_blocked_cycles::no_mshrs 60.750000 # average number of cycles each access was blocked 776system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 728system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 730system.cpu.icache.tags.age_task_id_blocks_1024::3 313 # Occupied blocks per task id 731system.cpu.icache.tags.age_task_id_blocks_1024::4 1156 # Occupied blocks per task id 732system.cpu.icache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id 733system.cpu.icache.tags.tag_accesses 359075141 # Number of tag accesses 734system.cpu.icache.tags.data_accesses 359075141 # Number of data accesses 735system.cpu.icache.ReadReq_hits::cpu.inst 179236865 # number of ReadReq hits 736system.cpu.icache.ReadReq_hits::total 179236865 # number of ReadReq hits 737system.cpu.icache.demand_hits::cpu.inst 179236865 # number of demand (read+write) hits 738system.cpu.icache.demand_hits::total 179236865 # number of demand (read+write) hits 739system.cpu.icache.overall_hits::cpu.inst 179236865 # number of overall hits 740system.cpu.icache.overall_hits::total 179236865 # number of overall hits 741system.cpu.icache.ReadReq_misses::cpu.inst 201330 # number of ReadReq misses 742system.cpu.icache.ReadReq_misses::total 201330 # number of ReadReq misses 743system.cpu.icache.demand_misses::cpu.inst 201330 # number of demand (read+write) misses 744system.cpu.icache.demand_misses::total 201330 # number of demand (read+write) misses 745system.cpu.icache.overall_misses::cpu.inst 201330 # number of overall misses 746system.cpu.icache.overall_misses::total 201330 # number of overall misses 747system.cpu.icache.ReadReq_miss_latency::cpu.inst 1280282499 # number of ReadReq miss cycles 748system.cpu.icache.ReadReq_miss_latency::total 1280282499 # number of ReadReq miss cycles 749system.cpu.icache.demand_miss_latency::cpu.inst 1280282499 # number of demand (read+write) miss cycles 750system.cpu.icache.demand_miss_latency::total 1280282499 # number of demand (read+write) miss cycles 751system.cpu.icache.overall_miss_latency::cpu.inst 1280282499 # number of overall miss cycles 752system.cpu.icache.overall_miss_latency::total 1280282499 # number of overall miss cycles 753system.cpu.icache.ReadReq_accesses::cpu.inst 179438195 # number of ReadReq accesses(hits+misses) 754system.cpu.icache.ReadReq_accesses::total 179438195 # number of ReadReq accesses(hits+misses) 755system.cpu.icache.demand_accesses::cpu.inst 179438195 # number of demand (read+write) accesses 756system.cpu.icache.demand_accesses::total 179438195 # number of demand (read+write) accesses 757system.cpu.icache.overall_accesses::cpu.inst 179438195 # number of overall (read+write) accesses 758system.cpu.icache.overall_accesses::total 179438195 # number of overall (read+write) accesses 759system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001122 # miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_miss_rate::total 0.001122 # miss rate for ReadReq accesses 761system.cpu.icache.demand_miss_rate::cpu.inst 0.001122 # miss rate for demand accesses 762system.cpu.icache.demand_miss_rate::total 0.001122 # miss rate for demand accesses 763system.cpu.icache.overall_miss_rate::cpu.inst 0.001122 # miss rate for overall accesses 764system.cpu.icache.overall_miss_rate::total 0.001122 # miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6359.124318 # average ReadReq miss latency 766system.cpu.icache.ReadReq_avg_miss_latency::total 6359.124318 # average ReadReq miss latency 767system.cpu.icache.demand_avg_miss_latency::cpu.inst 6359.124318 # average overall miss latency 768system.cpu.icache.demand_avg_miss_latency::total 6359.124318 # average overall miss latency 769system.cpu.icache.overall_avg_miss_latency::cpu.inst 6359.124318 # average overall miss latency 770system.cpu.icache.overall_avg_miss_latency::total 6359.124318 # average overall miss latency 771system.cpu.icache.blocked_cycles::no_mshrs 947 # number of cycles access was blocked 772system.cpu.icache.blocked_cycles::no_targets 40 # number of cycles access was blocked 773system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked 774system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 775system.cpu.icache.avg_blocked_cycles::no_mshrs 63.133333 # average number of cycles each access was blocked 776system.cpu.icache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked |
| 777system.cpu.icache.fast_writes 0 # number of fast writes performed 778system.cpu.icache.cache_copies 0 # number of cache copies performed | 777system.cpu.icache.fast_writes 0 # number of fast writes performed 778system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 779system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2599 # number of ReadReq MSHR hits 780system.cpu.icache.ReadReq_mshr_hits::total 2599 # number of ReadReq MSHR hits 781system.cpu.icache.demand_mshr_hits::cpu.inst 2599 # number of demand (read+write) MSHR hits 782system.cpu.icache.demand_mshr_hits::total 2599 # number of demand (read+write) MSHR hits 783system.cpu.icache.overall_mshr_hits::cpu.inst 2599 # number of overall MSHR hits 784system.cpu.icache.overall_mshr_hits::total 2599 # number of overall MSHR hits 785system.cpu.icache.ReadReq_mshr_misses::cpu.inst 199033 # number of ReadReq MSHR misses 786system.cpu.icache.ReadReq_mshr_misses::total 199033 # number of ReadReq MSHR misses 787system.cpu.icache.demand_mshr_misses::cpu.inst 199033 # number of demand (read+write) MSHR misses 788system.cpu.icache.demand_mshr_misses::total 199033 # number of demand (read+write) MSHR misses 789system.cpu.icache.overall_mshr_misses::cpu.inst 199033 # number of overall MSHR misses 790system.cpu.icache.overall_mshr_misses::total 199033 # number of overall MSHR misses 791system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 971187998 # number of ReadReq MSHR miss cycles 792system.cpu.icache.ReadReq_mshr_miss_latency::total 971187998 # number of ReadReq MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::cpu.inst 971187998 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.demand_mshr_miss_latency::total 971187998 # number of demand (read+write) MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::cpu.inst 971187998 # number of overall MSHR miss cycles 796system.cpu.icache.overall_mshr_miss_latency::total 971187998 # number of overall MSHR miss cycles 797system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for ReadReq accesses 798system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001109 # mshr miss rate for ReadReq accesses 799system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for demand accesses 800system.cpu.icache.demand_mshr_miss_rate::total 0.001109 # mshr miss rate for demand accesses 801system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for overall accesses 802system.cpu.icache.overall_mshr_miss_rate::total 0.001109 # mshr miss rate for overall accesses 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4879.532530 # average ReadReq mshr miss latency 804system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4879.532530 # average ReadReq mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency 806system.cpu.icache.demand_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency 808system.cpu.icache.overall_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency | 779system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2576 # number of ReadReq MSHR hits 780system.cpu.icache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits 781system.cpu.icache.demand_mshr_hits::cpu.inst 2576 # number of demand (read+write) MSHR hits 782system.cpu.icache.demand_mshr_hits::total 2576 # number of demand (read+write) MSHR hits 783system.cpu.icache.overall_mshr_hits::cpu.inst 2576 # number of overall MSHR hits 784system.cpu.icache.overall_mshr_hits::total 2576 # number of overall MSHR hits 785system.cpu.icache.ReadReq_mshr_misses::cpu.inst 198754 # number of ReadReq MSHR misses 786system.cpu.icache.ReadReq_mshr_misses::total 198754 # number of ReadReq MSHR misses 787system.cpu.icache.demand_mshr_misses::cpu.inst 198754 # number of demand (read+write) MSHR misses 788system.cpu.icache.demand_mshr_misses::total 198754 # number of demand (read+write) MSHR misses 789system.cpu.icache.overall_mshr_misses::cpu.inst 198754 # number of overall MSHR misses 790system.cpu.icache.overall_mshr_misses::total 198754 # number of overall MSHR misses 791system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 967804499 # number of ReadReq MSHR miss cycles 792system.cpu.icache.ReadReq_mshr_miss_latency::total 967804499 # number of ReadReq MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::cpu.inst 967804499 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.demand_mshr_miss_latency::total 967804499 # number of demand (read+write) MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::cpu.inst 967804499 # number of overall MSHR miss cycles 796system.cpu.icache.overall_mshr_miss_latency::total 967804499 # number of overall MSHR miss cycles 797system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001108 # mshr miss rate for ReadReq accesses 798system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001108 # mshr miss rate for ReadReq accesses 799system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001108 # mshr miss rate for demand accesses 800system.cpu.icache.demand_mshr_miss_rate::total 0.001108 # mshr miss rate for demand accesses 801system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001108 # mshr miss rate for overall accesses 802system.cpu.icache.overall_mshr_miss_rate::total 0.001108 # mshr miss rate for overall accesses 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4869.358599 # average ReadReq mshr miss latency 804system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4869.358599 # average ReadReq mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4869.358599 # average overall mshr miss latency 806system.cpu.icache.demand_avg_mshr_miss_latency::total 4869.358599 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4869.358599 # average overall mshr miss latency 808system.cpu.icache.overall_avg_mshr_miss_latency::total 4869.358599 # average overall mshr miss latency |
| 809system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 809system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 810system.cpu.l2cache.tags.replacements 354039 # number of replacements 811system.cpu.l2cache.tags.tagsinuse 29616.478826 # Cycle average of tags in use 812system.cpu.l2cache.tags.total_refs 3899597 # Total number of references to valid blocks. 813system.cpu.l2cache.tags.sampled_refs 386397 # Sample count of references to valid blocks. 814system.cpu.l2cache.tags.avg_refs 10.092203 # Average number of references to valid blocks. | 810system.cpu.l2cache.tags.replacements 354031 # number of replacements 811system.cpu.l2cache.tags.tagsinuse 29616.745203 # Cycle average of tags in use 812system.cpu.l2cache.tags.total_refs 3899360 # Total number of references to valid blocks. 813system.cpu.l2cache.tags.sampled_refs 386379 # Sample count of references to valid blocks. 814system.cpu.l2cache.tags.avg_refs 10.092060 # Average number of references to valid blocks. |
| 815system.cpu.l2cache.tags.warmup_cycle 197715227000 # Cycle when the warmup percentage was hit. | 815system.cpu.l2cache.tags.warmup_cycle 197715227000 # Cycle when the warmup percentage was hit. |
| 816system.cpu.l2cache.tags.occ_blocks::writebacks 20954.813586 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.117391 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.547849 # Average occupied blocks per requestor 819system.cpu.l2cache.tags.occ_percent::writebacks 0.639490 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007663 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::cpu.data 0.256670 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_percent::total 0.903823 # Average percentage of cache occupancy 823system.cpu.l2cache.tags.occ_task_id_blocks::1024 32358 # Occupied blocks per task id | 816system.cpu.l2cache.tags.occ_blocks::writebacks 20955.071178 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.225127 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.448899 # Average occupied blocks per requestor 819system.cpu.l2cache.tags.occ_percent::writebacks 0.639498 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007667 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::cpu.data 0.256667 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_percent::total 0.903831 # Average percentage of cache occupancy 823system.cpu.l2cache.tags.occ_task_id_blocks::1024 32348 # Occupied blocks per task id |
| 824system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id | 824system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id |
| 825system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13367 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18661 # Occupied blocks per task id 829system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987488 # Percentage of cache occupancy per task id 830system.cpu.l2cache.tags.tag_accesses 43296958 # Number of tag accesses 831system.cpu.l2cache.tags.data_accesses 43296958 # Number of data accesses 832system.cpu.l2cache.Writeback_hits::writebacks 2332718 # number of Writeback hits 833system.cpu.l2cache.Writeback_hits::total 2332718 # number of Writeback hits 834system.cpu.l2cache.UpgradeReq_hits::cpu.data 1894 # number of UpgradeReq hits 835system.cpu.l2cache.UpgradeReq_hits::total 1894 # number of UpgradeReq hits 836system.cpu.l2cache.ReadExReq_hits::cpu.data 564156 # number of ReadExReq hits 837system.cpu.l2cache.ReadExReq_hits::total 564156 # number of ReadExReq hits 838system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5160 # number of ReadCleanReq hits 839system.cpu.l2cache.ReadCleanReq_hits::total 5160 # number of ReadCleanReq hits 840system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590936 # number of ReadSharedReq hits 841system.cpu.l2cache.ReadSharedReq_hits::total 1590936 # number of ReadSharedReq hits 842system.cpu.l2cache.demand_hits::cpu.inst 5160 # number of demand (read+write) hits 843system.cpu.l2cache.demand_hits::cpu.data 2155092 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::total 2160252 # number of demand (read+write) hits 845system.cpu.l2cache.overall_hits::cpu.inst 5160 # number of overall hits 846system.cpu.l2cache.overall_hits::cpu.data 2155092 # number of overall hits 847system.cpu.l2cache.overall_hits::total 2160252 # number of overall hits 848system.cpu.l2cache.UpgradeReq_misses::cpu.data 188379 # number of UpgradeReq misses 849system.cpu.l2cache.UpgradeReq_misses::total 188379 # number of UpgradeReq misses 850system.cpu.l2cache.ReadExReq_misses::cpu.data 206660 # number of ReadExReq misses 851system.cpu.l2cache.ReadExReq_misses::total 206660 # number of ReadExReq misses 852system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3483 # number of ReadCleanReq misses 853system.cpu.l2cache.ReadCleanReq_misses::total 3483 # number of ReadCleanReq misses 854system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176617 # number of ReadSharedReq misses 855system.cpu.l2cache.ReadSharedReq_misses::total 176617 # number of ReadSharedReq misses 856system.cpu.l2cache.demand_misses::cpu.inst 3483 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.data 383277 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::total 386760 # number of demand (read+write) misses 859system.cpu.l2cache.overall_misses::cpu.inst 3483 # number of overall misses 860system.cpu.l2cache.overall_misses::cpu.data 383277 # number of overall misses 861system.cpu.l2cache.overall_misses::total 386760 # number of overall misses 862system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13128500 # number of UpgradeReq miss cycles 863system.cpu.l2cache.UpgradeReq_miss_latency::total 13128500 # number of UpgradeReq miss cycles 864system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382009500 # number of ReadExReq miss cycles 865system.cpu.l2cache.ReadExReq_miss_latency::total 16382009500 # number of ReadExReq miss cycles 866system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 282985000 # number of ReadCleanReq miss cycles 867system.cpu.l2cache.ReadCleanReq_miss_latency::total 282985000 # number of ReadCleanReq miss cycles 868system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14212128500 # number of ReadSharedReq miss cycles 869system.cpu.l2cache.ReadSharedReq_miss_latency::total 14212128500 # number of ReadSharedReq miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.inst 282985000 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.data 30594138000 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::total 30877123000 # number of demand (read+write) miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.inst 282985000 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.data 30594138000 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::total 30877123000 # number of overall miss cycles 876system.cpu.l2cache.Writeback_accesses::writebacks 2332718 # number of Writeback accesses(hits+misses) 877system.cpu.l2cache.Writeback_accesses::total 2332718 # number of Writeback accesses(hits+misses) 878system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190273 # number of UpgradeReq accesses(hits+misses) 879system.cpu.l2cache.UpgradeReq_accesses::total 190273 # number of UpgradeReq accesses(hits+misses) 880system.cpu.l2cache.ReadExReq_accesses::cpu.data 770816 # number of ReadExReq accesses(hits+misses) 881system.cpu.l2cache.ReadExReq_accesses::total 770816 # number of ReadExReq accesses(hits+misses) 882system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8643 # number of ReadCleanReq accesses(hits+misses) 883system.cpu.l2cache.ReadCleanReq_accesses::total 8643 # number of ReadCleanReq accesses(hits+misses) 884system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1767553 # number of ReadSharedReq accesses(hits+misses) 885system.cpu.l2cache.ReadSharedReq_accesses::total 1767553 # number of ReadSharedReq accesses(hits+misses) 886system.cpu.l2cache.demand_accesses::cpu.inst 8643 # number of demand (read+write) accesses 887system.cpu.l2cache.demand_accesses::cpu.data 2538369 # number of demand (read+write) accesses 888system.cpu.l2cache.demand_accesses::total 2547012 # number of demand (read+write) accesses 889system.cpu.l2cache.overall_accesses::cpu.inst 8643 # number of overall (read+write) accesses 890system.cpu.l2cache.overall_accesses::cpu.data 2538369 # number of overall (read+write) accesses 891system.cpu.l2cache.overall_accesses::total 2547012 # number of overall (read+write) accesses 892system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990046 # miss rate for UpgradeReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990046 # miss rate for UpgradeReq accesses 894system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268105 # miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::total 0.268105 # miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.402985 # miss rate for ReadCleanReq accesses 897system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.402985 # miss rate for ReadCleanReq accesses 898system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099922 # miss rate for ReadSharedReq accesses 899system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099922 # miss rate for ReadSharedReq accesses 900system.cpu.l2cache.demand_miss_rate::cpu.inst 0.402985 # miss rate for demand accesses 901system.cpu.l2cache.demand_miss_rate::cpu.data 0.150993 # miss rate for demand accesses 902system.cpu.l2cache.demand_miss_rate::total 0.151849 # miss rate for demand accesses 903system.cpu.l2cache.overall_miss_rate::cpu.inst 0.402985 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::cpu.data 0.150993 # miss rate for overall accesses 905system.cpu.l2cache.overall_miss_rate::total 0.151849 # miss rate for overall accesses 906system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.691951 # average UpgradeReq miss latency 907system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.691951 # average UpgradeReq miss latency 908system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79270.345011 # average ReadExReq miss latency 909system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79270.345011 # average ReadExReq miss latency 910system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81247.487798 # average ReadCleanReq miss latency 911system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81247.487798 # average ReadCleanReq miss latency 912system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80468.632691 # average ReadSharedReq miss latency 913system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80468.632691 # average ReadSharedReq miss latency 914system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81247.487798 # average overall miss latency 915system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79822.525223 # average overall miss latency 916system.cpu.l2cache.demand_avg_miss_latency::total 79835.357845 # average overall miss latency 917system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81247.487798 # average overall miss latency 918system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79822.525223 # average overall miss latency 919system.cpu.l2cache.overall_avg_miss_latency::total 79835.357845 # average overall miss latency | 825system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13348 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18673 # Occupied blocks per task id 829system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987183 # Percentage of cache occupancy per task id 830system.cpu.l2cache.tags.tag_accesses 43294513 # Number of tag accesses 831system.cpu.l2cache.tags.data_accesses 43294513 # Number of data accesses 832system.cpu.l2cache.Writeback_hits::writebacks 2332705 # number of Writeback hits 833system.cpu.l2cache.Writeback_hits::total 2332705 # number of Writeback hits 834system.cpu.l2cache.UpgradeReq_hits::cpu.data 1885 # number of UpgradeReq hits 835system.cpu.l2cache.UpgradeReq_hits::total 1885 # number of UpgradeReq hits 836system.cpu.l2cache.ReadExReq_hits::cpu.data 564153 # number of ReadExReq hits 837system.cpu.l2cache.ReadExReq_hits::total 564153 # number of ReadExReq hits 838system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5133 # number of ReadCleanReq hits 839system.cpu.l2cache.ReadCleanReq_hits::total 5133 # number of ReadCleanReq hits 840system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590938 # number of ReadSharedReq hits 841system.cpu.l2cache.ReadSharedReq_hits::total 1590938 # number of ReadSharedReq hits 842system.cpu.l2cache.demand_hits::cpu.inst 5133 # number of demand (read+write) hits 843system.cpu.l2cache.demand_hits::cpu.data 2155091 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::total 2160224 # number of demand (read+write) hits 845system.cpu.l2cache.overall_hits::cpu.inst 5133 # number of overall hits 846system.cpu.l2cache.overall_hits::cpu.data 2155091 # number of overall hits 847system.cpu.l2cache.overall_hits::total 2160224 # number of overall hits 848system.cpu.l2cache.UpgradeReq_misses::cpu.data 188135 # number of UpgradeReq misses 849system.cpu.l2cache.UpgradeReq_misses::total 188135 # number of UpgradeReq misses 850system.cpu.l2cache.ReadExReq_misses::cpu.data 206662 # number of ReadExReq misses 851system.cpu.l2cache.ReadExReq_misses::total 206662 # number of ReadExReq misses 852system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3478 # number of ReadCleanReq misses 853system.cpu.l2cache.ReadCleanReq_misses::total 3478 # number of ReadCleanReq misses 854system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176611 # number of ReadSharedReq misses 855system.cpu.l2cache.ReadSharedReq_misses::total 176611 # number of ReadSharedReq misses 856system.cpu.l2cache.demand_misses::cpu.inst 3478 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.data 383273 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::total 386751 # number of demand (read+write) misses 859system.cpu.l2cache.overall_misses::cpu.inst 3478 # number of overall misses 860system.cpu.l2cache.overall_misses::cpu.data 383273 # number of overall misses 861system.cpu.l2cache.overall_misses::total 386751 # number of overall misses 862system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13341000 # number of UpgradeReq miss cycles 863system.cpu.l2cache.UpgradeReq_miss_latency::total 13341000 # number of UpgradeReq miss cycles 864system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16380998500 # number of ReadExReq miss cycles 865system.cpu.l2cache.ReadExReq_miss_latency::total 16380998500 # number of ReadExReq miss cycles 866system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 281189000 # number of ReadCleanReq miss cycles 867system.cpu.l2cache.ReadCleanReq_miss_latency::total 281189000 # number of ReadCleanReq miss cycles 868system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14213384500 # number of ReadSharedReq miss cycles 869system.cpu.l2cache.ReadSharedReq_miss_latency::total 14213384500 # number of ReadSharedReq miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.inst 281189000 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.data 30594383000 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::total 30875572000 # number of demand (read+write) miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.inst 281189000 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.data 30594383000 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::total 30875572000 # number of overall miss cycles 876system.cpu.l2cache.Writeback_accesses::writebacks 2332705 # number of Writeback accesses(hits+misses) 877system.cpu.l2cache.Writeback_accesses::total 2332705 # number of Writeback accesses(hits+misses) 878system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190020 # number of UpgradeReq accesses(hits+misses) 879system.cpu.l2cache.UpgradeReq_accesses::total 190020 # number of UpgradeReq accesses(hits+misses) 880system.cpu.l2cache.ReadExReq_accesses::cpu.data 770815 # number of ReadExReq accesses(hits+misses) 881system.cpu.l2cache.ReadExReq_accesses::total 770815 # number of ReadExReq accesses(hits+misses) 882system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8611 # number of ReadCleanReq accesses(hits+misses) 883system.cpu.l2cache.ReadCleanReq_accesses::total 8611 # number of ReadCleanReq accesses(hits+misses) 884system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1767549 # number of ReadSharedReq accesses(hits+misses) 885system.cpu.l2cache.ReadSharedReq_accesses::total 1767549 # number of ReadSharedReq accesses(hits+misses) 886system.cpu.l2cache.demand_accesses::cpu.inst 8611 # number of demand (read+write) accesses 887system.cpu.l2cache.demand_accesses::cpu.data 2538364 # number of demand (read+write) accesses 888system.cpu.l2cache.demand_accesses::total 2546975 # number of demand (read+write) accesses 889system.cpu.l2cache.overall_accesses::cpu.inst 8611 # number of overall (read+write) accesses 890system.cpu.l2cache.overall_accesses::cpu.data 2538364 # number of overall (read+write) accesses 891system.cpu.l2cache.overall_accesses::total 2546975 # number of overall (read+write) accesses 892system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990080 # miss rate for UpgradeReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990080 # miss rate for UpgradeReq accesses 894system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268108 # miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::total 0.268108 # miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.403902 # miss rate for ReadCleanReq accesses 897system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.403902 # miss rate for ReadCleanReq accesses 898system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099919 # miss rate for ReadSharedReq accesses 899system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099919 # miss rate for ReadSharedReq accesses 900system.cpu.l2cache.demand_miss_rate::cpu.inst 0.403902 # miss rate for demand accesses 901system.cpu.l2cache.demand_miss_rate::cpu.data 0.150992 # miss rate for demand accesses 902system.cpu.l2cache.demand_miss_rate::total 0.151847 # miss rate for demand accesses 903system.cpu.l2cache.overall_miss_rate::cpu.inst 0.403902 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::cpu.data 0.150992 # miss rate for overall accesses 905system.cpu.l2cache.overall_miss_rate::total 0.151847 # miss rate for overall accesses 906system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 70.911845 # average UpgradeReq miss latency 907system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 70.911845 # average UpgradeReq miss latency 908system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79264.685815 # average ReadExReq miss latency 909system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79264.685815 # average ReadExReq miss latency 910system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80847.901093 # average ReadCleanReq miss latency 911system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80847.901093 # average ReadCleanReq miss latency 912system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80478.478124 # average ReadSharedReq miss latency 913system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80478.478124 # average ReadSharedReq miss latency 914system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80847.901093 # average overall miss latency 915system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79823.997516 # average overall miss latency 916system.cpu.l2cache.demand_avg_miss_latency::total 79833.205344 # average overall miss latency 917system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80847.901093 # average overall miss latency 918system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79823.997516 # average overall miss latency 919system.cpu.l2cache.overall_avg_miss_latency::total 79833.205344 # average overall miss latency |
| 920system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 925system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu.l2cache.fast_writes 0 # number of fast writes performed 927system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 920system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 925system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu.l2cache.fast_writes 0 # number of fast writes performed 927system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 928system.cpu.l2cache.writebacks::writebacks 295055 # number of writebacks 929system.cpu.l2cache.writebacks::total 295055 # number of writebacks | 928system.cpu.l2cache.writebacks::writebacks 295046 # number of writebacks 929system.cpu.l2cache.writebacks::total 295046 # number of writebacks |
| 930system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 931system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 932system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 933system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 934system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 935system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 930system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 931system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 932system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 933system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 934system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 935system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 936system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1999 # number of CleanEvict MSHR misses 937system.cpu.l2cache.CleanEvict_mshr_misses::total 1999 # number of CleanEvict MSHR misses 938system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 188379 # number of UpgradeReq MSHR misses 939system.cpu.l2cache.UpgradeReq_mshr_misses::total 188379 # number of UpgradeReq MSHR misses 940system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206660 # number of ReadExReq MSHR misses 941system.cpu.l2cache.ReadExReq_mshr_misses::total 206660 # number of ReadExReq MSHR misses 942system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3482 # number of ReadCleanReq MSHR misses 943system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3482 # number of ReadCleanReq MSHR misses 944system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176617 # number of ReadSharedReq MSHR misses 945system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176617 # number of ReadSharedReq MSHR misses 946system.cpu.l2cache.demand_mshr_misses::cpu.inst 3482 # number of demand (read+write) MSHR misses 947system.cpu.l2cache.demand_mshr_misses::cpu.data 383277 # number of demand (read+write) MSHR misses 948system.cpu.l2cache.demand_mshr_misses::total 386759 # number of demand (read+write) MSHR misses 949system.cpu.l2cache.overall_mshr_misses::cpu.inst 3482 # number of overall MSHR misses 950system.cpu.l2cache.overall_mshr_misses::cpu.data 383277 # number of overall MSHR misses 951system.cpu.l2cache.overall_mshr_misses::total 386759 # number of overall MSHR misses 952system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3964257964 # number of UpgradeReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3964257964 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14315409500 # number of ReadExReq MSHR miss cycles 955system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14315409500 # number of ReadExReq MSHR miss cycles 956system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248098000 # 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number of overall MSHR miss cycles |
| 966system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 967system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 966system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 967system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 968system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990046 # mshr miss rate for UpgradeReq accesses 969system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990046 # mshr miss rate for UpgradeReq accesses 970system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268105 # mshr miss rate for ReadExReq accesses 971system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268105 # mshr miss rate for ReadExReq accesses 972system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for ReadCleanReq accesses 973system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.402869 # mshr miss rate for ReadCleanReq accesses 974system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099922 # mshr miss rate for ReadSharedReq accesses 975system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099922 # mshr miss rate for ReadSharedReq accesses 976system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for demand accesses 977system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for demand accesses 978system.cpu.l2cache.demand_mshr_miss_rate::total 0.151848 # mshr miss rate for demand accesses 979system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for overall accesses 980system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for overall accesses 981system.cpu.l2cache.overall_mshr_miss_rate::total 0.151848 # mshr miss rate for overall accesses 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21044.054613 # average UpgradeReq mshr miss latency 983system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21044.054613 # average UpgradeReq mshr miss latency 984system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69270.345011 # average ReadExReq mshr miss latency 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69270.345011 # average ReadExReq mshr miss latency 986system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71251.579552 # average ReadCleanReq mshr miss latency 987system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71251.579552 # average ReadCleanReq mshr miss latency 988system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70468.632691 # average ReadSharedReq mshr miss latency 989system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70468.632691 # average ReadSharedReq mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency 991system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency 992system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency 994system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency 995system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency | 968system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990080 # mshr miss rate for UpgradeReq accesses 969system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990080 # mshr miss rate for UpgradeReq accesses 970system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268108 # mshr miss rate for ReadExReq accesses 971system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268108 # mshr miss rate for ReadExReq accesses 972system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.403786 # mshr miss rate for ReadCleanReq accesses 973system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.403786 # mshr miss rate for ReadCleanReq accesses 974system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099919 # mshr miss rate for ReadSharedReq accesses 975system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099919 # mshr miss rate for ReadSharedReq accesses 976system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.403786 # mshr miss rate for demand accesses 977system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150992 # mshr miss rate for demand accesses 978system.cpu.l2cache.demand_mshr_miss_rate::total 0.151847 # mshr miss rate for demand accesses 979system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.403786 # mshr miss rate for overall accesses 980system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150992 # mshr miss rate for overall accesses 981system.cpu.l2cache.overall_mshr_miss_rate::total 0.151847 # mshr miss rate for overall accesses 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21043.265299 # average UpgradeReq mshr miss latency 983system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21043.265299 # average UpgradeReq mshr miss latency 984system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69264.685815 # average ReadExReq mshr miss latency 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69264.685815 # average ReadExReq mshr miss latency 986system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70857.635893 # average ReadCleanReq mshr miss latency 987system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70857.635893 # average ReadCleanReq mshr miss latency 988system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70478.478124 # average ReadSharedReq mshr miss latency 989system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70478.478124 # average ReadSharedReq mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70857.635893 # average overall mshr miss latency 991system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69823.997516 # average overall mshr miss latency 992system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69833.290239 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70857.635893 # average overall mshr miss latency 994system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69823.997516 # average overall mshr miss latency 995system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69833.290239 # average overall mshr miss latency |
| 996system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 996system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 997system.cpu.toL2Bus.trans_dist::ReadResp 1966585 # Transaction distribution 998system.cpu.toL2Bus.trans_dist::Writeback 2627773 # Transaction distribution 999system.cpu.toL2Bus.trans_dist::CleanEvict 256159 # Transaction distribution 1000system.cpu.toL2Bus.trans_dist::UpgradeReq 190273 # Transaction distribution 1001system.cpu.toL2Bus.trans_dist::UpgradeResp 190273 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::ReadExReq 770816 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::ReadExResp 770816 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::ReadCleanReq 199033 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767553 # Transaction distribution 1006system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214213 # Packet count per connected master and slave (bytes) 1007system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7980639 # Packet count per connected master and slave (bytes) 1008system.cpu.toL2Bus.pkt_count::total 8194852 # Packet count per connected master and slave (bytes) 1009system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553088 # Cumulative packet size per connected master and slave (bytes) 1010system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311749568 # Cumulative packet size per connected master and slave (bytes) 1011system.cpu.toL2Bus.pkt_size::total 312302656 # Cumulative packet size per connected master and slave (bytes) 1012system.cpu.toL2Bus.snoops 544429 # Total snoops (count) 1013system.cpu.toL2Bus.snoop_fanout::samples 5822983 # Request fanout histogram 1014system.cpu.toL2Bus.snoop_fanout::mean 1.060800 # Request fanout histogram 1015system.cpu.toL2Bus.snoop_fanout::stdev 0.238964 # Request fanout histogram | 997system.cpu.toL2Bus.trans_dist::ReadResp 1966300 # Transaction distribution 998system.cpu.toL2Bus.trans_dist::Writeback 2627751 # Transaction distribution 999system.cpu.toL2Bus.trans_dist::CleanEvict 256160 # Transaction distribution 1000system.cpu.toL2Bus.trans_dist::UpgradeReq 190020 # Transaction distribution 1001system.cpu.toL2Bus.trans_dist::UpgradeResp 190020 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::ReadExReq 770815 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::ReadExResp 770815 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::ReadCleanReq 198754 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767549 # Transaction distribution 1006system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 213879 # Packet count per connected master and slave (bytes) 1007system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7980131 # Packet count per connected master and slave (bytes) 1008system.cpu.toL2Bus.pkt_count::total 8194010 # Packet count per connected master and slave (bytes) 1009system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550912 # Cumulative packet size per connected master and slave (bytes) 1010system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311748416 # Cumulative packet size per connected master and slave (bytes) 1011system.cpu.toL2Bus.pkt_size::total 312299328 # Cumulative packet size per connected master and slave (bytes) 1012system.cpu.toL2Bus.snoops 544174 # Total snoops (count) 1013system.cpu.toL2Bus.snoop_fanout::samples 5822413 # Request fanout histogram 1014system.cpu.toL2Bus.snoop_fanout::mean 1.060805 # Request fanout histogram 1015system.cpu.toL2Bus.snoop_fanout::stdev 0.238972 # Request fanout histogram |
| 1016system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1017system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1016system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1017system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1018system.cpu.toL2Bus.snoop_fanout::1 5468944 93.92% 93.92% # Request fanout histogram 1019system.cpu.toL2Bus.snoop_fanout::2 354039 6.08% 100.00% # Request fanout histogram | 1018system.cpu.toL2Bus.snoop_fanout::1 5468382 93.92% 93.92% # Request fanout histogram 1019system.cpu.toL2Bus.snoop_fanout::2 354031 6.08% 100.00% # Request fanout histogram |
| 1020system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1021system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1022system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1020system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1021system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1022system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1023system.cpu.toL2Bus.snoop_fanout::total 5822983 # Request fanout histogram 1024system.cpu.toL2Bus.reqLayer0.occupancy 5095186894 # Layer occupancy (ticks) | 1023system.cpu.toL2Bus.snoop_fanout::total 5822413 # Request fanout histogram 1024system.cpu.toL2Bus.reqLayer0.occupancy 5094765649 # Layer occupancy (ticks) |
| 1025system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) | 1025system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) |
| 1026system.cpu.toL2Bus.respLayer0.occupancy 298551493 # Layer occupancy (ticks) | 1026system.cpu.toL2Bus.respLayer0.occupancy 298130492 # Layer occupancy (ticks) |
| 1027system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1027system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1028system.cpu.toL2Bus.respLayer1.occupancy 3902690569 # Layer occupancy (ticks) | 1028system.cpu.toL2Bus.respLayer1.occupancy 3902557066 # Layer occupancy (ticks) |
| 1029system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) | 1029system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 1030system.membus.trans_dist::ReadResp 180098 # Transaction distribution 1031system.membus.trans_dist::Writeback 295055 # Transaction distribution 1032system.membus.trans_dist::CleanEvict 57423 # Transaction distribution 1033system.membus.trans_dist::UpgradeReq 188421 # Transaction distribution 1034system.membus.trans_dist::UpgradeResp 188421 # Transaction distribution 1035system.membus.trans_dist::ReadExReq 206618 # Transaction distribution 1036system.membus.trans_dist::ReadExResp 206618 # Transaction distribution 1037system.membus.trans_dist::ReadSharedReq 180098 # Transaction distribution 1038system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1502752 # Packet count per connected master and slave (bytes) 1039system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1502752 # Packet count per connected master and slave (bytes) 1040system.membus.pkt_count::total 1502752 # Packet count per connected master and slave (bytes) 1041system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633344 # Cumulative packet size per connected master and slave (bytes) 1042system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633344 # Cumulative packet size per connected master and slave (bytes) 1043system.membus.pkt_size::total 43633344 # Cumulative packet size per connected master and slave (bytes) | 1030system.membus.trans_dist::ReadResp 180085 # Transaction distribution 1031system.membus.trans_dist::Writeback 295046 # Transaction distribution 1032system.membus.trans_dist::CleanEvict 57422 # Transaction distribution 1033system.membus.trans_dist::UpgradeReq 188175 # Transaction distribution 1034system.membus.trans_dist::UpgradeResp 188175 # Transaction distribution 1035system.membus.trans_dist::ReadExReq 206622 # Transaction distribution 1036system.membus.trans_dist::ReadExResp 206622 # Transaction distribution 1037system.membus.trans_dist::ReadSharedReq 180087 # Transaction distribution 1038system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1502234 # Packet count per connected master and slave (bytes) 1039system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1502234 # Packet count per connected master and slave (bytes) 1040system.membus.pkt_count::total 1502234 # Packet count per connected master and slave (bytes) 1041system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43632192 # Cumulative packet size per connected master and slave (bytes) 1042system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43632192 # Cumulative packet size per connected master and slave (bytes) 1043system.membus.pkt_size::total 43632192 # Cumulative packet size per connected master and slave (bytes) |
| 1044system.membus.snoops 0 # Total snoops (count) | 1044system.membus.snoops 0 # Total snoops (count) |
| 1045system.membus.snoop_fanout::samples 927615 # Request fanout histogram | 1045system.membus.snoop_fanout::samples 927352 # Request fanout histogram |
| 1046system.membus.snoop_fanout::mean 0 # Request fanout histogram 1047system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1048system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1046system.membus.snoop_fanout::mean 0 # Request fanout histogram 1047system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1048system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1049system.membus.snoop_fanout::0 927615 100.00% 100.00% # Request fanout histogram | 1049system.membus.snoop_fanout::0 927352 100.00% 100.00% # Request fanout histogram |
| 1050system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1051system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1052system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1053system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1050system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1051system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1052system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1053system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1054system.membus.snoop_fanout::total 927615 # Request fanout histogram 1055system.membus.reqLayer0.occupancy 2233739536 # Layer occupancy (ticks) | 1054system.membus.snoop_fanout::total 927352 # Request fanout histogram 1055system.membus.reqLayer0.occupancy 2233095783 # Layer occupancy (ticks) |
| 1056system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) | 1056system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 1057system.membus.respLayer1.occupancy 2422494891 # Layer occupancy (ticks) | 1057system.membus.respLayer1.occupancy 2421970141 # Layer occupancy (ticks) |
| 1058system.membus.respLayer1.utilization 0.6 # Layer utilization (%) 1059 1060---------- End Simulation Statistics ---------- | 1058system.membus.respLayer1.utilization 0.6 # Layer utilization (%) 1059 1060---------- End Simulation Statistics ---------- |