| stats.txt (10811:e6b20e6b5cf9) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.417785 # Number of seconds simulated 4sim_ticks 417784645500 # Number of ticks simulated 5final_tick 417784645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.417996 # Number of seconds simulated 4sim_ticks 417996021500 # Number of ticks simulated 5final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 77548 # Simulator instruction rate (inst/s) 8host_op_rate 143396 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39181823 # Simulator tick rate (ticks/s) 10host_mem_usage 423644 # Number of bytes of host memory used 11host_seconds 10662.72 # Real time elapsed on the host | 7host_inst_rate 98610 # Simulator instruction rate (inst/s) 8host_op_rate 182341 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49848381 # Simulator tick rate (ticks/s) 10host_mem_usage 430328 # Number of bytes of host memory used 11host_seconds 8385.35 # Real time elapsed on the host |
| 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 225536 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 24761856 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 225536 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 225536 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18818176 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18818176 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3524 # Number of read requests responded to by this memory | 18system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::total 386904 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 294034 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 294034 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 539838 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 58729588 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 59269426 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 539838 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 539838 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 45042766 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 45042766 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 45042766 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 539838 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 58729588 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 104312192 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386904 # Number of read requests accepted 40system.physmem.writeReqs 294034 # Number of write requests accepted 41system.physmem.readBursts 386904 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 294034 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24739840 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18816320 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24761856 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18818176 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue | 25system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386930 # Number of read requests accepted 40system.physmem.writeReqs 294035 # Number of write requests accepted 41system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 50system.physmem.neitherReadNorWriteReqs 194832 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24113 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26506 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24704 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24585 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23284 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23758 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24455 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24304 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23622 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23951 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24786 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24077 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23364 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22990 # Per bank write bursts 65system.physmem.perBankRdBursts::14 24090 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23971 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18545 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19845 # Per bank write bursts 69system.physmem.perBankWrBursts::2 18943 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18938 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18040 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18456 # Per bank write bursts | 50system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24110 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26511 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24689 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24586 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23301 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23773 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24463 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24300 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23625 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23952 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24787 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24070 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23353 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22981 # Per bank write bursts 65system.physmem.perBankRdBursts::14 24097 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23979 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18543 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19847 # Per bank write bursts 69system.physmem.perBankWrBursts::2 18947 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18939 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18047 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18457 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::6 18996 # Per bank write bursts | 73system.physmem.perBankWrBursts::6 18996 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 18987 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18549 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18172 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18834 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17732 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17374 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16972 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 18981 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18548 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18168 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18839 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17728 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17372 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16973 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::14 17820 # Per bank write bursts | 81system.physmem.perBankWrBursts::14 17820 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::15 17802 # Per bank write bursts | 82system.physmem.perBankWrBursts::15 17811 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 417784619000 # Total gap between requests | 85system.physmem.totGap 417995980500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 386904 # Read request sizes (log2) | 92system.physmem.readPktSize::6 386930 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 294034 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381510 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4656 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 343 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 294035 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 6151 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6574 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16911 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17474 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17558 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17562 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17630 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17624 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17632 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17742 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17647 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see | 161system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::30 17830 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17528 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17474 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see |
| 174system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see --- 6 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 174system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see --- 6 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 147384 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 295.518428 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 174.412890 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 322.590500 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54886 37.24% 37.24% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 39792 27.00% 64.24% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13719 9.31% 73.55% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7560 5.13% 78.68% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5573 3.78% 82.46% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3862 2.62% 85.08% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3103 2.11% 87.18% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2674 1.81% 89.00% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16215 11.00% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 147384 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17444 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.159252 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 209.918601 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17431 99.93% 99.93% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 17444 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17444 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.854219 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.780353 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.660093 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17244 98.85% 98.85% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 141 0.81% 99.66% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 26 0.15% 99.81% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 11 0.06% 99.87% # Writes before turning the bus around for reads | 218system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads |
| 227system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads | 227system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads |
| 240system.physmem.wrPerTurnAround::total 17444 # Writes before turning the bus around for reads 241system.physmem.totQLat 4274781750 # Total ticks spent queuing 242system.physmem.totMemAccLat 11522781750 # Total ticks spent from burst creation until serviced by the DRAM 243system.physmem.totBusLat 1932800000 # Total ticks spent in databus transfers 244system.physmem.avgQLat 11058.52 # Average queueing delay per DRAM burst | 240system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads 241system.physmem.totQLat 4282714250 # Total ticks spent queuing 242system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM 243system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers 244system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst |
| 245system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 245system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 246system.physmem.avgMemAccLat 29808.52 # Average memory access latency per DRAM burst 247system.physmem.avgRdBW 59.22 # Average DRAM read bandwidth in MiByte/s 248system.physmem.avgWrBW 45.04 # Average achieved write bandwidth in MiByte/s 249system.physmem.avgRdBWSys 59.27 # Average system read bandwidth in MiByte/s 250system.physmem.avgWrBWSys 45.04 # Average system write bandwidth in MiByte/s | 246system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst 247system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s 248system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s 249system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s 250system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s |
| 251system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 252system.physmem.busUtil 0.81 # Data bus utilization in percentage 253system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads 254system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes 255system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 251system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 252system.physmem.busUtil 0.81 # Data bus utilization in percentage 253system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads 254system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes 255system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 256system.physmem.avgWrQLen 21.29 # Average write queue length when enqueuing 257system.physmem.readRowHits 318043 # Number of row buffer hits during reads 258system.physmem.writeRowHits 215127 # Number of row buffer hits during writes 259system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads 260system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes 261system.physmem.avgGap 613542.82 # Average gap between requests 262system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined 263system.physmem_0.actEnergy 567476280 # Energy for activate commands per rank (pJ) 264system.physmem_0.preEnergy 309634875 # Energy for precharge commands per rank (pJ) 265system.physmem_0.readEnergy 1526389800 # Energy for read commands per rank (pJ) 266system.physmem_0.writeEnergy 976691520 # Energy for write commands per rank (pJ) 267system.physmem_0.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ) 268system.physmem_0.actBackEnergy 63728995635 # Energy for active background per rank (pJ) 269system.physmem_0.preBackEnergy 194764938000 # Energy for precharge background per rank (pJ) 270system.physmem_0.totalEnergy 289161421470 # Total energy per rank (pJ) 271system.physmem_0.averagePower 692.139218 # Core power per rank (mW) 272system.physmem_0.memoryStateTime::IDLE 323446024000 # Time in different power states 273system.physmem_0.memoryStateTime::REF 13950560000 # Time in different power states | 256system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing 257system.physmem.readRowHits 318033 # Number of row buffer hits during reads 258system.physmem.writeRowHits 215097 # Number of row buffer hits during writes 259system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads 260system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes 261system.physmem.avgGap 613828.88 # Average gap between requests 262system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined 263system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ) 264system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ) 265system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ) 266system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ) 267system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) 268system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ) 269system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ) 270system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ) 271system.physmem_0.averagePower 692.167087 # Core power per rank (mW) 272system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states 273system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states |
| 274system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 274system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 275system.physmem_0.memoryStateTime::ACT 80384174500 # Time in different power states | 275system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states |
| 276system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 276system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 277system.physmem_1.actEnergy 546399000 # Energy for activate commands per rank (pJ) 278system.physmem_1.preEnergy 298134375 # Energy for precharge commands per rank (pJ) 279system.physmem_1.readEnergy 1488177600 # Energy for read commands per rank (pJ) 280system.physmem_1.writeEnergy 928104480 # Energy for write commands per rank (pJ) 281system.physmem_1.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ) 282system.physmem_1.actBackEnergy 61807042845 # Energy for active background per rank (pJ) 283system.physmem_1.preBackEnergy 196450861500 # Energy for precharge background per rank (pJ) 284system.physmem_1.totalEnergy 288806015160 # Total energy per rank (pJ) 285system.physmem_1.averagePower 691.288514 # Core power per rank (mW) 286system.physmem_1.memoryStateTime::IDLE 326265955250 # Time in different power states 287system.physmem_1.memoryStateTime::REF 13950560000 # Time in different power states | 277system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ) 278system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ) 279system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ) 280system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ) 281system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) 282system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ) 283system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ) 284system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ) 285system.physmem_1.averagePower 691.276862 # Core power per rank (mW) 286system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states 287system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states |
| 288system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 288system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 289system.physmem_1.memoryStateTime::ACT 77563900250 # Time in different power states | 289system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states |
| 290system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 290system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 291system.cpu.branchPred.lookups 230228501 # Number of BP lookups 292system.cpu.branchPred.condPredicted 230228501 # Number of conditional branches predicted 293system.cpu.branchPred.condIncorrect 9739021 # Number of conditional branches incorrect 294system.cpu.branchPred.BTBLookups 131459692 # Number of BTB lookups 295system.cpu.branchPred.BTBHits 128773186 # Number of BTB hits | 291system.cpu.branchPred.lookups 230262495 # Number of BP lookups 292system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted 293system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect 294system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups 295system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits |
| 296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 297system.cpu.branchPred.BTBHitPct 97.956403 # BTB Hit Percentage 298system.cpu.branchPred.usedRAS 27739164 # Number of times the RAS was used to get a target. 299system.cpu.branchPred.RASInCorrect 1472550 # Number of incorrect RAS predictions. | 297system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage 298system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target. 299system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions. |
| 300system.cpu_clk_domain.clock 500 # Clock period in ticks 301system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 302system.cpu.workload.num_syscalls 551 # Number of system calls | 300system.cpu_clk_domain.clock 500 # Clock period in ticks 301system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 302system.cpu.workload.num_syscalls 551 # Number of system calls |
| 303system.cpu.numCycles 835569292 # number of cpu cycles simulated | 303system.cpu.numCycles 835992044 # number of cpu cycles simulated |
| 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 306system.cpu.fetch.icacheStallCycles 185184379 # Number of cycles fetch is stalled on an Icache miss 307system.cpu.fetch.Insts 1269166320 # Number of instructions fetch has processed 308system.cpu.fetch.Branches 230228501 # Number of branches that fetch encountered 309system.cpu.fetch.predictedBranches 156512350 # Number of branches that fetch has predicted taken 310system.cpu.fetch.Cycles 639147953 # Number of cycles fetch has run and was not squashing or blocked 311system.cpu.fetch.SquashCycles 20213743 # Number of cycles fetch has spent squashing 312system.cpu.fetch.TlbCycles 511 # Number of cycles fetch has spent waiting for tlb 313system.cpu.fetch.MiscStallCycles 99253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 314system.cpu.fetch.PendingTrapStallCycles 822297 # Number of stall cycles due to pending traps 315system.cpu.fetch.PendingQuiesceStallCycles 1772 # Number of stall cycles due to pending quiesce instructions 316system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR 317system.cpu.fetch.CacheLines 179484418 # Number of cache lines fetched 318system.cpu.fetch.IcacheSquashes 2740851 # Number of outstanding Icache misses that were squashed | 306system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss 307system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed 308system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered 309system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken 310system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked 311system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing 312system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb 313system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 314system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps 315system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions 316system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR 317system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched 318system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed |
| 319system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed | 319system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed |
| 320system.cpu.fetch.rateDist::samples 835363066 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::mean 2.826562 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::stdev 3.382493 # Number of instructions fetched each cycle (Total) | 320system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total) |
| 323system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 323system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 324system.cpu.fetch.rateDist::0 427868247 51.22% 51.22% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::1 33702021 4.03% 55.25% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::2 32929710 3.94% 59.20% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::3 33265996 3.98% 63.18% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::4 27012416 3.23% 66.41% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::5 27748723 3.32% 69.73% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::6 36992796 4.43% 74.16% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::7 33648824 4.03% 78.19% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::8 182194333 21.81% 100.00% # Number of instructions fetched each cycle (Total) | 324system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total) |
| 333system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 333system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 336system.cpu.fetch.rateDist::total 835363066 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.branchRate 0.275535 # Number of branch fetches per cycle 338system.cpu.fetch.rate 1.518924 # Number of inst fetches per cycle 339system.cpu.decode.IdleCycles 127510375 # Number of cycles decode is idle 340system.cpu.decode.BlockedCycles 375947418 # Number of cycles decode is blocked 341system.cpu.decode.RunCycles 240571925 # Number of cycles decode is running 342system.cpu.decode.UnblockCycles 81226477 # Number of cycles decode is unblocking 343system.cpu.decode.SquashCycles 10106871 # Number of cycles decode is squashing 344system.cpu.decode.DecodedInsts 2225382694 # Number of instructions handled by decode 345system.cpu.rename.SquashCycles 10106871 # Number of cycles rename is squashing 346system.cpu.rename.IdleCycles 159640008 # Number of cycles rename is idle 347system.cpu.rename.BlockCycles 160513488 # Number of cycles rename is blocking 348system.cpu.rename.serializeStallCycles 42854 # count of cycles rename stalled for serializing inst 349system.cpu.rename.RunCycles 285557624 # Number of cycles rename is running 350system.cpu.rename.UnblockCycles 219502221 # Number of cycles rename is unblocking 351system.cpu.rename.RenamedInsts 2175351414 # Number of instructions processed by rename 352system.cpu.rename.ROBFullEvents 185986 # Number of times rename has blocked due to ROB full 353system.cpu.rename.IQFullEvents 136028392 # Number of times rename has blocked due to IQ full 354system.cpu.rename.LQFullEvents 24255750 # Number of times rename has blocked due to LQ full 355system.cpu.rename.SQFullEvents 49096014 # Number of times rename has blocked due to SQ full 356system.cpu.rename.RenamedOperands 2279465980 # Number of destination operands rename has renamed 357system.cpu.rename.RenameLookups 5501874168 # Number of register rename lookups that rename has made 358system.cpu.rename.int_rename_lookups 3499442561 # Number of integer rename lookups 359system.cpu.rename.fp_rename_lookups 66867 # Number of floating rename lookups | 336system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle 338system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle 339system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle 340system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked 341system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running 342system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking 343system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing 344system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode 345system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing 346system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle 347system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking 348system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst 349system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running 350system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking 351system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename 352system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full 353system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full 354system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full 355system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full 356system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed 357system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made 358system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups 359system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups |
| 360system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed | 360system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed |
| 361system.cpu.rename.UndoneMaps 665425126 # Number of HB maps that are undone due to squashing 362system.cpu.rename.serializingInsts 3167 # count of serializing insts renamed 363system.cpu.rename.tempSerializingInsts 2999 # count of temporary serializing insts renamed 364system.cpu.rename.skidInsts 415602419 # count of insts added to the skid buffer 365system.cpu.memDep0.insertedLoads 528341229 # Number of loads inserted to the mem dependence unit. 366system.cpu.memDep0.insertedStores 209838821 # Number of stores inserted to the mem dependence unit. 367system.cpu.memDep0.conflictingLoads 239501304 # Number of conflicting loads. 368system.cpu.memDep0.conflictingStores 72157646 # Number of conflicting stores. 369system.cpu.iq.iqInstsAdded 2101036293 # Number of instructions added to the IQ (excludes non-spec) 370system.cpu.iq.iqNonSpecInstsAdded 25395 # Number of non-speculative instructions added to the IQ 371system.cpu.iq.iqInstsIssued 1826926557 # Number of instructions issued 372system.cpu.iq.iqSquashedInstsIssued 429463 # Number of squashed instructions issued 373system.cpu.iq.iqSquashedInstsExamined 572072987 # Number of squashed instructions iterated over during squash; mainly for profiling 374system.cpu.iq.iqSquashedOperandsExamined 974001425 # Number of squashed operands that are examined and possibly removed from graph 375system.cpu.iq.iqSquashedNonSpecRemoved 24843 # Number of squashed non-spec instructions that were removed 376system.cpu.iq.issued_per_cycle::samples 835363066 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::mean 2.186985 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::stdev 2.073368 # Number of insts issued each cycle | 361system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing 362system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed 363system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed 364system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer 365system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit. 366system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit. 367system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads. 368system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores. 369system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec) 370system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ 371system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued 372system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued 373system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling 374system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph 375system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed 376system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle |
| 379system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 379system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 380system.cpu.iq.issued_per_cycle::0 255962202 30.64% 30.64% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::1 125607638 15.04% 45.68% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::2 118770145 14.22% 59.89% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::3 111086257 13.30% 73.19% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::4 92824001 11.11% 84.30% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::5 61460839 7.36% 91.66% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::6 43056890 5.15% 96.82% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::7 19182433 2.30% 99.11% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::8 7412661 0.89% 100.00% # Number of insts issued each cycle | 380system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle |
| 389system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 389system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::total 835363066 # Number of insts issued each cycle | 392system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle |
| 393system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 393system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 394system.cpu.iq.fu_full::IntAlu 11317596 42.46% 42.46% # attempts to use FU when none available 395system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available 423system.cpu.iq.fu_full::MemRead 12272214 46.05% 88.51% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemWrite 3062486 11.49% 100.00% # attempts to use FU when none available | 394system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available 395system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available 423system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available |
| 425system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 425system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 427system.cpu.iq.FU_type_0::No_OpClass 2719434 0.15% 0.15% # Type of FU issued 428system.cpu.iq.FU_type_0::IntAlu 1211207278 66.30% 66.45% # Type of FU issued 429system.cpu.iq.FU_type_0::IntMult 389699 0.02% 66.47% # Type of FU issued 430system.cpu.iq.FU_type_0::IntDiv 3880989 0.21% 66.68% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatAdd 135 0.00% 66.68% # Type of FU issued | 427system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued 428system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued 429system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued 430system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued |
| 432system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued | 432system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued |
| 434system.cpu.iq.FU_type_0::FloatMult 39 0.00% 66.68% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued | 434system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued |
| 436system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 449system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued | 436system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 449system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued |
| 457system.cpu.iq.FU_type_0::MemRead 435021653 23.81% 90.49% # Type of FU issued 458system.cpu.iq.FU_type_0::MemWrite 173706920 9.51% 100.00% # Type of FU issued | 457system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued 458system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued |
| 459system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 459system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 461system.cpu.iq.FU_type_0::total 1826926557 # Type of FU issued 462system.cpu.iq.rate 2.186445 # Inst issue rate 463system.cpu.iq.fu_busy_cnt 26652296 # FU busy when requested 464system.cpu.iq.fu_busy_rate 0.014589 # FU busy rate (busy events/executed inst) 465system.cpu.iq.int_inst_queue_reads 4516265766 # Number of integer instruction queue reads 466system.cpu.iq.int_inst_queue_writes 2673396604 # Number of integer instruction queue writes 467system.cpu.iq.int_inst_queue_wakeup_accesses 1796798251 # Number of integer instruction queue wakeup accesses 468system.cpu.iq.fp_inst_queue_reads 32173 # Number of floating instruction queue reads 469system.cpu.iq.fp_inst_queue_writes 70520 # Number of floating instruction queue writes 470system.cpu.iq.fp_inst_queue_wakeup_accesses 7153 # Number of floating instruction queue wakeup accesses 471system.cpu.iq.int_alu_accesses 1850844448 # Number of integer alu accesses 472system.cpu.iq.fp_alu_accesses 14971 # Number of floating point alu accesses 473system.cpu.iew.lsq.thread0.forwLoads 185549711 # Number of loads that had data forwarded from stores | 461system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued 462system.cpu.iq.rate 2.185458 # Inst issue rate 463system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested 464system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst) 465system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads 466system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes 467system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses 468system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads 469system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes 470system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses 471system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses 472system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses 473system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores |
| 474system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 474system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 475system.cpu.iew.lsq.thread0.squashedLoads 144242393 # Number of loads squashed 476system.cpu.iew.lsq.thread0.ignoredResponses 210251 # Number of memory responses ignored because the instruction is squashed 477system.cpu.iew.lsq.thread0.memOrderViolation 386532 # Number of memory ordering violations 478system.cpu.iew.lsq.thread0.squashedStores 60678635 # Number of stores squashed | 475system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed 476system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed 477system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations 478system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed |
| 479system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 480system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 479system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 480system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 481system.cpu.iew.lsq.thread0.rescheduledLoads 19153 # Number of loads that were rescheduled 482system.cpu.iew.lsq.thread0.cacheBlocked 1029 # Number of times an access to memory failed due to the cache being blocked | 481system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled 482system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked |
| 483system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 483system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 484system.cpu.iew.iewSquashCycles 10106871 # Number of cycles IEW is squashing 485system.cpu.iew.iewBlockCycles 107291908 # Number of cycles IEW is blocking 486system.cpu.iew.iewUnblockCycles 6438859 # Number of cycles IEW is unblocking 487system.cpu.iew.iewDispatchedInsts 2101061688 # Number of instructions dispatched to IQ 488system.cpu.iew.iewDispSquashedInsts 392799 # Number of squashed instructions skipped by dispatch 489system.cpu.iew.iewDispLoadInsts 528344550 # Number of dispatched load instructions 490system.cpu.iew.iewDispStoreInsts 209838821 # Number of dispatched store instructions 491system.cpu.iew.iewDispNonSpecInsts 7385 # Number of dispatched non-speculative instructions 492system.cpu.iew.iewIQFullEvents 1906737 # Number of times the IQ has become full, causing a stall 493system.cpu.iew.iewLSQFullEvents 3653179 # Number of times the LSQ has become full, causing a stall 494system.cpu.iew.memOrderViolationEvents 386532 # Number of memory order violations 495system.cpu.iew.predictedTakenIncorrect 5738958 # Number of branches that were predicted taken incorrectly 496system.cpu.iew.predictedNotTakenIncorrect 4581595 # Number of branches that were predicted not taken incorrectly 497system.cpu.iew.branchMispredicts 10320553 # Number of branch mispredicts detected at execute 498system.cpu.iew.iewExecutedInsts 1805492449 # Number of executed instructions 499system.cpu.iew.iewExecLoadInsts 428838978 # Number of load instructions executed 500system.cpu.iew.iewExecSquashedInsts 21434108 # Number of squashed instructions skipped in execute | 484system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing 485system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking 486system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking 487system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ 488system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch 489system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions 490system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions 491system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions 492system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall 493system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall 494system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations 495system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly 496system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly 497system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute 498system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions 499system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed 500system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute |
| 501system.cpu.iew.exec_swp 0 # number of swp insts executed 502system.cpu.iew.exec_nop 0 # number of nop insts executed | 501system.cpu.iew.exec_swp 0 # number of swp insts executed 502system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 503system.cpu.iew.exec_refs 598981338 # number of memory reference insts executed 504system.cpu.iew.exec_branches 171787473 # Number of branches executed 505system.cpu.iew.exec_stores 170142360 # Number of stores executed 506system.cpu.iew.exec_rate 2.160793 # Inst execution rate 507system.cpu.iew.wb_sent 1802094257 # cumulative count of insts sent to commit 508system.cpu.iew.wb_count 1796805404 # cumulative count of insts written-back 509system.cpu.iew.wb_producers 1368063103 # num instructions producing a value 510system.cpu.iew.wb_consumers 2090238527 # num instructions consuming a value | 503system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed 504system.cpu.iew.exec_branches 171793179 # Number of branches executed 505system.cpu.iew.exec_stores 170131277 # Number of stores executed 506system.cpu.iew.exec_rate 2.159821 # Inst execution rate 507system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit 508system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back 509system.cpu.iew.wb_producers 1367992688 # num instructions producing a value 510system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value |
| 511system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 511system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 512system.cpu.iew.wb_rate 2.150397 # insts written-back per cycle 513system.cpu.iew.wb_fanout 0.654501 # average fanout of values written-back | 512system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle 513system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back |
| 514system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 514system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 515system.cpu.commit.commitSquashedInsts 572152437 # The number of squashed insts skipped by commit | 515system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit |
| 516system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 516system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 517system.cpu.commit.branchMispredicts 9826757 # The number of times a branch was mispredicted 518system.cpu.commit.committed_per_cycle::samples 757699482 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::mean 2.017936 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::stdev 2.547497 # Number of insts commited each cycle | 517system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted 518system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle |
| 521system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 521system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 522system.cpu.commit.committed_per_cycle::0 289066041 38.15% 38.15% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::1 175144894 23.12% 61.27% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::2 57411271 7.58% 68.84% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::3 86235215 11.38% 80.22% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::4 27150149 3.58% 83.81% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::5 27136057 3.58% 87.39% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::6 9784065 1.29% 88.68% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::7 8843971 1.17% 89.85% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::8 76927819 10.15% 100.00% # Number of insts commited each cycle | 522system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle |
| 531system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 531system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 534system.cpu.commit.committed_per_cycle::total 757699482 # Number of insts commited each cycle | 534system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle |
| 535system.cpu.commit.committedInsts 826877109 # Number of instructions committed 536system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 537system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 538system.cpu.commit.refs 533262343 # Number of memory references committed 539system.cpu.commit.loads 384102157 # Number of loads committed 540system.cpu.commit.membars 0 # Number of memory barriers committed 541system.cpu.commit.branches 149758583 # Number of branches committed 542system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 572system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 576system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction | 535system.cpu.commit.committedInsts 826877109 # Number of instructions committed 536system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 537system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 538system.cpu.commit.refs 533262343 # Number of memory references committed 539system.cpu.commit.loads 384102157 # Number of loads committed 540system.cpu.commit.membars 0 # Number of memory barriers committed 541system.cpu.commit.branches 149758583 # Number of branches committed 542system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 572system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 576system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction |
| 580system.cpu.commit.bw_lim_events 76927819 # number cycles where commit BW limit reached 581system.cpu.rob.rob_reads 2781912801 # The number of ROB reads 582system.cpu.rob.rob_writes 4280130406 # The number of ROB writes 583system.cpu.timesIdled 2299 # Number of times that the entire CPU went into an idle state and unscheduled itself 584system.cpu.idleCycles 206226 # Total number of cycles that the CPU has spent unscheduled due to idling | 580system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached 581system.cpu.rob.rob_reads 2782646702 # The number of ROB reads 582system.cpu.rob.rob_writes 4280772798 # The number of ROB writes 583system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself 584system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 585system.cpu.committedInsts 826877109 # Number of Instructions Simulated 586system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated | 585system.cpu.committedInsts 826877109 # Number of Instructions Simulated 586system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated |
| 587system.cpu.cpi 1.010512 # CPI: Cycles Per Instruction 588system.cpu.cpi_total 1.010512 # CPI: Total CPI of All Threads 589system.cpu.ipc 0.989597 # IPC: Instructions Per Cycle 590system.cpu.ipc_total 0.989597 # IPC: Total IPC of All Threads 591system.cpu.int_regfile_reads 2761971319 # number of integer regfile reads 592system.cpu.int_regfile_writes 1465030124 # number of integer regfile writes 593system.cpu.fp_regfile_reads 7481 # number of floating regfile reads 594system.cpu.fp_regfile_writes 493 # number of floating regfile writes 595system.cpu.cc_regfile_reads 600902917 # number of cc regfile reads 596system.cpu.cc_regfile_writes 409659635 # number of cc regfile writes 597system.cpu.misc_regfile_reads 990136590 # number of misc regfile reads | 587system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction 588system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads 589system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle 590system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads 591system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads 592system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes 593system.cpu.fp_regfile_reads 7563 # number of floating regfile reads 594system.cpu.fp_regfile_writes 476 # number of floating regfile writes 595system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads 596system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes 597system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads |
| 598system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 598system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 599system.cpu.dcache.tags.replacements 2534249 # number of replacements 600system.cpu.dcache.tags.tagsinuse 4087.994933 # Cycle average of tags in use 601system.cpu.dcache.tags.total_refs 387820460 # Total number of references to valid blocks. 602system.cpu.dcache.tags.sampled_refs 2538345 # Sample count of references to valid blocks. 603system.cpu.dcache.tags.avg_refs 152.784771 # Average number of references to valid blocks. | 599system.cpu.dcache.tags.replacements 2534281 # number of replacements 600system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use 601system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks. 602system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks. 603system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks. |
| 604system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. | 604system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. |
| 605system.cpu.dcache.tags.occ_blocks::cpu.data 4087.994933 # Average occupied blocks per requestor 606system.cpu.dcache.tags.occ_percent::cpu.data 0.998046 # Average percentage of cache occupancy 607system.cpu.dcache.tags.occ_percent::total 0.998046 # Average percentage of cache occupancy | 605system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor 606system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy 607system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy |
| 608system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 609system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id | 608system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 609system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id |
| 610system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id | 610system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id |
| 613system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 613system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 614system.cpu.dcache.tags.tag_accesses 784768509 # Number of tag accesses 615system.cpu.dcache.tags.data_accesses 784768509 # Number of data accesses 616system.cpu.dcache.ReadReq_hits::cpu.data 239165062 # number of ReadReq hits 617system.cpu.dcache.ReadReq_hits::total 239165062 # number of ReadReq hits 618system.cpu.dcache.WriteReq_hits::cpu.data 148173846 # number of WriteReq hits 619system.cpu.dcache.WriteReq_hits::total 148173846 # number of WriteReq hits 620system.cpu.dcache.demand_hits::cpu.data 387338908 # number of demand (read+write) hits 621system.cpu.dcache.demand_hits::total 387338908 # number of demand (read+write) hits 622system.cpu.dcache.overall_hits::cpu.data 387338908 # number of overall hits 623system.cpu.dcache.overall_hits::total 387338908 # number of overall hits 624system.cpu.dcache.ReadReq_misses::cpu.data 2789818 # number of ReadReq misses 625system.cpu.dcache.ReadReq_misses::total 2789818 # number of ReadReq misses 626system.cpu.dcache.WriteReq_misses::cpu.data 986356 # number of WriteReq misses 627system.cpu.dcache.WriteReq_misses::total 986356 # number of WriteReq misses 628system.cpu.dcache.demand_misses::cpu.data 3776174 # number of demand (read+write) misses 629system.cpu.dcache.demand_misses::total 3776174 # number of demand (read+write) misses 630system.cpu.dcache.overall_misses::cpu.data 3776174 # number of overall misses 631system.cpu.dcache.overall_misses::total 3776174 # number of overall misses 632system.cpu.dcache.ReadReq_miss_latency::cpu.data 60126724251 # number of ReadReq miss cycles 633system.cpu.dcache.ReadReq_miss_latency::total 60126724251 # number of ReadReq miss cycles 634system.cpu.dcache.WriteReq_miss_latency::cpu.data 31294703774 # number of WriteReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::total 31294703774 # number of WriteReq miss cycles 636system.cpu.dcache.demand_miss_latency::cpu.data 91421428025 # number of demand (read+write) miss cycles 637system.cpu.dcache.demand_miss_latency::total 91421428025 # number of demand (read+write) miss cycles 638system.cpu.dcache.overall_miss_latency::cpu.data 91421428025 # number of overall miss cycles 639system.cpu.dcache.overall_miss_latency::total 91421428025 # number of overall miss cycles 640system.cpu.dcache.ReadReq_accesses::cpu.data 241954880 # number of ReadReq accesses(hits+misses) 641system.cpu.dcache.ReadReq_accesses::total 241954880 # number of ReadReq accesses(hits+misses) | 614system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses 615system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses 616system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits 617system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits 618system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits 619system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits 620system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits 621system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits 622system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits 623system.cpu.dcache.overall_hits::total 387196758 # number of overall hits 624system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses 625system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses 626system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses 627system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses 628system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses 629system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses 630system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses 631system.cpu.dcache.overall_misses::total 3775006 # number of overall misses 632system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles 633system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles 634system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles 636system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles 637system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles 638system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles 639system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles 640system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses) 641system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses) |
| 642system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) | 642system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) |
| 644system.cpu.dcache.demand_accesses::cpu.data 391115082 # number of demand (read+write) accesses 645system.cpu.dcache.demand_accesses::total 391115082 # number of demand (read+write) accesses 646system.cpu.dcache.overall_accesses::cpu.data 391115082 # number of overall (read+write) accesses 647system.cpu.dcache.overall_accesses::total 391115082 # number of overall (read+write) accesses 648system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011530 # miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_miss_rate::total 0.011530 # miss rate for ReadReq accesses 650system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses | 644system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses 645system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses 646system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses 647system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses 648system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses 650system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses |
| 652system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses 653system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses 654system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses 655system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses | 652system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses 653system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses 654system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses 655system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses |
| 656system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21552.203137 # average ReadReq miss latency 657system.cpu.dcache.ReadReq_avg_miss_latency::total 21552.203137 # average ReadReq miss latency 658system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31727.595081 # average WriteReq miss latency 659system.cpu.dcache.WriteReq_avg_miss_latency::total 31727.595081 # average WriteReq miss latency 660system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency 661system.cpu.dcache.demand_avg_miss_latency::total 24210.067657 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::total 24210.067657 # average overall miss latency 664system.cpu.dcache.blocked_cycles::no_mshrs 10621 # number of cycles access was blocked 665system.cpu.dcache.blocked_cycles::no_targets 71 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_mshrs 1078 # number of cycles access was blocked | 656system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency 657system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency 658system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency 659system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency 660system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency 661system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency 664system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked 665system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked |
| 667system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked | 667system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked |
| 668system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.852505 # average number of cycles each access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_targets 14.200000 # average number of cycles each access was blocked | 668system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked |
| 670system.cpu.dcache.fast_writes 0 # number of fast writes performed 671system.cpu.dcache.cache_copies 0 # number of cache copies performed | 670system.cpu.dcache.fast_writes 0 # number of fast writes performed 671system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 672system.cpu.dcache.writebacks::writebacks 2332976 # number of writebacks 673system.cpu.dcache.writebacks::total 2332976 # number of writebacks 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1022764 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 1022764 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18373 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 18373 # number of WriteReq MSHR hits 678system.cpu.dcache.demand_mshr_hits::cpu.data 1041137 # number of demand (read+write) MSHR hits 679system.cpu.dcache.demand_mshr_hits::total 1041137 # number of demand (read+write) MSHR hits 680system.cpu.dcache.overall_mshr_hits::cpu.data 1041137 # number of overall MSHR hits 681system.cpu.dcache.overall_mshr_hits::total 1041137 # number of overall MSHR hits | 672system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks 673system.cpu.dcache.writebacks::total 2332980 # number of writebacks 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits 678system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits 679system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits 680system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits 681system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits |
| 682system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses 683system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses | 682system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses 683system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses |
| 684system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967983 # number of WriteReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::total 967983 # number of WriteReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.data 2735037 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 2735037 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 2735037 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 2735037 # number of overall MSHR misses 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779636252 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779636252 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29507402723 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 29507402723 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62287038975 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::total 62287038975 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62287038975 # number of overall MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::total 62287038975 # number of overall MSHR miss cycles 698system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007303 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007303 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.006993 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.006993 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.443989 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.443989 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30483.389401 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30483.389401 # average WriteReq mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency | 684system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles 698system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency |
| 714system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 714system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 715system.cpu.icache.tags.replacements 7023 # number of replacements 716system.cpu.icache.tags.tagsinuse 1053.963479 # Cycle average of tags in use 717system.cpu.icache.tags.total_refs 179273130 # Total number of references to valid blocks. 718system.cpu.icache.tags.sampled_refs 8620 # Sample count of references to valid blocks. 719system.cpu.icache.tags.avg_refs 20797.346868 # Average number of references to valid blocks. | 715system.cpu.icache.tags.replacements 7107 # number of replacements 716system.cpu.icache.tags.tagsinuse 1054.726418 # Cycle average of tags in use 717system.cpu.icache.tags.total_refs 179314504 # Total number of references to valid blocks. 718system.cpu.icache.tags.sampled_refs 8709 # Sample count of references to valid blocks. 719system.cpu.icache.tags.avg_refs 20589.562981 # Average number of references to valid blocks. |
| 720system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 720system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 721system.cpu.icache.tags.occ_blocks::cpu.inst 1053.963479 # Average occupied blocks per requestor 722system.cpu.icache.tags.occ_percent::cpu.inst 0.514631 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_percent::total 0.514631 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_task_id_blocks::1024 1597 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::4 1155 # Occupied blocks per task id 730system.cpu.icache.tags.occ_task_id_percent::1024 0.779785 # Percentage of cache occupancy per task id 731system.cpu.icache.tags.tag_accesses 359174294 # Number of tag accesses 732system.cpu.icache.tags.data_accesses 359174294 # Number of data accesses 733system.cpu.icache.ReadReq_hits::cpu.inst 179276307 # number of ReadReq hits 734system.cpu.icache.ReadReq_hits::total 179276307 # number of ReadReq hits 735system.cpu.icache.demand_hits::cpu.inst 179276307 # number of demand (read+write) hits 736system.cpu.icache.demand_hits::total 179276307 # number of demand (read+write) hits 737system.cpu.icache.overall_hits::cpu.inst 179276307 # number of overall hits 738system.cpu.icache.overall_hits::total 179276307 # number of overall hits 739system.cpu.icache.ReadReq_misses::cpu.inst 208110 # number of ReadReq misses 740system.cpu.icache.ReadReq_misses::total 208110 # number of ReadReq misses 741system.cpu.icache.demand_misses::cpu.inst 208110 # number of demand (read+write) misses 742system.cpu.icache.demand_misses::total 208110 # number of demand (read+write) misses 743system.cpu.icache.overall_misses::cpu.inst 208110 # number of overall misses 744system.cpu.icache.overall_misses::total 208110 # number of overall misses 745system.cpu.icache.ReadReq_miss_latency::cpu.inst 1327923993 # number of ReadReq miss cycles 746system.cpu.icache.ReadReq_miss_latency::total 1327923993 # number of ReadReq miss cycles 747system.cpu.icache.demand_miss_latency::cpu.inst 1327923993 # number of demand (read+write) miss cycles 748system.cpu.icache.demand_miss_latency::total 1327923993 # number of demand (read+write) miss cycles 749system.cpu.icache.overall_miss_latency::cpu.inst 1327923993 # number of overall miss cycles 750system.cpu.icache.overall_miss_latency::total 1327923993 # number of overall miss cycles 751system.cpu.icache.ReadReq_accesses::cpu.inst 179484417 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.ReadReq_accesses::total 179484417 # number of ReadReq accesses(hits+misses) 753system.cpu.icache.demand_accesses::cpu.inst 179484417 # number of demand (read+write) accesses 754system.cpu.icache.demand_accesses::total 179484417 # number of demand (read+write) accesses 755system.cpu.icache.overall_accesses::cpu.inst 179484417 # number of overall (read+write) accesses 756system.cpu.icache.overall_accesses::total 179484417 # number of overall (read+write) accesses 757system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001159 # miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses 759system.cpu.icache.demand_miss_rate::cpu.inst 0.001159 # miss rate for demand accesses 760system.cpu.icache.demand_miss_rate::total 0.001159 # miss rate for demand accesses 761system.cpu.icache.overall_miss_rate::cpu.inst 0.001159 # miss rate for overall accesses 762system.cpu.icache.overall_miss_rate::total 0.001159 # miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.875465 # average ReadReq miss latency 764system.cpu.icache.ReadReq_avg_miss_latency::total 6380.875465 # average ReadReq miss latency 765system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency 766system.cpu.icache.demand_avg_miss_latency::total 6380.875465 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency 768system.cpu.icache.overall_avg_miss_latency::total 6380.875465 # average overall miss latency 769system.cpu.icache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked | 721system.cpu.icache.tags.occ_blocks::cpu.inst 1054.726418 # Average occupied blocks per requestor 722system.cpu.icache.tags.occ_percent::cpu.inst 0.515003 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_percent::total 0.515003 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_task_id_blocks::1024 1602 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::3 330 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::4 1149 # Occupied blocks per task id 730system.cpu.icache.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id 731system.cpu.icache.tags.tag_accesses 359258778 # Number of tag accesses 732system.cpu.icache.tags.data_accesses 359258778 # Number of data accesses 733system.cpu.icache.ReadReq_hits::cpu.inst 179317997 # number of ReadReq hits 734system.cpu.icache.ReadReq_hits::total 179317997 # number of ReadReq hits 735system.cpu.icache.demand_hits::cpu.inst 179317997 # number of demand (read+write) hits 736system.cpu.icache.demand_hits::total 179317997 # number of demand (read+write) hits 737system.cpu.icache.overall_hits::cpu.inst 179317997 # number of overall hits 738system.cpu.icache.overall_hits::total 179317997 # number of overall hits 739system.cpu.icache.ReadReq_misses::cpu.inst 208472 # number of ReadReq misses 740system.cpu.icache.ReadReq_misses::total 208472 # number of ReadReq misses 741system.cpu.icache.demand_misses::cpu.inst 208472 # number of demand (read+write) misses 742system.cpu.icache.demand_misses::total 208472 # number of demand (read+write) misses 743system.cpu.icache.overall_misses::cpu.inst 208472 # number of overall misses 744system.cpu.icache.overall_misses::total 208472 # number of overall misses 745system.cpu.icache.ReadReq_miss_latency::cpu.inst 1336227738 # number of ReadReq miss cycles 746system.cpu.icache.ReadReq_miss_latency::total 1336227738 # number of ReadReq miss cycles 747system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # number of demand (read+write) miss cycles 748system.cpu.icache.demand_miss_latency::total 1336227738 # number of demand (read+write) miss cycles 749system.cpu.icache.overall_miss_latency::cpu.inst 1336227738 # number of overall miss cycles 750system.cpu.icache.overall_miss_latency::total 1336227738 # number of overall miss cycles 751system.cpu.icache.ReadReq_accesses::cpu.inst 179526469 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.ReadReq_accesses::total 179526469 # number of ReadReq accesses(hits+misses) 753system.cpu.icache.demand_accesses::cpu.inst 179526469 # number of demand (read+write) accesses 754system.cpu.icache.demand_accesses::total 179526469 # number of demand (read+write) accesses 755system.cpu.icache.overall_accesses::cpu.inst 179526469 # number of overall (read+write) accesses 756system.cpu.icache.overall_accesses::total 179526469 # number of overall (read+write) accesses 757system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001161 # miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_miss_rate::total 0.001161 # miss rate for ReadReq accesses 759system.cpu.icache.demand_miss_rate::cpu.inst 0.001161 # miss rate for demand accesses 760system.cpu.icache.demand_miss_rate::total 0.001161 # miss rate for demand accesses 761system.cpu.icache.overall_miss_rate::cpu.inst 0.001161 # miss rate for overall accesses 762system.cpu.icache.overall_miss_rate::total 0.001161 # miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6409.626895 # average ReadReq miss latency 764system.cpu.icache.ReadReq_avg_miss_latency::total 6409.626895 # average ReadReq miss latency 765system.cpu.icache.demand_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency 766system.cpu.icache.demand_avg_miss_latency::total 6409.626895 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency 768system.cpu.icache.overall_avg_miss_latency::total 6409.626895 # average overall miss latency 769system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked |
| 770system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 770system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 771system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked | 771system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked |
| 772system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 772system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 773system.cpu.icache.avg_blocked_cycles::no_mshrs 57.916667 # average number of cycles each access was blocked | 773system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked |
| 774system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.icache.fast_writes 0 # number of fast writes performed 776system.cpu.icache.cache_copies 0 # number of cache copies performed | 774system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.icache.fast_writes 0 # number of fast writes performed 776system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 777system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2649 # number of ReadReq MSHR hits 778system.cpu.icache.ReadReq_mshr_hits::total 2649 # number of ReadReq MSHR hits 779system.cpu.icache.demand_mshr_hits::cpu.inst 2649 # number of demand (read+write) MSHR hits 780system.cpu.icache.demand_mshr_hits::total 2649 # number of demand (read+write) MSHR hits 781system.cpu.icache.overall_mshr_hits::cpu.inst 2649 # number of overall MSHR hits 782system.cpu.icache.overall_mshr_hits::total 2649 # number of overall MSHR hits 783system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205461 # number of ReadReq MSHR misses 784system.cpu.icache.ReadReq_mshr_misses::total 205461 # number of ReadReq MSHR misses 785system.cpu.icache.demand_mshr_misses::cpu.inst 205461 # number of demand (read+write) MSHR misses 786system.cpu.icache.demand_mshr_misses::total 205461 # number of demand (read+write) MSHR misses 787system.cpu.icache.overall_mshr_misses::cpu.inst 205461 # number of overall MSHR misses 788system.cpu.icache.overall_mshr_misses::total 205461 # number of overall MSHR misses 789system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 892683754 # number of ReadReq MSHR miss cycles 790system.cpu.icache.ReadReq_mshr_miss_latency::total 892683754 # number of ReadReq MSHR miss cycles 791system.cpu.icache.demand_mshr_miss_latency::cpu.inst 892683754 # number of demand (read+write) MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::total 892683754 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.overall_mshr_miss_latency::cpu.inst 892683754 # number of overall MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::total 892683754 # number of overall MSHR miss cycles 795system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for ReadReq accesses 796system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001145 # mshr miss rate for ReadReq accesses 797system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for demand accesses 798system.cpu.icache.demand_mshr_miss_rate::total 0.001145 # mshr miss rate for demand accesses 799system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for overall accesses 800system.cpu.icache.overall_mshr_miss_rate::total 0.001145 # mshr miss rate for overall accesses 801system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4344.784431 # average ReadReq mshr miss latency 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4344.784431 # average ReadReq mshr miss latency 803system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency 805system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency | 777system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2630 # number of ReadReq MSHR hits 778system.cpu.icache.ReadReq_mshr_hits::total 2630 # number of ReadReq MSHR hits 779system.cpu.icache.demand_mshr_hits::cpu.inst 2630 # number of demand (read+write) MSHR hits 780system.cpu.icache.demand_mshr_hits::total 2630 # number of demand (read+write) MSHR hits 781system.cpu.icache.overall_mshr_hits::cpu.inst 2630 # number of overall MSHR hits 782system.cpu.icache.overall_mshr_hits::total 2630 # number of overall MSHR hits 783system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205842 # number of ReadReq MSHR misses 784system.cpu.icache.ReadReq_mshr_misses::total 205842 # number of ReadReq MSHR misses 785system.cpu.icache.demand_mshr_misses::cpu.inst 205842 # number of demand (read+write) MSHR misses 786system.cpu.icache.demand_mshr_misses::total 205842 # number of demand (read+write) MSHR misses 787system.cpu.icache.overall_mshr_misses::cpu.inst 205842 # number of overall MSHR misses 788system.cpu.icache.overall_mshr_misses::total 205842 # number of overall MSHR misses 789system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 900667759 # number of ReadReq MSHR miss cycles 790system.cpu.icache.ReadReq_mshr_miss_latency::total 900667759 # number of ReadReq MSHR miss cycles 791system.cpu.icache.demand_mshr_miss_latency::cpu.inst 900667759 # number of demand (read+write) MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::total 900667759 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.overall_mshr_miss_latency::cpu.inst 900667759 # number of overall MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::total 900667759 # number of overall MSHR miss cycles 795system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for ReadReq accesses 796system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001147 # mshr miss rate for ReadReq accesses 797system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for demand accesses 798system.cpu.icache.demand_mshr_miss_rate::total 0.001147 # mshr miss rate for demand accesses 799system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for overall accesses 800system.cpu.icache.overall_mshr_miss_rate::total 0.001147 # mshr miss rate for overall accesses 801system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4375.529576 # average ReadReq mshr miss latency 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4375.529576 # average ReadReq mshr miss latency 803system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency 805system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency |
| 807system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 807system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 808system.cpu.l2cache.tags.replacements 354223 # number of replacements 809system.cpu.l2cache.tags.tagsinuse 29619.061304 # Cycle average of tags in use 810system.cpu.l2cache.tags.total_refs 3704244 # Total number of references to valid blocks. 811system.cpu.l2cache.tags.sampled_refs 386583 # Sample count of references to valid blocks. 812system.cpu.l2cache.tags.avg_refs 9.582015 # Average number of references to valid blocks. | 808system.cpu.l2cache.tags.replacements 354249 # number of replacements 809system.cpu.l2cache.tags.tagsinuse 29619.496841 # Cycle average of tags in use 810system.cpu.l2cache.tags.total_refs 3704141 # Total number of references to valid blocks. 811system.cpu.l2cache.tags.sampled_refs 386604 # Sample count of references to valid blocks. 812system.cpu.l2cache.tags.avg_refs 9.581228 # Average number of references to valid blocks. |
| 813system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit. | 813system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit. |
| 814system.cpu.l2cache.tags.occ_blocks::writebacks 21085.370146 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.812049 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.data 8281.879109 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_percent::writebacks 0.643474 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007685 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.data 0.252743 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::total 0.903902 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id | 814system.cpu.l2cache.tags.occ_blocks::writebacks 21082.499774 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.inst 254.372713 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.data 8282.624354 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_percent::writebacks 0.643387 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007763 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.data 0.252766 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::total 0.903915 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id |
| 823system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id | 823system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id |
| 824system.cpu.l2cache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13363 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18671 # Occupied blocks per task id 827system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id 828system.cpu.l2cache.tags.tag_accesses 41773644 # Number of tag accesses 829system.cpu.l2cache.tags.data_accesses 41773644 # Number of data accesses 830system.cpu.l2cache.ReadReq_hits::cpu.inst 5119 # number of ReadReq hits 831system.cpu.l2cache.ReadReq_hits::cpu.data 1590451 # number of ReadReq hits 832system.cpu.l2cache.ReadReq_hits::total 1595570 # number of ReadReq hits 833system.cpu.l2cache.Writeback_hits::writebacks 2332976 # number of Writeback hits 834system.cpu.l2cache.Writeback_hits::total 2332976 # number of Writeback hits 835system.cpu.l2cache.UpgradeReq_hits::cpu.data 1900 # number of UpgradeReq hits 836system.cpu.l2cache.UpgradeReq_hits::total 1900 # number of UpgradeReq hits 837system.cpu.l2cache.ReadExReq_hits::cpu.data 564474 # number of ReadExReq hits 838system.cpu.l2cache.ReadExReq_hits::total 564474 # number of ReadExReq hits 839system.cpu.l2cache.demand_hits::cpu.inst 5119 # number of demand (read+write) hits 840system.cpu.l2cache.demand_hits::cpu.data 2154925 # number of demand (read+write) hits 841system.cpu.l2cache.demand_hits::total 2160044 # number of demand (read+write) hits 842system.cpu.l2cache.overall_hits::cpu.inst 5119 # number of overall hits 843system.cpu.l2cache.overall_hits::cpu.data 2154925 # number of overall hits 844system.cpu.l2cache.overall_hits::total 2160044 # number of overall hits 845system.cpu.l2cache.ReadReq_misses::cpu.inst 3526 # number of ReadReq misses 846system.cpu.l2cache.ReadReq_misses::cpu.data 176410 # number of ReadReq misses 847system.cpu.l2cache.ReadReq_misses::total 179936 # number of ReadReq misses 848system.cpu.l2cache.UpgradeReq_misses::cpu.data 194792 # number of UpgradeReq misses 849system.cpu.l2cache.UpgradeReq_misses::total 194792 # number of UpgradeReq misses 850system.cpu.l2cache.ReadExReq_misses::cpu.data 207010 # number of ReadExReq misses 851system.cpu.l2cache.ReadExReq_misses::total 207010 # number of ReadExReq misses 852system.cpu.l2cache.demand_misses::cpu.inst 3526 # number of demand (read+write) misses 853system.cpu.l2cache.demand_misses::cpu.data 383420 # number of demand (read+write) misses 854system.cpu.l2cache.demand_misses::total 386946 # number of demand (read+write) misses 855system.cpu.l2cache.overall_misses::cpu.inst 3526 # number of overall misses 856system.cpu.l2cache.overall_misses::cpu.data 383420 # number of overall misses 857system.cpu.l2cache.overall_misses::total 386946 # number of overall misses 858system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 288437750 # number of ReadReq miss cycles 859system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275708250 # number of ReadReq miss cycles 860system.cpu.l2cache.ReadReq_miss_latency::total 14564146000 # number of ReadReq miss cycles 861system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12898587 # number of UpgradeReq miss cycles 862system.cpu.l2cache.UpgradeReq_miss_latency::total 12898587 # number of UpgradeReq miss cycles 863system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16427155710 # number of ReadExReq miss cycles 864system.cpu.l2cache.ReadExReq_miss_latency::total 16427155710 # number of ReadExReq miss cycles 865system.cpu.l2cache.demand_miss_latency::cpu.inst 288437750 # number of demand (read+write) miss cycles 866system.cpu.l2cache.demand_miss_latency::cpu.data 30702863960 # number of demand (read+write) miss cycles 867system.cpu.l2cache.demand_miss_latency::total 30991301710 # number of demand (read+write) miss cycles 868system.cpu.l2cache.overall_miss_latency::cpu.inst 288437750 # number of overall miss cycles 869system.cpu.l2cache.overall_miss_latency::cpu.data 30702863960 # number of overall miss cycles 870system.cpu.l2cache.overall_miss_latency::total 30991301710 # number of overall miss cycles 871system.cpu.l2cache.ReadReq_accesses::cpu.inst 8645 # number of ReadReq accesses(hits+misses) 872system.cpu.l2cache.ReadReq_accesses::cpu.data 1766861 # number of ReadReq accesses(hits+misses) 873system.cpu.l2cache.ReadReq_accesses::total 1775506 # number of ReadReq accesses(hits+misses) 874system.cpu.l2cache.Writeback_accesses::writebacks 2332976 # number of Writeback accesses(hits+misses) 875system.cpu.l2cache.Writeback_accesses::total 2332976 # number of Writeback accesses(hits+misses) 876system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196692 # number of UpgradeReq accesses(hits+misses) 877system.cpu.l2cache.UpgradeReq_accesses::total 196692 # number of UpgradeReq accesses(hits+misses) 878system.cpu.l2cache.ReadExReq_accesses::cpu.data 771484 # number of ReadExReq accesses(hits+misses) 879system.cpu.l2cache.ReadExReq_accesses::total 771484 # number of ReadExReq accesses(hits+misses) 880system.cpu.l2cache.demand_accesses::cpu.inst 8645 # number of demand (read+write) accesses 881system.cpu.l2cache.demand_accesses::cpu.data 2538345 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::total 2546990 # number of demand (read+write) accesses 883system.cpu.l2cache.overall_accesses::cpu.inst 8645 # number of overall (read+write) accesses 884system.cpu.l2cache.overall_accesses::cpu.data 2538345 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::total 2546990 # number of overall (read+write) accesses 886system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.407866 # miss rate for ReadReq accesses 887system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099844 # miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_miss_rate::total 0.101344 # miss rate for ReadReq accesses 889system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990340 # miss rate for UpgradeReq accesses 890system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990340 # miss rate for UpgradeReq accesses 891system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268327 # miss rate for ReadExReq accesses 892system.cpu.l2cache.ReadExReq_miss_rate::total 0.268327 # miss rate for ReadExReq accesses 893system.cpu.l2cache.demand_miss_rate::cpu.inst 0.407866 # miss rate for demand accesses 894system.cpu.l2cache.demand_miss_rate::cpu.data 0.151051 # miss rate for demand accesses 895system.cpu.l2cache.demand_miss_rate::total 0.151923 # miss rate for demand accesses 896system.cpu.l2cache.overall_miss_rate::cpu.inst 0.407866 # miss rate for overall accesses 897system.cpu.l2cache.overall_miss_rate::cpu.data 0.151051 # miss rate for overall accesses 898system.cpu.l2cache.overall_miss_rate::total 0.151923 # miss rate for overall accesses 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81803.105502 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80923.463806 # average ReadReq miss latency 901system.cpu.l2cache.ReadReq_avg_miss_latency::total 80940.701138 # average ReadReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 66.217232 # average UpgradeReq miss latency 903system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 66.217232 # average UpgradeReq miss latency 904system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79354.406599 # average ReadExReq miss latency 905system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79354.406599 # average ReadExReq miss latency 906system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency 907system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency 908system.cpu.l2cache.demand_avg_miss_latency::total 80092.058608 # average overall miss latency 909system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency 910system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency 911system.cpu.l2cache.overall_avg_miss_latency::total 80092.058608 # average overall miss latency | 824system.cpu.l2cache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13370 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18660 # Occupied blocks per task id 827system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id 828system.cpu.l2cache.tags.tag_accesses 41777056 # Number of tag accesses 829system.cpu.l2cache.tags.data_accesses 41777056 # Number of data accesses 830system.cpu.l2cache.ReadReq_hits::cpu.inst 5192 # number of ReadReq hits 831system.cpu.l2cache.ReadReq_hits::cpu.data 1590453 # number of ReadReq hits 832system.cpu.l2cache.ReadReq_hits::total 1595645 # number of ReadReq hits 833system.cpu.l2cache.Writeback_hits::writebacks 2332980 # number of Writeback hits 834system.cpu.l2cache.Writeback_hits::total 2332980 # number of Writeback hits 835system.cpu.l2cache.UpgradeReq_hits::cpu.data 1881 # number of UpgradeReq hits 836system.cpu.l2cache.UpgradeReq_hits::total 1881 # number of UpgradeReq hits 837system.cpu.l2cache.ReadExReq_hits::cpu.data 564507 # number of ReadExReq hits 838system.cpu.l2cache.ReadExReq_hits::total 564507 # number of ReadExReq hits 839system.cpu.l2cache.demand_hits::cpu.inst 5192 # number of demand (read+write) hits 840system.cpu.l2cache.demand_hits::cpu.data 2154960 # number of demand (read+write) hits 841system.cpu.l2cache.demand_hits::total 2160152 # number of demand (read+write) hits 842system.cpu.l2cache.overall_hits::cpu.inst 5192 # number of overall hits 843system.cpu.l2cache.overall_hits::cpu.data 2154960 # number of overall hits 844system.cpu.l2cache.overall_hits::total 2160152 # number of overall hits 845system.cpu.l2cache.ReadReq_misses::cpu.inst 3552 # number of ReadReq misses 846system.cpu.l2cache.ReadReq_misses::cpu.data 176400 # number of ReadReq misses 847system.cpu.l2cache.ReadReq_misses::total 179952 # number of ReadReq misses 848system.cpu.l2cache.UpgradeReq_misses::cpu.data 195096 # number of UpgradeReq misses 849system.cpu.l2cache.UpgradeReq_misses::total 195096 # number of UpgradeReq misses 850system.cpu.l2cache.ReadExReq_misses::cpu.data 207017 # number of ReadExReq misses 851system.cpu.l2cache.ReadExReq_misses::total 207017 # number of ReadExReq misses 852system.cpu.l2cache.demand_misses::cpu.inst 3552 # number of demand (read+write) misses 853system.cpu.l2cache.demand_misses::cpu.data 383417 # number of demand (read+write) misses 854system.cpu.l2cache.demand_misses::total 386969 # number of demand (read+write) misses 855system.cpu.l2cache.overall_misses::cpu.inst 3552 # number of overall misses 856system.cpu.l2cache.overall_misses::cpu.data 383417 # number of overall misses 857system.cpu.l2cache.overall_misses::total 386969 # number of overall misses 858system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 294540500 # number of ReadReq miss cycles 859system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275679000 # number of ReadReq miss cycles 860system.cpu.l2cache.ReadReq_miss_latency::total 14570219500 # number of ReadReq miss cycles 861system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13220077 # number of UpgradeReq miss cycles 862system.cpu.l2cache.UpgradeReq_miss_latency::total 13220077 # number of UpgradeReq miss cycles 863system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16430030463 # number of ReadExReq miss cycles 864system.cpu.l2cache.ReadExReq_miss_latency::total 16430030463 # number of ReadExReq miss cycles 865system.cpu.l2cache.demand_miss_latency::cpu.inst 294540500 # number of demand (read+write) miss cycles 866system.cpu.l2cache.demand_miss_latency::cpu.data 30705709463 # number of demand (read+write) miss cycles 867system.cpu.l2cache.demand_miss_latency::total 31000249963 # number of demand (read+write) miss cycles 868system.cpu.l2cache.overall_miss_latency::cpu.inst 294540500 # number of overall miss cycles 869system.cpu.l2cache.overall_miss_latency::cpu.data 30705709463 # number of overall miss cycles 870system.cpu.l2cache.overall_miss_latency::total 31000249963 # number of overall miss cycles 871system.cpu.l2cache.ReadReq_accesses::cpu.inst 8744 # number of ReadReq accesses(hits+misses) 872system.cpu.l2cache.ReadReq_accesses::cpu.data 1766853 # number of ReadReq accesses(hits+misses) 873system.cpu.l2cache.ReadReq_accesses::total 1775597 # number of ReadReq accesses(hits+misses) 874system.cpu.l2cache.Writeback_accesses::writebacks 2332980 # number of Writeback accesses(hits+misses) 875system.cpu.l2cache.Writeback_accesses::total 2332980 # number of Writeback accesses(hits+misses) 876system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196977 # number of UpgradeReq accesses(hits+misses) 877system.cpu.l2cache.UpgradeReq_accesses::total 196977 # number of UpgradeReq accesses(hits+misses) 878system.cpu.l2cache.ReadExReq_accesses::cpu.data 771524 # number of ReadExReq accesses(hits+misses) 879system.cpu.l2cache.ReadExReq_accesses::total 771524 # number of ReadExReq accesses(hits+misses) 880system.cpu.l2cache.demand_accesses::cpu.inst 8744 # number of demand (read+write) accesses 881system.cpu.l2cache.demand_accesses::cpu.data 2538377 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::total 2547121 # number of demand (read+write) accesses 883system.cpu.l2cache.overall_accesses::cpu.inst 8744 # number of overall (read+write) accesses 884system.cpu.l2cache.overall_accesses::cpu.data 2538377 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::total 2547121 # number of overall (read+write) accesses 886system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.406221 # miss rate for ReadReq accesses 887system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099839 # miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_miss_rate::total 0.101347 # miss rate for ReadReq accesses 889system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990451 # miss rate for UpgradeReq accesses 890system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990451 # miss rate for UpgradeReq accesses 891system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268322 # miss rate for ReadExReq accesses 892system.cpu.l2cache.ReadExReq_miss_rate::total 0.268322 # miss rate for ReadExReq accesses 893system.cpu.l2cache.demand_miss_rate::cpu.inst 0.406221 # miss rate for demand accesses 894system.cpu.l2cache.demand_miss_rate::cpu.data 0.151048 # miss rate for demand accesses 895system.cpu.l2cache.demand_miss_rate::total 0.151924 # miss rate for demand accesses 896system.cpu.l2cache.overall_miss_rate::cpu.inst 0.406221 # miss rate for overall accesses 897system.cpu.l2cache.overall_miss_rate::cpu.data 0.151048 # miss rate for overall accesses 898system.cpu.l2cache.overall_miss_rate::total 0.151924 # miss rate for overall accesses 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82922.438063 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80927.885488 # average ReadReq miss latency 901system.cpu.l2cache.ReadReq_avg_miss_latency::total 80967.255157 # average ReadReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 67.761907 # average UpgradeReq miss latency 903system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 67.761907 # average UpgradeReq miss latency 904system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79365.609892 # average ReadExReq miss latency 905system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79365.609892 # average ReadExReq miss latency 906system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency 907system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency 908system.cpu.l2cache.demand_avg_miss_latency::total 80110.422186 # average overall miss latency 909system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency 910system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency 911system.cpu.l2cache.overall_avg_miss_latency::total 80110.422186 # average overall miss latency |
| 912system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 913system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 914system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 915system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 916system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 917system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 918system.cpu.l2cache.fast_writes 0 # number of fast writes performed 919system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 912system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 913system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 914system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 915system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 916system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 917system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 918system.cpu.l2cache.fast_writes 0 # number of fast writes performed 919system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 920system.cpu.l2cache.writebacks::writebacks 294034 # number of writebacks 921system.cpu.l2cache.writebacks::total 294034 # number of writebacks | 920system.cpu.l2cache.writebacks::writebacks 294035 # number of writebacks 921system.cpu.l2cache.writebacks::total 294035 # number of writebacks |
| 922system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 923system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 924system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 925system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 926system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 927system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 922system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 923system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 924system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 925system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 926system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 927system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 928system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3525 # number of ReadReq MSHR misses 929system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176410 # number of ReadReq MSHR misses 930system.cpu.l2cache.ReadReq_mshr_misses::total 179935 # number of ReadReq MSHR misses 931system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 194792 # number of UpgradeReq MSHR misses 932system.cpu.l2cache.UpgradeReq_mshr_misses::total 194792 # number of UpgradeReq MSHR misses 933system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207010 # number of ReadExReq MSHR misses 934system.cpu.l2cache.ReadExReq_mshr_misses::total 207010 # number of ReadExReq MSHR misses 935system.cpu.l2cache.demand_mshr_misses::cpu.inst 3525 # number of demand (read+write) MSHR misses 936system.cpu.l2cache.demand_mshr_misses::cpu.data 383420 # number of demand (read+write) MSHR misses 937system.cpu.l2cache.demand_mshr_misses::total 386945 # number of demand (read+write) MSHR misses 938system.cpu.l2cache.overall_mshr_misses::cpu.inst 3525 # number of overall MSHR misses 939system.cpu.l2cache.overall_mshr_misses::cpu.data 383420 # number of overall MSHR misses 940system.cpu.l2cache.overall_mshr_misses::total 386945 # number of overall MSHR misses 941system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 244319250 # number of ReadReq MSHR miss cycles 942system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068297250 # number of ReadReq MSHR miss cycles 943system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12312616500 # number of ReadReq MSHR miss cycles 944system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3517284221 # number of UpgradeReq MSHR miss cycles 945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3517284221 # number of UpgradeReq MSHR miss cycles 946system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13838517790 # number of ReadExReq MSHR miss cycles 947system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13838517790 # number of ReadExReq MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244319250 # number of demand (read+write) MSHR miss cycles 949system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25906815040 # number of demand (read+write) MSHR miss cycles 950system.cpu.l2cache.demand_mshr_miss_latency::total 26151134290 # number of demand (read+write) MSHR miss cycles 951system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244319250 # number of overall MSHR miss cycles 952system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25906815040 # number of overall MSHR miss cycles 953system.cpu.l2cache.overall_mshr_miss_latency::total 26151134290 # number of overall MSHR miss cycles 954system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for ReadReq accesses 955system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099844 # mshr miss rate for ReadReq accesses 956system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101343 # mshr miss rate for ReadReq accesses 957system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990340 # mshr miss rate for UpgradeReq accesses 958system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990340 # mshr miss rate for UpgradeReq accesses 959system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268327 # mshr miss rate for ReadExReq accesses 960system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268327 # mshr miss rate for ReadExReq accesses 961system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for demand accesses 962system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for demand accesses 963system.cpu.l2cache.demand_mshr_miss_rate::total 0.151922 # mshr miss rate for demand accesses 964system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for overall accesses 965system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for overall accesses 966system.cpu.l2cache.overall_mshr_miss_rate::total 0.151922 # mshr miss rate for overall accesses 967system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69310.425532 # average ReadReq mshr miss latency 968system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68410.505357 # average ReadReq mshr miss latency 969system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68428.135160 # average ReadReq mshr miss latency 970system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18056.615369 # average UpgradeReq mshr miss latency 971system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18056.615369 # average UpgradeReq mshr miss latency 972system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66849.513502 # average ReadExReq mshr miss latency 973system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66849.513502 # average ReadExReq mshr miss latency 974system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency 975system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency 976system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency 977system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency 978system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency 979system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency | 928system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3551 # number of ReadReq MSHR misses 929system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176400 # number of ReadReq MSHR misses 930system.cpu.l2cache.ReadReq_mshr_misses::total 179951 # number of ReadReq MSHR misses 931system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195096 # number of UpgradeReq MSHR misses 932system.cpu.l2cache.UpgradeReq_mshr_misses::total 195096 # number of UpgradeReq MSHR misses 933system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207017 # number of ReadExReq MSHR misses 934system.cpu.l2cache.ReadExReq_mshr_misses::total 207017 # number of ReadExReq MSHR misses 935system.cpu.l2cache.demand_mshr_misses::cpu.inst 3551 # number of demand (read+write) MSHR misses 936system.cpu.l2cache.demand_mshr_misses::cpu.data 383417 # number of demand (read+write) MSHR misses 937system.cpu.l2cache.demand_mshr_misses::total 386968 # number of demand (read+write) MSHR misses 938system.cpu.l2cache.overall_mshr_misses::cpu.inst 3551 # number of overall MSHR misses 939system.cpu.l2cache.overall_mshr_misses::cpu.data 383417 # number of overall MSHR misses 940system.cpu.l2cache.overall_mshr_misses::total 386968 # number of overall MSHR misses 941system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250130000 # number of ReadReq MSHR miss cycles 942system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068381000 # number of ReadReq MSHR miss cycles 943system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12318511000 # number of ReadReq MSHR miss cycles 944system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3521803787 # number of UpgradeReq MSHR miss cycles 945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3521803787 # number of UpgradeReq MSHR miss cycles 946system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13841306537 # number of ReadExReq MSHR miss cycles 947system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13841306537 # number of ReadExReq MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250130000 # number of demand (read+write) MSHR miss cycles 949system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25909687537 # number of demand (read+write) MSHR miss cycles 950system.cpu.l2cache.demand_mshr_miss_latency::total 26159817537 # number of demand (read+write) MSHR miss cycles 951system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250130000 # number of overall MSHR miss cycles 952system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25909687537 # number of overall MSHR miss cycles 953system.cpu.l2cache.overall_mshr_miss_latency::total 26159817537 # number of overall MSHR miss cycles 954system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for ReadReq accesses 955system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099839 # mshr miss rate for ReadReq accesses 956system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses 957system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990451 # mshr miss rate for UpgradeReq accesses 958system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990451 # mshr miss rate for UpgradeReq accesses 959system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268322 # mshr miss rate for ReadExReq accesses 960system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268322 # mshr miss rate for ReadExReq accesses 961system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for demand accesses 962system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for demand accesses 963system.cpu.l2cache.demand_mshr_miss_rate::total 0.151924 # mshr miss rate for demand accesses 964system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for overall accesses 965system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for overall accesses 966system.cpu.l2cache.overall_mshr_miss_rate::total 0.151924 # mshr miss rate for overall accesses 967system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870 # average ReadReq mshr miss latency 968system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277 # average ReadReq mshr miss latency 969system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency 970system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency 971system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency 972system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency 973system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency 974system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency 975system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency 976system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency 977system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency 978system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency 979system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency |
| 980system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 980system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 981system.cpu.toL2Bus.trans_dist::ReadReq 1972322 # Transaction distribution 982system.cpu.toL2Bus.trans_dist::ReadResp 1972321 # Transaction distribution 983system.cpu.toL2Bus.trans_dist::Writeback 2332976 # Transaction distribution 984system.cpu.toL2Bus.trans_dist::UpgradeReq 196692 # Transaction distribution 985system.cpu.toL2Bus.trans_dist::UpgradeResp 196692 # Transaction distribution 986system.cpu.toL2Bus.trans_dist::ReadExReq 771484 # Transaction distribution 987system.cpu.toL2Bus.trans_dist::ReadExResp 771484 # Transaction distribution 988system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214105 # Packet count per connected master and slave (bytes) 989system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803050 # Packet count per connected master and slave (bytes) 990system.cpu.toL2Bus.pkt_count::total 8017155 # Packet count per connected master and slave (bytes) 991system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553216 # Cumulative packet size per connected master and slave (bytes) 992system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311764544 # Cumulative packet size per connected master and slave (bytes) 993system.cpu.toL2Bus.pkt_size::total 312317760 # Cumulative packet size per connected master and slave (bytes) 994system.cpu.toL2Bus.snoops 196816 # Total snoops (count) 995system.cpu.toL2Bus.snoop_fanout::samples 5273474 # Request fanout histogram 996system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram | 981system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution 982system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution 983system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution 984system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution 985system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution 986system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution 987system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution 988system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes) 989system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes) 990system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes) 991system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes) 992system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes) 993system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes) 994system.cpu.toL2Bus.snoops 197098 # Total snoops (count) 995system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram 996system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram |
| 997system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 998system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 999system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 997system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 998system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 999system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1000system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1001system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1002system.cpu.toL2Bus.snoop_fanout::3 5273474 100.00% 100.00% # Request fanout histogram 1003system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram | 1000system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram 1001system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 1004system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1002system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1005system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1006system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1007system.cpu.toL2Bus.snoop_fanout::total 5273474 # Request fanout histogram 1008system.cpu.toL2Bus.reqLayer0.occupancy 4998709391 # Layer occupancy (ticks) | 1003system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1004system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1005system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram 1006system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks) |
| 1009system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) | 1007system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) |
| 1010system.cpu.toL2Bus.respLayer0.occupancy 308726995 # Layer occupancy (ticks) | 1008system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks) |
| 1011system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1009system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1012system.cpu.toL2Bus.respLayer1.occupancy 3988953025 # Layer occupancy (ticks) | 1010system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks) |
| 1013system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) | 1011system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 1014system.membus.trans_dist::ReadReq 179934 # Transaction distribution 1015system.membus.trans_dist::ReadResp 179934 # Transaction distribution 1016system.membus.trans_dist::Writeback 294034 # Transaction distribution 1017system.membus.trans_dist::UpgradeReq 194832 # Transaction distribution 1018system.membus.trans_dist::UpgradeResp 194832 # Transaction distribution 1019system.membus.trans_dist::ReadExReq 206970 # Transaction distribution 1020system.membus.trans_dist::ReadExResp 206970 # Transaction distribution 1021system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1457506 # Packet count per connected master and slave (bytes) 1022system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1457506 # Packet count per connected master and slave (bytes) 1023system.membus.pkt_count::total 1457506 # Packet count per connected master and slave (bytes) 1024system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43580032 # Cumulative packet size per connected master and slave (bytes) 1025system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43580032 # Cumulative packet size per connected master and slave (bytes) 1026system.membus.pkt_size::total 43580032 # Cumulative packet size per connected master and slave (bytes) | 1012system.membus.trans_dist::ReadReq 179950 # Transaction distribution 1013system.membus.trans_dist::ReadResp 179949 # Transaction distribution 1014system.membus.trans_dist::Writeback 294035 # Transaction distribution 1015system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution 1016system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution 1017system.membus.trans_dist::ReadExReq 206980 # Transaction distribution 1018system.membus.trans_dist::ReadExResp 206980 # Transaction distribution 1019system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes) 1020system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes) 1021system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes) 1022system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes) 1023system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes) 1024system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes) |
| 1027system.membus.snoops 0 # Total snoops (count) | 1025system.membus.snoops 0 # Total snoops (count) |
| 1028system.membus.snoop_fanout::samples 875770 # Request fanout histogram | 1026system.membus.snoop_fanout::samples 876098 # Request fanout histogram |
| 1029system.membus.snoop_fanout::mean 0 # Request fanout histogram 1030system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1031system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1027system.membus.snoop_fanout::mean 0 # Request fanout histogram 1028system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1029system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1032system.membus.snoop_fanout::0 875770 100.00% 100.00% # Request fanout histogram | 1030system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram |
| 1033system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1034system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1035system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1036system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1031system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1032system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1033system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1034system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1037system.membus.snoop_fanout::total 875770 # Request fanout histogram 1038system.membus.reqLayer0.occupancy 2246779030 # Layer occupancy (ticks) | 1035system.membus.snoop_fanout::total 876098 # Request fanout histogram 1036system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks) |
| 1039system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) | 1037system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 1040system.membus.respLayer1.occupancy 2437213959 # Layer occupancy (ticks) | 1038system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks) |
| 1041system.membus.respLayer1.utilization 0.6 # Layer utilization (%) 1042 1043---------- End Simulation Statistics ---------- | 1039system.membus.respLayer1.utilization 0.6 # Layer utilization (%) 1040 1041---------- End Simulation Statistics ---------- |