| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.455304 # Number of seconds simulated 4sim_ticks 455304035500 # Number of ticks simulated 5final_tick 455304035500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 97470 # Simulator instruction rate (inst/s) 8host_op_rate 180233 # Simulator op (including micro ops) rate (op/s) --- 565 unchanged lines hidden (view full) --- 574system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 576system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 577system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction 581system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.455304 # Number of seconds simulated 4sim_ticks 455304035500 # Number of ticks simulated 5final_tick 455304035500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 97470 # Simulator instruction rate (inst/s) 8host_op_rate 180233 # Simulator op (including micro ops) rate (op/s) --- 565 unchanged lines hidden (view full) --- 574system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 576system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 577system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction 581system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached |
| 582system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 583system.cpu.rob.rob_reads 2867051516 # The number of ROB reads 584system.cpu.rob.rob_writes 4304473794 # The number of ROB writes 585system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself 586system.cpu.idleCycles 197748 # Total number of cycles that the CPU has spent unscheduled due to idling 587system.cpu.committedInsts 826877109 # Number of Instructions Simulated 588system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 589system.cpu.cpi 1.101262 # CPI: Cycles Per Instruction 590system.cpu.cpi_total 1.101262 # CPI: Total CPI of All Threads --- 455 unchanged lines hidden --- | 582system.cpu.rob.rob_reads 2867051516 # The number of ROB reads 583system.cpu.rob.rob_writes 4304473794 # The number of ROB writes 584system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself 585system.cpu.idleCycles 197748 # Total number of cycles that the CPU has spent unscheduled due to idling 586system.cpu.committedInsts 826877109 # Number of Instructions Simulated 587system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 588system.cpu.cpi 1.101262 # CPI: Cycles Per Instruction 589system.cpu.cpi_total 1.101262 # CPI: Total CPI of All Threads --- 455 unchanged lines hidden --- |