| stats.txt (10036:80e84beef3bb) | stats.txt (10063:9595c7a1d837) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.459106 # Number of seconds simulated 4sim_ticks 459105675500 # Number of ticks simulated 5final_tick 459105675500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.459119 # Number of seconds simulated 4sim_ticks 459118646000 # Number of ticks simulated 5final_tick 459118646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 97287 # Simulator instruction rate (inst/s) 8host_op_rate 179895 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54016738 # Simulator tick rate (ticks/s) 10host_mem_usage 345252 # Number of bytes of host memory used 11host_seconds 8499.32 # Real time elapsed on the host | 7host_inst_rate 66655 # Simulator instruction rate (inst/s) 8host_op_rate 123253 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37009979 # Simulator tick rate (ticks/s) 10host_mem_usage 397004 # Number of bytes of host memory used 11host_seconds 12405.27 # Real time elapsed on the host |
| 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 202240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24471936 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24674176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 202240 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 202240 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18788544 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18788544 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3160 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 382374 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 385534 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 293571 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 293571 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 440509 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 53303493 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 53744001 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 440509 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 440509 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 40924225 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 40924225 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 40924225 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 440509 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 53303493 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 94668226 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 385534 # Number of read requests accepted 40system.physmem.writeReqs 293571 # Number of write requests accepted 41system.physmem.readBursts 385534 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 293571 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24663936 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18787328 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24674176 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18788544 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 202048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24472064 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24674112 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 202048 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 202048 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18787264 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18787264 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3157 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 382376 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 385533 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 293551 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 293551 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 440078 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 53302266 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 53742344 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 440078 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 440078 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 40920281 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 40920281 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 40920281 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 440078 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 53302266 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 94662625 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 385533 # Number of read requests accepted 40system.physmem.writeReqs 293551 # Number of write requests accepted 41system.physmem.readBursts 385533 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 293551 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24663104 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 11008 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18787008 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24674112 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18787264 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 172 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 50system.physmem.neitherReadNorWriteReqs 133980 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24056 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26412 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24662 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24490 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23228 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23668 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24406 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24200 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23616 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23822 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24814 # Per bank write bursts | 50system.physmem.neitherReadNorWriteReqs 134286 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24058 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26419 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24669 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24489 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23234 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23657 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24395 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24194 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23609 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23827 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24795 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::11 24049 # Per bank write bursts | 62system.physmem.perBankRdBursts::11 24049 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::12 23223 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22960 # Per bank write bursts 65system.physmem.perBankRdBursts::14 23777 # Per bank write bursts | 63system.physmem.perBankRdBursts::12 23230 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22964 # Per bank write bursts 65system.physmem.perBankRdBursts::14 23781 # Per bank write bursts |
| 66system.physmem.perBankRdBursts::15 23991 # Per bank write bursts | 66system.physmem.perBankRdBursts::15 23991 # Per bank write bursts |
| 67system.physmem.perBankWrBursts::0 18528 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19813 # Per bank write bursts 69system.physmem.perBankWrBursts::2 18933 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18904 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18032 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18409 # Per bank write bursts 73system.physmem.perBankWrBursts::6 18982 # Per bank write bursts | 67system.physmem.perBankWrBursts::0 18530 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19817 # Per bank write bursts 69system.physmem.perBankWrBursts::2 18937 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18901 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18031 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18405 # Per bank write bursts 73system.physmem.perBankWrBursts::6 18977 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 18937 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 18937 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::8 18536 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18110 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18825 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17714 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17347 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16962 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17712 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17808 # Per bank write bursts | 75system.physmem.perBankWrBursts::8 18537 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18113 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18820 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17706 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17343 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16958 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17714 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17821 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 459105568000 # Total gap between requests | 85system.physmem.totGap 459118532000 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 385534 # Read request sizes (log2) | 92system.physmem.readPktSize::6 385533 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 293571 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 380726 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4314 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 297 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 293551 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 380740 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4302 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 283 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 32 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 13202 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 13202 # What write queue length does an incoming req see |
| 133system.physmem.wrQLenPdf::1 13293 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 13312 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 13323 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 13320 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 13319 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 13374 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 13373 # What write queue length does an incoming req see | 133system.physmem.wrQLenPdf::1 13291 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 13315 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 13327 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 13375 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see |
| 140system.physmem.wrQLenPdf::8 13375 # What write queue length does an incoming req see | 140system.physmem.wrQLenPdf::8 13375 # What write queue length does an incoming req see |
| 141system.physmem.wrQLenPdf::9 13406 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 13420 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 13359 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 13363 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 13367 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 13343 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 13321 # What write queue length does an incoming req see | 141system.physmem.wrQLenPdf::9 13396 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 13419 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 13353 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 13357 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 13368 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 13341 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see |
| 149system.physmem.wrQLenPdf::17 13309 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 13330 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 13311 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 13494 # What write queue length does an incoming req see | 149system.physmem.wrQLenPdf::17 13315 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 13309 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 13490 # What write queue length does an incoming req see |
| 153system.physmem.wrQLenPdf::21 13282 # What write queue length does an incoming req see | 153system.physmem.wrQLenPdf::21 13282 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::22 18 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::22 17 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 164system.physmem.bytesPerActivate::samples 147523 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::mean 294.532839 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::gmean 155.815987 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::stdev 442.359788 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::64 63790 43.24% 43.24% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::128 27848 18.88% 62.12% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::192 12415 8.42% 70.53% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::256 7114 4.82% 75.36% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::320 4845 3.28% 78.64% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::384 3608 2.45% 81.09% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::448 2677 1.81% 82.90% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::512 2233 1.51% 84.41% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::576 1891 1.28% 85.70% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::640 1571 1.06% 86.76% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::704 1991 1.35% 88.11% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::768 1204 0.82% 88.93% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::832 1205 0.82% 89.74% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::896 1076 0.73% 90.47% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::960 955 0.65% 91.12% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1024 927 0.63% 91.75% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1088 1004 0.68% 92.43% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1152 1138 0.77% 93.20% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1216 1120 0.76% 93.96% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1280 845 0.57% 94.53% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1344 784 0.53% 95.06% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1408 5236 3.55% 98.61% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1472 318 0.22% 98.83% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1536 229 0.16% 98.98% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1600 157 0.11% 99.09% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1664 117 0.08% 99.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1728 103 0.07% 99.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1792 91 0.06% 99.30% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1856 87 0.06% 99.36% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1920 53 0.04% 99.40% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1984 53 0.04% 99.43% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2048 37 0.03% 99.46% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2112 48 0.03% 99.49% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2176 24 0.02% 99.51% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2240 28 0.02% 99.52% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2304 24 0.02% 99.54% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2368 28 0.02% 99.56% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2432 24 0.02% 99.58% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2496 15 0.01% 99.59% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2560 23 0.02% 99.60% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2624 31 0.02% 99.62% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2688 20 0.01% 99.64% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2752 27 0.02% 99.65% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2816 23 0.02% 99.67% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2880 23 0.02% 99.69% # Bytes accessed per row activation | 164system.physmem.bytesPerActivate::samples 147556 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::mean 294.463932 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::gmean 155.686360 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::stdev 443.719039 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::64 63845 43.27% 43.27% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::128 27907 18.91% 62.18% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::192 12368 8.38% 70.56% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::256 7167 4.86% 75.42% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::320 4813 3.26% 78.68% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::384 3571 2.42% 81.10% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::448 2697 1.83% 82.93% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::512 2226 1.51% 84.44% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::576 1892 1.28% 85.72% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::640 1575 1.07% 86.79% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::704 1962 1.33% 88.12% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::768 1193 0.81% 88.93% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::832 1191 0.81% 89.73% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::896 1073 0.73% 90.46% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::960 940 0.64% 91.10% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1024 929 0.63% 91.73% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1088 1014 0.69% 92.41% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1152 1122 0.76% 93.17% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1216 1123 0.76% 93.94% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1280 892 0.60% 94.54% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1344 768 0.52% 95.06% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1408 5249 3.56% 98.62% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1472 304 0.21% 98.82% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1536 220 0.15% 98.97% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1600 176 0.12% 99.09% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1664 127 0.09% 99.18% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1728 88 0.06% 99.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1792 94 0.06% 99.30% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1856 86 0.06% 99.36% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1920 56 0.04% 99.40% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1984 55 0.04% 99.44% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2048 48 0.03% 99.47% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2112 43 0.03% 99.50% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2176 26 0.02% 99.51% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2240 35 0.02% 99.54% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2304 32 0.02% 99.56% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2368 24 0.02% 99.58% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2432 27 0.02% 99.59% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2496 18 0.01% 99.61% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2688 20 0.01% 99.65% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2752 23 0.02% 99.66% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2816 17 0.01% 99.68% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2880 18 0.01% 99.69% # Bytes accessed per row activation |
| 213system.physmem.bytesPerActivate::2944 20 0.01% 99.70% # Bytes accessed per row activation | 213system.physmem.bytesPerActivate::2944 20 0.01% 99.70% # Bytes accessed per row activation |
| 214system.physmem.bytesPerActivate::3008 23 0.02% 99.72% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3072 23 0.02% 99.73% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3136 19 0.01% 99.74% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3200 14 0.01% 99.75% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3264 18 0.01% 99.77% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3328 16 0.01% 99.78% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3392 9 0.01% 99.78% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3456 13 0.01% 99.79% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3520 16 0.01% 99.80% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3584 16 0.01% 99.81% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3648 15 0.01% 99.82% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3712 8 0.01% 99.83% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3776 10 0.01% 99.84% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3840 5 0.00% 99.84% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3904 11 0.01% 99.85% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3968 8 0.01% 99.85% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4032 10 0.01% 99.86% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4096 6 0.00% 99.86% # Bytes accessed per row activation | 214system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3072 19 0.01% 99.73% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3136 14 0.01% 99.74% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3200 17 0.01% 99.75% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3264 12 0.01% 99.75% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3328 19 0.01% 99.77% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3392 5 0.00% 99.77% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3456 18 0.01% 99.78% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3584 8 0.01% 99.80% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3648 14 0.01% 99.81% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3712 10 0.01% 99.81% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3776 15 0.01% 99.82% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3904 9 0.01% 99.84% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3968 11 0.01% 99.84% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4032 10 0.01% 99.85% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4096 12 0.01% 99.86% # Bytes accessed per row activation |
| 232system.physmem.bytesPerActivate::4160 14 0.01% 99.87% # Bytes accessed per row activation | 232system.physmem.bytesPerActivate::4160 14 0.01% 99.87% # Bytes accessed per row activation |
| 233system.physmem.bytesPerActivate::4224 17 0.01% 99.88% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4288 34 0.02% 99.91% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4352 3 0.00% 99.91% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4416 7 0.00% 99.91% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4480 2 0.00% 99.91% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4544 6 0.00% 99.92% # Bytes accessed per row activation | 233system.physmem.bytesPerActivate::4224 20 0.01% 99.88% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4288 31 0.02% 99.90% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4352 4 0.00% 99.90% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4416 10 0.01% 99.91% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4480 3 0.00% 99.91% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation |
| 239system.physmem.bytesPerActivate::4608 2 0.00% 99.92% # Bytes accessed per row activation | 239system.physmem.bytesPerActivate::4608 2 0.00% 99.92% # Bytes accessed per row activation |
| 240system.physmem.bytesPerActivate::4672 3 0.00% 99.92% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4736 5 0.00% 99.93% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4800 6 0.00% 99.93% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4864 1 0.00% 99.93% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4928 6 0.00% 99.93% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4992 5 0.00% 99.94% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5056 6 0.00% 99.94% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5120 5 0.00% 99.95% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5184 2 0.00% 99.95% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5248 2 0.00% 99.95% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5312 4 0.00% 99.95% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5376 3 0.00% 99.95% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5440 6 0.00% 99.96% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5504 3 0.00% 99.96% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5568 1 0.00% 99.96% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5760 4 0.00% 99.97% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5824 4 0.00% 99.97% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5888 6 0.00% 99.97% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5952 4 0.00% 99.97% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6016 7 0.00% 99.98% # Bytes accessed per row activation | 240system.physmem.bytesPerActivate::4672 6 0.00% 99.92% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4736 6 0.00% 99.93% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4800 2 0.00% 99.93% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4928 2 0.00% 99.93% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4992 4 0.00% 99.93% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5184 4 0.00% 99.94% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5376 1 0.00% 99.95% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5504 3 0.00% 99.95% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5568 3 0.00% 99.95% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5632 2 0.00% 99.95% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5760 6 0.00% 99.96% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5888 9 0.01% 99.97% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6016 11 0.01% 99.98% # Bytes accessed per row activation |
| 262system.physmem.bytesPerActivate::6080 4 0.00% 99.98% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6144 1 0.00% 99.98% # Bytes accessed per row activation | 261system.physmem.bytesPerActivate::6080 4 0.00% 99.98% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6144 1 0.00% 99.98% # Bytes accessed per row activation |
| 264system.physmem.bytesPerActivate::6208 2 0.00% 99.98% # Bytes accessed per row activation | 263system.physmem.bytesPerActivate::6208 3 0.00% 99.98% # Bytes accessed per row activation |
| 265system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation | 264system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation |
| 266system.physmem.bytesPerActivate::6336 2 0.00% 100.00% # Bytes accessed per row activation | 265system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation |
| 267system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation | 266system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation |
| 268system.physmem.bytesPerActivate::7104 1 0.00% 100.00% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::total 147523 # Bytes accessed per row activation 270system.physmem.totQLat 3823508500 # Total ticks spent queuing 271system.physmem.totMemAccLat 12080026000 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 1926870000 # Total ticks spent in databus transfers 273system.physmem.totBankLat 6329647500 # Total ticks spent accessing banks 274system.physmem.avgQLat 9921.55 # Average queueing delay per DRAM burst 275system.physmem.avgBankLat 16424.69 # Average bank access latency per DRAM burst | 267system.physmem.bytesPerActivate::7872 1 0.00% 100.00% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::total 147556 # Bytes accessed per row activation 269system.physmem.totQLat 3828283250 # Total ticks spent queuing 270system.physmem.totMemAccLat 12084928250 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 1926805000 # Total ticks spent in databus transfers 272system.physmem.totBankLat 6329840000 # Total ticks spent accessing banks 273system.physmem.avgQLat 9934.28 # Average queueing delay per DRAM burst 274system.physmem.avgBankLat 16425.74 # Average bank access latency per DRAM burst |
| 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 277system.physmem.avgMemAccLat 31346.24 # Average memory access latency per DRAM burst | 276system.physmem.avgMemAccLat 31360.02 # Average memory access latency per DRAM burst |
| 278system.physmem.avgRdBW 53.72 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 40.92 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 53.74 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 40.92 # Average system write bandwidth in MiByte/s 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.74 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing | 277system.physmem.avgRdBW 53.72 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 40.92 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 53.74 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 40.92 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.74 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing |
| 287system.physmem.avgWrQLen 9.75 # Average write queue length when enqueuing 288system.physmem.readRowHits 326967 # Number of row buffer hits during reads 289system.physmem.writeRowHits 204436 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 84.84 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes 292system.physmem.avgGap 676045.04 # Average gap between requests | 286system.physmem.avgWrQLen 9.64 # Average write queue length when enqueuing 287system.physmem.readRowHits 326971 # Number of row buffer hits during reads 288system.physmem.writeRowHits 204381 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 84.85 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 69.62 # Row buffer hit rate for writes 291system.physmem.avgGap 676085.04 # Average gap between requests |
| 293system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined | 292system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined |
| 294system.physmem.prechargeAllPercent 5.78 # Percentage of time for which DRAM has all the banks in precharge state 295system.membus.throughput 94668226 # Throughput (bytes/s) 296system.membus.trans_dist::ReadReq 178706 # Transaction distribution 297system.membus.trans_dist::ReadResp 178706 # Transaction distribution 298system.membus.trans_dist::Writeback 293571 # Transaction distribution 299system.membus.trans_dist::UpgradeReq 133980 # Transaction distribution 300system.membus.trans_dist::UpgradeResp 133980 # Transaction distribution 301system.membus.trans_dist::ReadExReq 206828 # Transaction distribution 302system.membus.trans_dist::ReadExResp 206828 # Transaction distribution 303system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1332599 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1332599 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count::total 1332599 # Packet count per connected master and slave (bytes) 306system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43462720 # Cumulative packet size per connected master and slave (bytes) 307system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43462720 # Cumulative packet size per connected master and slave (bytes) 308system.membus.tot_pkt_size::total 43462720 # Cumulative packet size per connected master and slave (bytes) 309system.membus.data_through_bus 43462720 # Total data (bytes) | 293system.physmem.prechargeAllPercent 5.79 # Percentage of time for which DRAM has all the banks in precharge state 294system.membus.throughput 94662625 # Throughput (bytes/s) 295system.membus.trans_dist::ReadReq 178699 # Transaction distribution 296system.membus.trans_dist::ReadResp 178699 # Transaction distribution 297system.membus.trans_dist::Writeback 293551 # Transaction distribution 298system.membus.trans_dist::UpgradeReq 134286 # Transaction distribution 299system.membus.trans_dist::UpgradeResp 134286 # Transaction distribution 300system.membus.trans_dist::ReadExReq 206834 # Transaction distribution 301system.membus.trans_dist::ReadExResp 206834 # Transaction distribution 302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1333189 # Packet count per connected master and slave (bytes) 303system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1333189 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count::total 1333189 # Packet count per connected master and slave (bytes) 305system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43461376 # Cumulative packet size per connected master and slave (bytes) 306system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43461376 # Cumulative packet size per connected master and slave (bytes) 307system.membus.tot_pkt_size::total 43461376 # Cumulative packet size per connected master and slave (bytes) 308system.membus.data_through_bus 43461376 # Total data (bytes) |
| 310system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 309system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 311system.membus.reqLayer0.occupancy 3389205500 # Layer occupancy (ticks) | 310system.membus.reqLayer0.occupancy 3389612000 # Layer occupancy (ticks) |
| 312system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) | 311system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 313system.membus.respLayer1.occupancy 3898787780 # Layer occupancy (ticks) | 312system.membus.respLayer1.occupancy 3899599974 # Layer occupancy (ticks) |
| 314system.membus.respLayer1.utilization 0.8 # Layer utilization (%) 315system.cpu_clk_domain.clock 500 # Clock period in ticks | 313system.membus.respLayer1.utilization 0.8 # Layer utilization (%) 314system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 316system.cpu.branchPred.lookups 205604659 # Number of BP lookups 317system.cpu.branchPred.condPredicted 205604659 # Number of conditional branches predicted 318system.cpu.branchPred.condIncorrect 9906655 # Number of conditional branches incorrect 319system.cpu.branchPred.BTBLookups 117175952 # Number of BTB lookups 320system.cpu.branchPred.BTBHits 114700451 # Number of BTB hits | 315system.cpu.branchPred.lookups 205593718 # Number of BP lookups 316system.cpu.branchPred.condPredicted 205593718 # Number of conditional branches predicted 317system.cpu.branchPred.condIncorrect 9903647 # Number of conditional branches incorrect 318system.cpu.branchPred.BTBLookups 117157105 # Number of BTB lookups 319system.cpu.branchPred.BTBHits 114691543 # Number of BTB hits |
| 321system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 320system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 322system.cpu.branchPred.BTBHitPct 97.887364 # BTB Hit Percentage 323system.cpu.branchPred.usedRAS 25061463 # Number of times the RAS was used to get a target. 324system.cpu.branchPred.RASInCorrect 1805826 # Number of incorrect RAS predictions. | 321system.cpu.branchPred.BTBHitPct 97.895508 # BTB Hit Percentage 322system.cpu.branchPred.usedRAS 25059747 # Number of times the RAS was used to get a target. 323system.cpu.branchPred.RASInCorrect 1804675 # Number of incorrect RAS predictions. |
| 325system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 326system.cpu.workload.num_syscalls 551 # Number of system calls | 324system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 325system.cpu.workload.num_syscalls 551 # Number of system calls |
| 327system.cpu.numCycles 918372988 # number of cpu cycles simulated | 326system.cpu.numCycles 918398587 # number of cpu cycles simulated |
| 328system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 329system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 327system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 328system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 330system.cpu.fetch.icacheStallCycles 167405307 # Number of cycles fetch is stalled on an Icache miss 331system.cpu.fetch.Insts 1131731622 # Number of instructions fetch has processed 332system.cpu.fetch.Branches 205604659 # Number of branches that fetch encountered 333system.cpu.fetch.predictedBranches 139761914 # Number of branches that fetch has predicted taken 334system.cpu.fetch.Cycles 352276692 # Number of cycles fetch has run and was not squashing or blocked 335system.cpu.fetch.SquashCycles 71095438 # Number of cycles fetch has spent squashing 336system.cpu.fetch.BlockedCycles 305025706 # Number of cycles fetch has spent blocked 337system.cpu.fetch.MiscStallCycles 47339 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 338system.cpu.fetch.PendingTrapStallCycles 248116 # Number of stall cycles due to pending traps | 329system.cpu.fetch.icacheStallCycles 167393029 # Number of cycles fetch is stalled on an Icache miss 330system.cpu.fetch.Insts 1131661435 # Number of instructions fetch has processed 331system.cpu.fetch.Branches 205593718 # Number of branches that fetch encountered 332system.cpu.fetch.predictedBranches 139751290 # Number of branches that fetch has predicted taken 333system.cpu.fetch.Cycles 352253008 # Number of cycles fetch has run and was not squashing or blocked 334system.cpu.fetch.SquashCycles 71076779 # Number of cycles fetch has spent squashing 335system.cpu.fetch.BlockedCycles 305103735 # Number of cycles fetch has spent blocked 336system.cpu.fetch.MiscStallCycles 48807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 337system.cpu.fetch.PendingTrapStallCycles 255424 # Number of stall cycles due to pending traps |
| 339system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR | 338system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR |
| 340system.cpu.fetch.CacheLines 162029256 # Number of cache lines fetched 341system.cpu.fetch.IcacheSquashes 2531741 # Number of outstanding Icache misses that were squashed 342system.cpu.fetch.rateDist::samples 885941657 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::mean 2.376715 # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::stdev 3.323883 # Number of instructions fetched each cycle (Total) | 339system.cpu.fetch.CacheLines 162015300 # Number of cache lines fetched 340system.cpu.fetch.IcacheSquashes 2531137 # Number of outstanding Icache misses that were squashed 341system.cpu.fetch.rateDist::samples 885975121 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::mean 2.376486 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::stdev 3.323818 # Number of instructions fetched each cycle (Total) |
| 345system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 344system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 346system.cpu.fetch.rateDist::0 537736172 60.70% 60.70% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::1 23397075 2.64% 63.34% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::2 25259789 2.85% 66.19% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::3 27891024 3.15% 69.34% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::4 17747651 2.00% 71.34% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::5 22912562 2.59% 73.93% # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::6 29424314 3.32% 77.25% # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::7 26642726 3.01% 80.25% # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::8 174930344 19.75% 100.00% # Number of instructions fetched each cycle (Total) | 345system.cpu.fetch.rateDist::0 537792455 60.70% 60.70% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::1 23395629 2.64% 63.34% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::2 25258320 2.85% 66.19% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::3 27887801 3.15% 69.34% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::4 17745441 2.00% 71.34% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::5 22910084 2.59% 73.93% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::6 29420868 3.32% 77.25% # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::7 26641357 3.01% 80.26% # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::8 174923166 19.74% 100.00% # Number of instructions fetched each cycle (Total) |
| 355system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 354system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 358system.cpu.fetch.rateDist::total 885941657 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.branchRate 0.223879 # Number of branch fetches per cycle 360system.cpu.fetch.rate 1.232322 # Number of inst fetches per cycle 361system.cpu.decode.IdleCycles 222573687 # Number of cycles decode is idle 362system.cpu.decode.BlockedCycles 260132185 # Number of cycles decode is blocked 363system.cpu.decode.RunCycles 295357990 # Number of cycles decode is running 364system.cpu.decode.UnblockCycles 46939340 # Number of cycles decode is unblocking 365system.cpu.decode.SquashCycles 60938455 # Number of cycles decode is squashing 366system.cpu.decode.DecodedInsts 2071381091 # Number of instructions handled by decode 367system.cpu.decode.SquashedInsts 5 # Number of squashed instructions handled by decode 368system.cpu.rename.SquashCycles 60938455 # Number of cycles rename is squashing 369system.cpu.rename.IdleCycles 256079146 # Number of cycles rename is idle 370system.cpu.rename.BlockCycles 115670707 # Number of cycles rename is blocking 371system.cpu.rename.serializeStallCycles 18358 # count of cycles rename stalled for serializing inst 372system.cpu.rename.RunCycles 306659021 # Number of cycles rename is running 373system.cpu.rename.UnblockCycles 146575970 # Number of cycles rename is unblocking 374system.cpu.rename.RenamedInsts 2035220367 # Number of instructions processed by rename 375system.cpu.rename.ROBFullEvents 19921 # Number of times rename has blocked due to ROB full 376system.cpu.rename.IQFullEvents 24919931 # Number of times rename has blocked due to IQ full 377system.cpu.rename.LSQFullEvents 106353414 # Number of times rename has blocked due to LSQ full 378system.cpu.rename.RenamedOperands 2138170371 # Number of destination operands rename has renamed 379system.cpu.rename.RenameLookups 5150798156 # Number of register rename lookups that rename has made 380system.cpu.rename.int_rename_lookups 3273538468 # Number of integer rename lookups 381system.cpu.rename.fp_rename_lookups 41295 # Number of floating rename lookups | 357system.cpu.fetch.rateDist::total 885975121 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.branchRate 0.223861 # Number of branch fetches per cycle 359system.cpu.fetch.rate 1.232212 # Number of inst fetches per cycle 360system.cpu.decode.IdleCycles 222542151 # Number of cycles decode is idle 361system.cpu.decode.BlockedCycles 260234378 # Number of cycles decode is blocked 362system.cpu.decode.RunCycles 295346908 # Number of cycles decode is running 363system.cpu.decode.UnblockCycles 46930608 # Number of cycles decode is unblocking 364system.cpu.decode.SquashCycles 60921076 # Number of cycles decode is squashing 365system.cpu.decode.DecodedInsts 2071264981 # Number of instructions handled by decode 366system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode 367system.cpu.rename.SquashCycles 60921076 # Number of cycles rename is squashing 368system.cpu.rename.IdleCycles 256051169 # Number of cycles rename is idle 369system.cpu.rename.BlockCycles 115707666 # Number of cycles rename is blocking 370system.cpu.rename.serializeStallCycles 18212 # count of cycles rename stalled for serializing inst 371system.cpu.rename.RunCycles 306637897 # Number of cycles rename is running 372system.cpu.rename.UnblockCycles 146639101 # Number of cycles rename is unblocking 373system.cpu.rename.RenamedInsts 2035099231 # Number of instructions processed by rename 374system.cpu.rename.ROBFullEvents 19841 # Number of times rename has blocked due to ROB full 375system.cpu.rename.IQFullEvents 24966361 # Number of times rename has blocked due to IQ full 376system.cpu.rename.LSQFullEvents 106369922 # Number of times rename has blocked due to LSQ full 377system.cpu.rename.RenamedOperands 2138037437 # Number of destination operands rename has renamed 378system.cpu.rename.RenameLookups 5150524594 # Number of register rename lookups that rename has made 379system.cpu.rename.int_rename_lookups 3273371991 # Number of integer rename lookups 380system.cpu.rename.fp_rename_lookups 41733 # Number of floating rename lookups |
| 382system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed | 381system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed |
| 383system.cpu.rename.UndoneMaps 524129517 # Number of HB maps that are undone due to squashing 384system.cpu.rename.serializingInsts 1246 # count of serializing insts renamed 385system.cpu.rename.tempSerializingInsts 1179 # count of temporary serializing insts renamed 386system.cpu.rename.skidInsts 346542949 # count of insts added to the skid buffer 387system.cpu.memDep0.insertedLoads 495881862 # Number of loads inserted to the mem dependence unit. 388system.cpu.memDep0.insertedStores 194416479 # Number of stores inserted to the mem dependence unit. 389system.cpu.memDep0.conflictingLoads 195473768 # Number of conflicting loads. 390system.cpu.memDep0.conflictingStores 54732552 # Number of conflicting stores. 391system.cpu.iq.iqInstsAdded 1975446731 # Number of instructions added to the IQ (excludes non-spec) 392system.cpu.iq.iqNonSpecInstsAdded 13521 # Number of non-speculative instructions added to the IQ 393system.cpu.iq.iqInstsIssued 1772053501 # Number of instructions issued 394system.cpu.iq.iqSquashedInstsIssued 482535 # Number of squashed instructions issued 395system.cpu.iq.iqSquashedInstsExamined 441556981 # Number of squashed instructions iterated over during squash; mainly for profiling 396system.cpu.iq.iqSquashedOperandsExamined 735252947 # Number of squashed operands that are examined and possibly removed from graph 397system.cpu.iq.iqSquashedNonSpecRemoved 12969 # Number of squashed non-spec instructions that were removed 398system.cpu.iq.issued_per_cycle::samples 885941657 # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::mean 2.000192 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::stdev 1.883038 # Number of insts issued each cycle | 382system.cpu.rename.UndoneMaps 523996583 # Number of HB maps that are undone due to squashing 383system.cpu.rename.serializingInsts 1255 # count of serializing insts renamed 384system.cpu.rename.tempSerializingInsts 1189 # count of temporary serializing insts renamed 385system.cpu.rename.skidInsts 346554163 # count of insts added to the skid buffer 386system.cpu.memDep0.insertedLoads 495859665 # Number of loads inserted to the mem dependence unit. 387system.cpu.memDep0.insertedStores 194411587 # Number of stores inserted to the mem dependence unit. 388system.cpu.memDep0.conflictingLoads 195293101 # Number of conflicting loads. 389system.cpu.memDep0.conflictingStores 54696349 # Number of conflicting stores. 390system.cpu.iq.iqInstsAdded 1975355646 # Number of instructions added to the IQ (excludes non-spec) 391system.cpu.iq.iqNonSpecInstsAdded 13955 # Number of non-speculative instructions added to the IQ 392system.cpu.iq.iqInstsIssued 1772015968 # Number of instructions issued 393system.cpu.iq.iqSquashedInstsIssued 483793 # Number of squashed instructions issued 394system.cpu.iq.iqSquashedInstsExamined 441457587 # Number of squashed instructions iterated over during squash; mainly for profiling 395system.cpu.iq.iqSquashedOperandsExamined 735091170 # Number of squashed operands that are examined and possibly removed from graph 396system.cpu.iq.iqSquashedNonSpecRemoved 13403 # Number of squashed non-spec instructions that were removed 397system.cpu.iq.issued_per_cycle::samples 885975121 # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::mean 2.000074 # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::stdev 1.882925 # Number of insts issued each cycle |
| 401system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 400system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 402system.cpu.iq.issued_per_cycle::0 269231258 30.39% 30.39% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::1 151900240 17.15% 47.53% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::2 137366514 15.51% 63.04% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::3 131748871 14.87% 77.91% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::4 91701810 10.35% 88.26% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::5 55961984 6.32% 94.58% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::6 34425337 3.89% 98.46% # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::7 11840706 1.34% 99.80% # Number of insts issued each cycle 410system.cpu.iq.issued_per_cycle::8 1764937 0.20% 100.00% # Number of insts issued each cycle | 401system.cpu.iq.issued_per_cycle::0 269258289 30.39% 30.39% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::1 151881714 17.14% 47.53% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::2 137407528 15.51% 63.04% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::3 131753954 14.87% 77.91% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::4 91677002 10.35% 88.26% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::5 55986071 6.32% 94.58% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::6 34414851 3.88% 98.47% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::7 11835829 1.34% 99.80% # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::8 1759883 0.20% 100.00% # Number of insts issued each cycle |
| 411system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 412system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 413system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 410system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 411system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 412system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 414system.cpu.iq.issued_per_cycle::total 885941657 # Number of insts issued each cycle | 413system.cpu.iq.issued_per_cycle::total 885975121 # Number of insts issued each cycle |
| 415system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 414system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 416system.cpu.iq.fu_full::IntAlu 4931859 32.39% 32.39% # attempts to use FU when none available 417system.cpu.iq.fu_full::IntMult 0 0.00% 32.39% # attempts to use FU when none available 418system.cpu.iq.fu_full::IntDiv 0 0.00% 32.39% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.39% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.39% # attempts to use FU when none available 421system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.39% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatMult 0 0.00% 32.39% # attempts to use FU when none available 423system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.39% # attempts to use FU when none available 424system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.39% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.39% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.39% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.39% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.39% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.39% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.39% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdMult 0 0.00% 32.39% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.39% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdShift 0 0.00% 32.39% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.39% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.39% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.39% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.39% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.39% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.39% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.39% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.39% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.39% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.39% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.39% # attempts to use FU when none available 445system.cpu.iq.fu_full::MemRead 7680982 50.45% 82.84% # attempts to use FU when none available 446system.cpu.iq.fu_full::MemWrite 2612006 17.16% 100.00% # attempts to use FU when none available | 415system.cpu.iq.fu_full::IntAlu 4932504 32.46% 32.46% # attempts to use FU when none available 416system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available 417system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available 421system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available 423system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available 444system.cpu.iq.fu_full::MemRead 7653540 50.37% 82.83% # attempts to use FU when none available 445system.cpu.iq.fu_full::MemWrite 2609071 17.17% 100.00% # attempts to use FU when none available |
| 447system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 448system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 446system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 447system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 449system.cpu.iq.FU_type_0::No_OpClass 2622482 0.15% 0.15% # Type of FU issued 450system.cpu.iq.FU_type_0::IntAlu 1165712605 65.78% 65.93% # Type of FU issued 451system.cpu.iq.FU_type_0::IntMult 353084 0.02% 65.95% # Type of FU issued 452system.cpu.iq.FU_type_0::IntDiv 3880807 0.22% 66.17% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued | 448system.cpu.iq.FU_type_0::No_OpClass 2623104 0.15% 0.15% # Type of FU issued 449system.cpu.iq.FU_type_0::IntAlu 1165669250 65.78% 65.93% # Type of FU issued 450system.cpu.iq.FU_type_0::IntMult 353281 0.02% 65.95% # Type of FU issued 451system.cpu.iq.FU_type_0::IntDiv 3880805 0.22% 66.17% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatAdd 50 0.00% 66.17% # Type of FU issued |
| 454system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued 455system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued 456system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued 457system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued 458system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 471system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued | 453system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued 455system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued 456system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued 457system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 470system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued |
| 479system.cpu.iq.FU_type_0::MemRead 429261253 24.22% 90.39% # Type of FU issued 480system.cpu.iq.FU_type_0::MemWrite 170223265 9.61% 100.00% # Type of FU issued | 478system.cpu.iq.FU_type_0::MemRead 429265174 24.22% 90.39% # Type of FU issued 479system.cpu.iq.FU_type_0::MemWrite 170224304 9.61% 100.00% # Type of FU issued |
| 481system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 482system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 480system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 481system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 483system.cpu.iq.FU_type_0::total 1772053501 # Type of FU issued 484system.cpu.iq.rate 1.929558 # Inst issue rate 485system.cpu.iq.fu_busy_cnt 15224847 # FU busy when requested 486system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst) 487system.cpu.iq.int_inst_queue_reads 4445741046 # Number of integer instruction queue reads 488system.cpu.iq.int_inst_queue_writes 2417220510 # Number of integer instruction queue writes 489system.cpu.iq.int_inst_queue_wakeup_accesses 1744818779 # Number of integer instruction queue wakeup accesses 490system.cpu.iq.fp_inst_queue_reads 14995 # Number of floating instruction queue reads 491system.cpu.iq.fp_inst_queue_writes 52000 # Number of floating instruction queue writes 492system.cpu.iq.fp_inst_queue_wakeup_accesses 3560 # Number of floating instruction queue wakeup accesses 493system.cpu.iq.int_alu_accesses 1784648801 # Number of integer alu accesses 494system.cpu.iq.fp_alu_accesses 7065 # Number of floating point alu accesses 495system.cpu.iew.lsq.thread0.forwLoads 172668148 # Number of loads that had data forwarded from stores | 482system.cpu.iq.FU_type_0::total 1772015968 # Type of FU issued 483system.cpu.iq.rate 1.929463 # Inst issue rate 484system.cpu.iq.fu_busy_cnt 15195115 # FU busy when requested 485system.cpu.iq.fu_busy_rate 0.008575 # FU busy rate (busy events/executed inst) 486system.cpu.iq.int_inst_queue_reads 4445670799 # Number of integer instruction queue reads 487system.cpu.iq.int_inst_queue_writes 2417030484 # Number of integer instruction queue writes 488system.cpu.iq.int_inst_queue_wakeup_accesses 1744778187 # Number of integer instruction queue wakeup accesses 489system.cpu.iq.fp_inst_queue_reads 15166 # Number of floating instruction queue reads 490system.cpu.iq.fp_inst_queue_writes 51932 # Number of floating instruction queue writes 491system.cpu.iq.fp_inst_queue_wakeup_accesses 3516 # Number of floating instruction queue wakeup accesses 492system.cpu.iq.int_alu_accesses 1784580890 # Number of integer alu accesses 493system.cpu.iq.fp_alu_accesses 7089 # Number of floating point alu accesses 494system.cpu.iew.lsq.thread0.forwLoads 172585161 # Number of loads that had data forwarded from stores |
| 496system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 495system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 497system.cpu.iew.lsq.thread0.squashedLoads 111780722 # Number of loads squashed 498system.cpu.iew.lsq.thread0.ignoredResponses 387016 # Number of memory responses ignored because the instruction is squashed 499system.cpu.iew.lsq.thread0.memOrderViolation 326982 # Number of memory ordering violations 500system.cpu.iew.lsq.thread0.squashedStores 45256293 # Number of stores squashed | 496system.cpu.iew.lsq.thread0.squashedLoads 111758592 # Number of loads squashed 497system.cpu.iew.lsq.thread0.ignoredResponses 386790 # Number of memory responses ignored because the instruction is squashed 498system.cpu.iew.lsq.thread0.memOrderViolation 327293 # Number of memory ordering violations 499system.cpu.iew.lsq.thread0.squashedStores 45251401 # Number of stores squashed |
| 501system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 502system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 500system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 501system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 503system.cpu.iew.lsq.thread0.rescheduledLoads 15018 # Number of loads that were rescheduled 504system.cpu.iew.lsq.thread0.cacheBlocked 570 # Number of times an access to memory failed due to the cache being blocked | 502system.cpu.iew.lsq.thread0.rescheduledLoads 14735 # Number of loads that were rescheduled 503system.cpu.iew.lsq.thread0.cacheBlocked 596 # Number of times an access to memory failed due to the cache being blocked |
| 505system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 504system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 506system.cpu.iew.iewSquashCycles 60938455 # Number of cycles IEW is squashing 507system.cpu.iew.iewBlockCycles 67998417 # Number of cycles IEW is blocking 508system.cpu.iew.iewUnblockCycles 7163340 # Number of cycles IEW is unblocking 509system.cpu.iew.iewDispatchedInsts 1975460252 # Number of instructions dispatched to IQ 510system.cpu.iew.iewDispSquashedInsts 795198 # Number of squashed instructions skipped by dispatch 511system.cpu.iew.iewDispLoadInsts 495882879 # Number of dispatched load instructions 512system.cpu.iew.iewDispStoreInsts 194416479 # Number of dispatched store instructions 513system.cpu.iew.iewDispNonSpecInsts 3400 # Number of dispatched non-speculative instructions 514system.cpu.iew.iewIQFullEvents 4461902 # Number of times the IQ has become full, causing a stall 515system.cpu.iew.iewLSQFullEvents 83950 # Number of times the LSQ has become full, causing a stall 516system.cpu.iew.memOrderViolationEvents 326982 # Number of memory order violations 517system.cpu.iew.predictedTakenIncorrect 5904539 # Number of branches that were predicted taken incorrectly 518system.cpu.iew.predictedNotTakenIncorrect 4423611 # Number of branches that were predicted not taken incorrectly 519system.cpu.iew.branchMispredicts 10328150 # Number of branch mispredicts detected at execute 520system.cpu.iew.iewExecutedInsts 1752928715 # Number of executed instructions 521system.cpu.iew.iewExecLoadInsts 424128579 # Number of load instructions executed 522system.cpu.iew.iewExecSquashedInsts 19124786 # Number of squashed instructions skipped in execute | 505system.cpu.iew.iewSquashCycles 60921076 # Number of cycles IEW is squashing 506system.cpu.iew.iewBlockCycles 68026001 # Number of cycles IEW is blocking 507system.cpu.iew.iewUnblockCycles 7165661 # Number of cycles IEW is unblocking 508system.cpu.iew.iewDispatchedInsts 1975369601 # Number of instructions dispatched to IQ 509system.cpu.iew.iewDispSquashedInsts 781836 # Number of squashed instructions skipped by dispatch 510system.cpu.iew.iewDispLoadInsts 495860749 # Number of dispatched load instructions 511system.cpu.iew.iewDispStoreInsts 194411587 # Number of dispatched store instructions 512system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions 513system.cpu.iew.iewIQFullEvents 4462926 # Number of times the IQ has become full, causing a stall 514system.cpu.iew.iewLSQFullEvents 83952 # Number of times the LSQ has become full, causing a stall 515system.cpu.iew.memOrderViolationEvents 327293 # Number of memory order violations 516system.cpu.iew.predictedTakenIncorrect 5902213 # Number of branches that were predicted taken incorrectly 517system.cpu.iew.predictedNotTakenIncorrect 4423139 # Number of branches that were predicted not taken incorrectly 518system.cpu.iew.branchMispredicts 10325352 # Number of branch mispredicts detected at execute 519system.cpu.iew.iewExecutedInsts 1752891418 # Number of executed instructions 520system.cpu.iew.iewExecLoadInsts 424133385 # Number of load instructions executed 521system.cpu.iew.iewExecSquashedInsts 19124550 # Number of squashed instructions skipped in execute |
| 523system.cpu.iew.exec_swp 0 # number of swp insts executed 524system.cpu.iew.exec_nop 0 # number of nop insts executed | 522system.cpu.iew.exec_swp 0 # number of swp insts executed 523system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 525system.cpu.iew.exec_refs 590915769 # number of memory reference insts executed 526system.cpu.iew.exec_branches 167467646 # Number of branches executed 527system.cpu.iew.exec_stores 166787190 # Number of stores executed 528system.cpu.iew.exec_rate 1.908733 # Inst execution rate 529system.cpu.iew.wb_sent 1749675549 # cumulative count of insts sent to commit 530system.cpu.iew.wb_count 1744822339 # cumulative count of insts written-back 531system.cpu.iew.wb_producers 1324948168 # num instructions producing a value 532system.cpu.iew.wb_consumers 1945614075 # num instructions consuming a value | 524system.cpu.iew.exec_refs 590919865 # number of memory reference insts executed 525system.cpu.iew.exec_branches 167459905 # Number of branches executed 526system.cpu.iew.exec_stores 166786480 # Number of stores executed 527system.cpu.iew.exec_rate 1.908639 # Inst execution rate 528system.cpu.iew.wb_sent 1749637243 # cumulative count of insts sent to commit 529system.cpu.iew.wb_count 1744781703 # cumulative count of insts written-back 530system.cpu.iew.wb_producers 1324895228 # num instructions producing a value 531system.cpu.iew.wb_consumers 1945542332 # num instructions consuming a value |
| 533system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 532system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 534system.cpu.iew.wb_rate 1.899906 # insts written-back per cycle 535system.cpu.iew.wb_fanout 0.680992 # average fanout of values written-back | 533system.cpu.iew.wb_rate 1.899809 # insts written-back per cycle 534system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back |
| 536system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 535system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 537system.cpu.commit.commitSquashedInsts 446501460 # The number of squashed insts skipped by commit | 536system.cpu.commit.commitSquashedInsts 446410033 # The number of squashed insts skipped by commit |
| 538system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 537system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 539system.cpu.commit.branchMispredicts 9934679 # The number of times a branch was mispredicted 540system.cpu.commit.committed_per_cycle::samples 825003202 # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::mean 1.853312 # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::stdev 2.435859 # Number of insts commited each cycle | 538system.cpu.commit.branchMispredicts 9933076 # The number of times a branch was mispredicted 539system.cpu.commit.committed_per_cycle::samples 825054045 # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::mean 1.853198 # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::stdev 2.435700 # Number of insts commited each cycle |
| 543system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 542system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 544system.cpu.commit.committed_per_cycle::0 333018307 40.37% 40.37% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::1 193164035 23.41% 63.78% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::2 63275385 7.67% 71.45% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::3 92552193 11.22% 82.67% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::4 24927805 3.02% 85.69% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::5 27507260 3.33% 89.02% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::6 9364368 1.14% 90.16% # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::7 11367203 1.38% 91.54% # Number of insts commited each cycle 552system.cpu.commit.committed_per_cycle::8 69826646 8.46% 100.00% # Number of insts commited each cycle | 543system.cpu.commit.committed_per_cycle::0 333030107 40.36% 40.36% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::1 193187610 23.42% 63.78% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::2 63292581 7.67% 71.45% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::3 92556987 11.22% 82.67% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::4 24936073 3.02% 85.69% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::5 27503514 3.33% 89.03% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::6 9360719 1.13% 90.16% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::7 11372840 1.38% 91.54% # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::8 69813614 8.46% 100.00% # Number of insts commited each cycle |
| 553system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 554system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 555system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 552system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 553system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 554system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 556system.cpu.commit.committed_per_cycle::total 825003202 # Number of insts commited each cycle | 555system.cpu.commit.committed_per_cycle::total 825054045 # Number of insts commited each cycle |
| 557system.cpu.commit.committedInsts 826877109 # Number of instructions committed 558system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 559system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 560system.cpu.commit.refs 533262343 # Number of memory references committed 561system.cpu.commit.loads 384102157 # Number of loads committed 562system.cpu.commit.membars 0 # Number of memory barriers committed 563system.cpu.commit.branches 149758583 # Number of branches committed 564system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 565system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. 566system.cpu.commit.function_calls 17673145 # Number of function calls committed. | 556system.cpu.commit.committedInsts 826877109 # Number of instructions committed 557system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 558system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 559system.cpu.commit.refs 533262343 # Number of memory references committed 560system.cpu.commit.loads 384102157 # Number of loads committed 561system.cpu.commit.membars 0 # Number of memory barriers committed 562system.cpu.commit.branches 149758583 # Number of branches committed 563system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 564system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. 565system.cpu.commit.function_calls 17673145 # Number of function calls committed. |
| 567system.cpu.commit.bw_lim_events 69826646 # number cycles where commit BW limit reached | 566system.cpu.commit.bw_lim_events 69813614 # number cycles where commit BW limit reached |
| 568system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 567system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 569system.cpu.rob.rob_reads 2730666717 # The number of ROB reads 570system.cpu.rob.rob_writes 4012080782 # The number of ROB writes 571system.cpu.timesIdled 3354849 # Number of times that the entire CPU went into an idle state and unscheduled itself 572system.cpu.idleCycles 32431331 # Total number of cycles that the CPU has spent unscheduled due to idling | 568system.cpu.rob.rob_reads 2730639165 # The number of ROB reads 569system.cpu.rob.rob_writes 4011880242 # The number of ROB writes 570system.cpu.timesIdled 3355901 # Number of times that the entire CPU went into an idle state and unscheduled itself 571system.cpu.idleCycles 32423466 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 573system.cpu.committedInsts 826877109 # Number of Instructions Simulated 574system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 575system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated | 572system.cpu.committedInsts 826877109 # Number of Instructions Simulated 573system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 574system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated |
| 576system.cpu.cpi 1.110652 # CPI: Cycles Per Instruction 577system.cpu.cpi_total 1.110652 # CPI: Total CPI of All Threads 578system.cpu.ipc 0.900372 # IPC: Instructions Per Cycle 579system.cpu.ipc_total 0.900372 # IPC: Total IPC of All Threads 580system.cpu.int_regfile_reads 2716202384 # number of integer regfile reads 581system.cpu.int_regfile_writes 1420402354 # number of integer regfile writes 582system.cpu.fp_regfile_reads 3547 # number of floating regfile reads 583system.cpu.fp_regfile_writes 23 # number of floating regfile writes 584system.cpu.cc_regfile_reads 597198676 # number of cc regfile reads 585system.cpu.cc_regfile_writes 405403172 # number of cc regfile writes 586system.cpu.misc_regfile_reads 964659775 # number of misc regfile reads | 575system.cpu.cpi 1.110683 # CPI: Cycles Per Instruction 576system.cpu.cpi_total 1.110683 # CPI: Total CPI of All Threads 577system.cpu.ipc 0.900347 # IPC: Instructions Per Cycle 578system.cpu.ipc_total 0.900347 # IPC: Total IPC of All Threads 579system.cpu.int_regfile_reads 2716194969 # number of integer regfile reads 580system.cpu.int_regfile_writes 1420370160 # number of integer regfile writes 581system.cpu.fp_regfile_reads 3538 # number of floating regfile reads 582system.cpu.fp_regfile_writes 76 # number of floating regfile writes 583system.cpu.cc_regfile_reads 597194910 # number of cc regfile reads 584system.cpu.cc_regfile_writes 405402169 # number of cc regfile writes 585system.cpu.misc_regfile_reads 964642327 # number of misc regfile reads |
| 587system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 586system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 588system.cpu.toL2Bus.throughput 697995780 # Throughput (bytes/s) 589system.cpu.toL2Bus.trans_dist::ReadReq 1904573 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::ReadResp 1904572 # Transaction distribution | 587system.cpu.toL2Bus.throughput 698022201 # Throughput (bytes/s) 588system.cpu.toL2Bus.trans_dist::ReadReq 1904986 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::ReadResp 1904985 # Transaction distribution |
| 591system.cpu.toL2Bus.trans_dist::Writeback 2330749 # Transaction distribution | 590system.cpu.toL2Bus.trans_dist::Writeback 2330749 # Transaction distribution |
| 592system.cpu.toL2Bus.trans_dist::UpgradeReq 135378 # Transaction distribution 593system.cpu.toL2Bus.trans_dist::UpgradeResp 135378 # Transaction distribution 594system.cpu.toL2Bus.trans_dist::ReadExReq 771770 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::ReadExResp 771770 # Transaction distribution 596system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 149099 # Packet count per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7669617 # Packet count per connected master and slave (bytes) 598system.cpu.toL2Bus.pkt_count::total 7818716 # Packet count per connected master and slave (bytes) 599system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 435968 # Cumulative packet size per connected master and slave (bytes) 600system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311347520 # Cumulative packet size per connected master and slave (bytes) 601system.cpu.toL2Bus.tot_pkt_size::total 311783488 # Cumulative packet size per connected master and slave (bytes) 602system.cpu.toL2Bus.data_through_bus 311783488 # Total data (bytes) 603system.cpu.toL2Bus.snoop_data_through_bus 8670336 # Total snoop data (bytes) 604system.cpu.toL2Bus.reqLayer0.occupancy 4905098758 # Layer occupancy (ticks) | 591system.cpu.toL2Bus.trans_dist::UpgradeReq 135709 # Transaction distribution 592system.cpu.toL2Bus.trans_dist::UpgradeResp 135709 # Transaction distribution 593system.cpu.toL2Bus.trans_dist::ReadExReq 771688 # Transaction distribution 594system.cpu.toL2Bus.trans_dist::ReadExResp 771688 # Transaction distribution 595system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 149463 # Packet count per connected master and slave (bytes) 596system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7670245 # Packet count per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_count::total 7819708 # Packet count per connected master and slave (bytes) 598system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 436992 # Cumulative packet size per connected master and slave (bytes) 599system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311346432 # Cumulative packet size per connected master and slave (bytes) 600system.cpu.toL2Bus.tot_pkt_size::total 311783424 # Cumulative packet size per connected master and slave (bytes) 601system.cpu.toL2Bus.data_through_bus 311783424 # Total data (bytes) 602system.cpu.toL2Bus.snoop_data_through_bus 8691584 # Total snoop data (bytes) 603system.cpu.toL2Bus.reqLayer0.occupancy 4905579957 # Layer occupancy (ticks) |
| 605system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) | 604system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 606system.cpu.toL2Bus.respLayer0.occupancy 213898487 # Layer occupancy (ticks) | 605system.cpu.toL2Bus.respLayer0.occupancy 214416742 # Layer occupancy (ticks) |
| 607system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 606system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 608system.cpu.toL2Bus.respLayer1.occupancy 3952694158 # Layer occupancy (ticks) | 607system.cpu.toL2Bus.respLayer1.occupancy 3952860716 # Layer occupancy (ticks) |
| 609system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) | 608system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 610system.cpu.icache.tags.replacements 5304 # number of replacements 611system.cpu.icache.tags.tagsinuse 1036.579952 # Cycle average of tags in use 612system.cpu.icache.tags.total_refs 161882998 # Total number of references to valid blocks. 613system.cpu.icache.tags.sampled_refs 6874 # Sample count of references to valid blocks. 614system.cpu.icache.tags.avg_refs 23550.043352 # Average number of references to valid blocks. | 609system.cpu.icache.tags.replacements 5299 # number of replacements 610system.cpu.icache.tags.tagsinuse 1035.961197 # Cycle average of tags in use 611system.cpu.icache.tags.total_refs 161868793 # Total number of references to valid blocks. 612system.cpu.icache.tags.sampled_refs 6888 # Sample count of references to valid blocks. 613system.cpu.icache.tags.avg_refs 23500.115128 # Average number of references to valid blocks. |
| 615system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 614system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 616system.cpu.icache.tags.occ_blocks::cpu.inst 1036.579952 # Average occupied blocks per requestor 617system.cpu.icache.tags.occ_percent::cpu.inst 0.506143 # Average percentage of cache occupancy 618system.cpu.icache.tags.occ_percent::total 0.506143 # Average percentage of cache occupancy 619system.cpu.icache.tags.occ_task_id_blocks::1024 1570 # Occupied blocks per task id 620system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id | 615system.cpu.icache.tags.occ_blocks::cpu.inst 1035.961197 # Average occupied blocks per requestor 616system.cpu.icache.tags.occ_percent::cpu.inst 0.505840 # Average percentage of cache occupancy 617system.cpu.icache.tags.occ_percent::total 0.505840 # Average percentage of cache occupancy 618system.cpu.icache.tags.occ_task_id_blocks::1024 1589 # Occupied blocks per task id 619system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id |
| 621system.cpu.icache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id | 620system.cpu.icache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id |
| 622system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::3 248 # Occupied blocks per task id 624system.cpu.icache.tags.age_task_id_blocks_1024::4 1211 # Occupied blocks per task id 625system.cpu.icache.tags.occ_task_id_percent::1024 0.766602 # Percentage of cache occupancy per task id 626system.cpu.icache.tags.tag_accesses 324200798 # Number of tag accesses 627system.cpu.icache.tags.data_accesses 324200798 # Number of data accesses 628system.cpu.icache.ReadReq_hits::cpu.inst 161884991 # number of ReadReq hits 629system.cpu.icache.ReadReq_hits::total 161884991 # number of ReadReq hits 630system.cpu.icache.demand_hits::cpu.inst 161884991 # number of demand (read+write) hits 631system.cpu.icache.demand_hits::total 161884991 # number of demand (read+write) hits 632system.cpu.icache.overall_hits::cpu.inst 161884991 # number of overall hits 633system.cpu.icache.overall_hits::total 161884991 # number of overall hits 634system.cpu.icache.ReadReq_misses::cpu.inst 144265 # number of ReadReq misses 635system.cpu.icache.ReadReq_misses::total 144265 # number of ReadReq misses 636system.cpu.icache.demand_misses::cpu.inst 144265 # number of demand (read+write) misses 637system.cpu.icache.demand_misses::total 144265 # number of demand (read+write) misses 638system.cpu.icache.overall_misses::cpu.inst 144265 # number of overall misses 639system.cpu.icache.overall_misses::total 144265 # number of overall misses 640system.cpu.icache.ReadReq_miss_latency::cpu.inst 939571727 # number of ReadReq miss cycles 641system.cpu.icache.ReadReq_miss_latency::total 939571727 # number of ReadReq miss cycles 642system.cpu.icache.demand_miss_latency::cpu.inst 939571727 # number of demand (read+write) miss cycles 643system.cpu.icache.demand_miss_latency::total 939571727 # number of demand (read+write) miss cycles 644system.cpu.icache.overall_miss_latency::cpu.inst 939571727 # number of overall miss cycles 645system.cpu.icache.overall_miss_latency::total 939571727 # number of overall miss cycles 646system.cpu.icache.ReadReq_accesses::cpu.inst 162029256 # number of ReadReq accesses(hits+misses) 647system.cpu.icache.ReadReq_accesses::total 162029256 # number of ReadReq accesses(hits+misses) 648system.cpu.icache.demand_accesses::cpu.inst 162029256 # number of demand (read+write) accesses 649system.cpu.icache.demand_accesses::total 162029256 # number of demand (read+write) accesses 650system.cpu.icache.overall_accesses::cpu.inst 162029256 # number of overall (read+write) accesses 651system.cpu.icache.overall_accesses::total 162029256 # number of overall (read+write) accesses 652system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000890 # miss rate for ReadReq accesses 653system.cpu.icache.ReadReq_miss_rate::total 0.000890 # miss rate for ReadReq accesses 654system.cpu.icache.demand_miss_rate::cpu.inst 0.000890 # miss rate for demand accesses 655system.cpu.icache.demand_miss_rate::total 0.000890 # miss rate for demand accesses 656system.cpu.icache.overall_miss_rate::cpu.inst 0.000890 # miss rate for overall accesses 657system.cpu.icache.overall_miss_rate::total 0.000890 # miss rate for overall accesses 658system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6512.818265 # average ReadReq miss latency 659system.cpu.icache.ReadReq_avg_miss_latency::total 6512.818265 # average ReadReq miss latency 660system.cpu.icache.demand_avg_miss_latency::cpu.inst 6512.818265 # average overall miss latency 661system.cpu.icache.demand_avg_miss_latency::total 6512.818265 # average overall miss latency 662system.cpu.icache.overall_avg_miss_latency::cpu.inst 6512.818265 # average overall miss latency 663system.cpu.icache.overall_avg_miss_latency::total 6512.818265 # average overall miss latency 664system.cpu.icache.blocked_cycles::no_mshrs 329 # number of cycles access was blocked | 621system.cpu.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 622system.cpu.icache.tags.age_task_id_blocks_1024::3 245 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::4 1238 # Occupied blocks per task id 624system.cpu.icache.tags.occ_task_id_percent::1024 0.775879 # Percentage of cache occupancy per task id 625system.cpu.icache.tags.tag_accesses 324173234 # Number of tag accesses 626system.cpu.icache.tags.data_accesses 324173234 # Number of data accesses 627system.cpu.icache.ReadReq_hits::cpu.inst 161870665 # number of ReadReq hits 628system.cpu.icache.ReadReq_hits::total 161870665 # number of ReadReq hits 629system.cpu.icache.demand_hits::cpu.inst 161870665 # number of demand (read+write) hits 630system.cpu.icache.demand_hits::total 161870665 # number of demand (read+write) hits 631system.cpu.icache.overall_hits::cpu.inst 161870665 # number of overall hits 632system.cpu.icache.overall_hits::total 161870665 # number of overall hits 633system.cpu.icache.ReadReq_misses::cpu.inst 144635 # number of ReadReq misses 634system.cpu.icache.ReadReq_misses::total 144635 # number of ReadReq misses 635system.cpu.icache.demand_misses::cpu.inst 144635 # number of demand (read+write) misses 636system.cpu.icache.demand_misses::total 144635 # number of demand (read+write) misses 637system.cpu.icache.overall_misses::cpu.inst 144635 # number of overall misses 638system.cpu.icache.overall_misses::total 144635 # number of overall misses 639system.cpu.icache.ReadReq_miss_latency::cpu.inst 939845985 # number of ReadReq miss cycles 640system.cpu.icache.ReadReq_miss_latency::total 939845985 # number of ReadReq miss cycles 641system.cpu.icache.demand_miss_latency::cpu.inst 939845985 # number of demand (read+write) miss cycles 642system.cpu.icache.demand_miss_latency::total 939845985 # number of demand (read+write) miss cycles 643system.cpu.icache.overall_miss_latency::cpu.inst 939845985 # number of overall miss cycles 644system.cpu.icache.overall_miss_latency::total 939845985 # number of overall miss cycles 645system.cpu.icache.ReadReq_accesses::cpu.inst 162015300 # number of ReadReq accesses(hits+misses) 646system.cpu.icache.ReadReq_accesses::total 162015300 # number of ReadReq accesses(hits+misses) 647system.cpu.icache.demand_accesses::cpu.inst 162015300 # number of demand (read+write) accesses 648system.cpu.icache.demand_accesses::total 162015300 # number of demand (read+write) accesses 649system.cpu.icache.overall_accesses::cpu.inst 162015300 # number of overall (read+write) accesses 650system.cpu.icache.overall_accesses::total 162015300 # number of overall (read+write) accesses 651system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000893 # miss rate for ReadReq accesses 652system.cpu.icache.ReadReq_miss_rate::total 0.000893 # miss rate for ReadReq accesses 653system.cpu.icache.demand_miss_rate::cpu.inst 0.000893 # miss rate for demand accesses 654system.cpu.icache.demand_miss_rate::total 0.000893 # miss rate for demand accesses 655system.cpu.icache.overall_miss_rate::cpu.inst 0.000893 # miss rate for overall accesses 656system.cpu.icache.overall_miss_rate::total 0.000893 # miss rate for overall accesses 657system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6498.053618 # average ReadReq miss latency 658system.cpu.icache.ReadReq_avg_miss_latency::total 6498.053618 # average ReadReq miss latency 659system.cpu.icache.demand_avg_miss_latency::cpu.inst 6498.053618 # average overall miss latency 660system.cpu.icache.demand_avg_miss_latency::total 6498.053618 # average overall miss latency 661system.cpu.icache.overall_avg_miss_latency::cpu.inst 6498.053618 # average overall miss latency 662system.cpu.icache.overall_avg_miss_latency::total 6498.053618 # average overall miss latency 663system.cpu.icache.blocked_cycles::no_mshrs 251 # number of cycles access was blocked |
| 665system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 664system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 666system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked | 665system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked |
| 667system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 666system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 668system.cpu.icache.avg_blocked_cycles::no_mshrs 41.125000 # average number of cycles each access was blocked | 667system.cpu.icache.avg_blocked_cycles::no_mshrs 41.833333 # average number of cycles each access was blocked |
| 669system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 670system.cpu.icache.fast_writes 0 # number of fast writes performed 671system.cpu.icache.cache_copies 0 # number of cache copies performed | 668system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.cpu.icache.fast_writes 0 # number of fast writes performed 670system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 672system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1978 # number of ReadReq MSHR hits 673system.cpu.icache.ReadReq_mshr_hits::total 1978 # number of ReadReq MSHR hits 674system.cpu.icache.demand_mshr_hits::cpu.inst 1978 # number of demand (read+write) MSHR hits 675system.cpu.icache.demand_mshr_hits::total 1978 # number of demand (read+write) MSHR hits 676system.cpu.icache.overall_mshr_hits::cpu.inst 1978 # number of overall MSHR hits 677system.cpu.icache.overall_mshr_hits::total 1978 # number of overall MSHR hits 678system.cpu.icache.ReadReq_mshr_misses::cpu.inst 142287 # number of ReadReq MSHR misses 679system.cpu.icache.ReadReq_mshr_misses::total 142287 # number of ReadReq MSHR misses 680system.cpu.icache.demand_mshr_misses::cpu.inst 142287 # number of demand (read+write) MSHR misses 681system.cpu.icache.demand_mshr_misses::total 142287 # number of demand (read+write) MSHR misses 682system.cpu.icache.overall_mshr_misses::cpu.inst 142287 # number of overall MSHR misses 683system.cpu.icache.overall_mshr_misses::total 142287 # number of overall MSHR misses 684system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558890013 # number of ReadReq MSHR miss cycles 685system.cpu.icache.ReadReq_mshr_miss_latency::total 558890013 # number of ReadReq MSHR miss cycles 686system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558890013 # number of demand (read+write) MSHR miss cycles 687system.cpu.icache.demand_mshr_miss_latency::total 558890013 # number of demand (read+write) MSHR miss cycles 688system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558890013 # number of overall MSHR miss cycles 689system.cpu.icache.overall_mshr_miss_latency::total 558890013 # number of overall MSHR miss cycles 690system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000878 # mshr miss rate for ReadReq accesses 691system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000878 # mshr miss rate for ReadReq accesses 692system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000878 # mshr miss rate for demand accesses 693system.cpu.icache.demand_mshr_miss_rate::total 0.000878 # mshr miss rate for demand accesses 694system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000878 # mshr miss rate for overall accesses 695system.cpu.icache.overall_mshr_miss_rate::total 0.000878 # mshr miss rate for overall accesses 696system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3927.906365 # average ReadReq mshr miss latency 697system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3927.906365 # average ReadReq mshr miss latency 698system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3927.906365 # average overall mshr miss latency 699system.cpu.icache.demand_avg_mshr_miss_latency::total 3927.906365 # average overall mshr miss latency 700system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3927.906365 # average overall mshr miss latency 701system.cpu.icache.overall_avg_mshr_miss_latency::total 3927.906365 # average overall mshr miss latency | 671system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2000 # number of ReadReq MSHR hits 672system.cpu.icache.ReadReq_mshr_hits::total 2000 # number of ReadReq MSHR hits 673system.cpu.icache.demand_mshr_hits::cpu.inst 2000 # number of demand (read+write) MSHR hits 674system.cpu.icache.demand_mshr_hits::total 2000 # number of demand (read+write) MSHR hits 675system.cpu.icache.overall_mshr_hits::cpu.inst 2000 # number of overall MSHR hits 676system.cpu.icache.overall_mshr_hits::total 2000 # number of overall MSHR hits 677system.cpu.icache.ReadReq_mshr_misses::cpu.inst 142635 # number of ReadReq MSHR misses 678system.cpu.icache.ReadReq_mshr_misses::total 142635 # number of ReadReq MSHR misses 679system.cpu.icache.demand_mshr_misses::cpu.inst 142635 # number of demand (read+write) MSHR misses 680system.cpu.icache.demand_mshr_misses::total 142635 # number of demand (read+write) MSHR misses 681system.cpu.icache.overall_mshr_misses::cpu.inst 142635 # number of overall MSHR misses 682system.cpu.icache.overall_mshr_misses::total 142635 # number of overall MSHR misses 683system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558603007 # number of ReadReq MSHR miss cycles 684system.cpu.icache.ReadReq_mshr_miss_latency::total 558603007 # number of ReadReq MSHR miss cycles 685system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558603007 # number of demand (read+write) MSHR miss cycles 686system.cpu.icache.demand_mshr_miss_latency::total 558603007 # number of demand (read+write) MSHR miss cycles 687system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558603007 # number of overall MSHR miss cycles 688system.cpu.icache.overall_mshr_miss_latency::total 558603007 # number of overall MSHR miss cycles 689system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for ReadReq accesses 690system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000880 # mshr miss rate for ReadReq accesses 691system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for demand accesses 692system.cpu.icache.demand_mshr_miss_rate::total 0.000880 # mshr miss rate for demand accesses 693system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for overall accesses 694system.cpu.icache.overall_mshr_miss_rate::total 0.000880 # mshr miss rate for overall accesses 695system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3916.310912 # average ReadReq mshr miss latency 696system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3916.310912 # average ReadReq mshr miss latency 697system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3916.310912 # average overall mshr miss latency 698system.cpu.icache.demand_avg_mshr_miss_latency::total 3916.310912 # average overall mshr miss latency 699system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3916.310912 # average overall mshr miss latency 700system.cpu.icache.overall_avg_mshr_miss_latency::total 3916.310912 # average overall mshr miss latency |
| 702system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 701system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 703system.cpu.l2cache.tags.replacements 352852 # number of replacements 704system.cpu.l2cache.tags.tagsinuse 29667.815296 # Cycle average of tags in use 705system.cpu.l2cache.tags.total_refs 3696724 # Total number of references to valid blocks. 706system.cpu.l2cache.tags.sampled_refs 385211 # Sample count of references to valid blocks. 707system.cpu.l2cache.tags.avg_refs 9.596621 # Average number of references to valid blocks. | 702system.cpu.l2cache.tags.replacements 352851 # number of replacements 703system.cpu.l2cache.tags.tagsinuse 29668.075307 # Cycle average of tags in use 704system.cpu.l2cache.tags.total_refs 3697142 # Total number of references to valid blocks. 705system.cpu.l2cache.tags.sampled_refs 385214 # Sample count of references to valid blocks. 706system.cpu.l2cache.tags.avg_refs 9.597631 # Average number of references to valid blocks. |
| 708system.cpu.l2cache.tags.warmup_cycle 199249645000 # Cycle when the warmup percentage was hit. | 707system.cpu.l2cache.tags.warmup_cycle 199249645000 # Cycle when the warmup percentage was hit. |
| 709system.cpu.l2cache.tags.occ_blocks::writebacks 21119.878039 # Average occupied blocks per requestor 710system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.140988 # Average occupied blocks per requestor 711system.cpu.l2cache.tags.occ_blocks::cpu.data 8324.796269 # Average occupied blocks per requestor 712system.cpu.l2cache.tags.occ_percent::writebacks 0.644528 # Average percentage of cache occupancy 713system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006810 # Average percentage of cache occupancy 714system.cpu.l2cache.tags.occ_percent::cpu.data 0.254053 # Average percentage of cache occupancy 715system.cpu.l2cache.tags.occ_percent::total 0.905390 # Average percentage of cache occupancy 716system.cpu.l2cache.tags.occ_task_id_blocks::1024 32359 # Occupied blocks per task id 717system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 718system.cpu.l2cache.tags.age_task_id_blocks_1024::2 241 # Occupied blocks per task id | 708system.cpu.l2cache.tags.occ_blocks::writebacks 21122.585790 # Average occupied blocks per requestor 709system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.642071 # Average occupied blocks per requestor 710system.cpu.l2cache.tags.occ_blocks::cpu.data 8321.847447 # Average occupied blocks per requestor 711system.cpu.l2cache.tags.occ_percent::writebacks 0.644610 # Average percentage of cache occupancy 712system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006825 # Average percentage of cache occupancy 713system.cpu.l2cache.tags.occ_percent::cpu.data 0.253963 # Average percentage of cache occupancy 714system.cpu.l2cache.tags.occ_percent::total 0.905398 # Average percentage of cache occupancy 715system.cpu.l2cache.tags.occ_task_id_blocks::1024 32363 # Occupied blocks per task id 716system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 717system.cpu.l2cache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id |
| 719system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11704 # Occupied blocks per task id | 718system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11704 # Occupied blocks per task id |
| 720system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20331 # Occupied blocks per task id 721system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987518 # Percentage of cache occupancy per task id 722system.cpu.l2cache.tags.tag_accesses 41214649 # Number of tag accesses 723system.cpu.l2cache.tags.data_accesses 41214649 # Number of data accesses 724system.cpu.l2cache.ReadReq_hits::cpu.inst 3652 # number of ReadReq hits 725system.cpu.l2cache.ReadReq_hits::cpu.data 1586740 # number of ReadReq hits 726system.cpu.l2cache.ReadReq_hits::total 1590392 # number of ReadReq hits | 719system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20343 # Occupied blocks per task id 720system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987640 # Percentage of cache occupancy per task id 721system.cpu.l2cache.tags.tag_accesses 41217237 # Number of tag accesses 722system.cpu.l2cache.tags.data_accesses 41217237 # Number of data accesses 723system.cpu.l2cache.ReadReq_hits::cpu.inst 3670 # number of ReadReq hits 724system.cpu.l2cache.ReadReq_hits::cpu.data 1586809 # number of ReadReq hits 725system.cpu.l2cache.ReadReq_hits::total 1590479 # number of ReadReq hits |
| 727system.cpu.l2cache.Writeback_hits::writebacks 2330749 # number of Writeback hits 728system.cpu.l2cache.Writeback_hits::total 2330749 # number of Writeback hits | 726system.cpu.l2cache.Writeback_hits::writebacks 2330749 # number of Writeback hits 727system.cpu.l2cache.Writeback_hits::total 2330749 # number of Writeback hits |
| 729system.cpu.l2cache.UpgradeReq_hits::cpu.data 1423 # number of UpgradeReq hits 730system.cpu.l2cache.UpgradeReq_hits::total 1423 # number of UpgradeReq hits 731system.cpu.l2cache.ReadExReq_hits::cpu.data 564917 # number of ReadExReq hits 732system.cpu.l2cache.ReadExReq_hits::total 564917 # number of ReadExReq hits 733system.cpu.l2cache.demand_hits::cpu.inst 3652 # number of demand (read+write) hits 734system.cpu.l2cache.demand_hits::cpu.data 2151657 # number of demand (read+write) hits 735system.cpu.l2cache.demand_hits::total 2155309 # number of demand (read+write) hits 736system.cpu.l2cache.overall_hits::cpu.inst 3652 # number of overall hits 737system.cpu.l2cache.overall_hits::cpu.data 2151657 # number of overall hits 738system.cpu.l2cache.overall_hits::total 2155309 # number of overall hits 739system.cpu.l2cache.ReadReq_misses::cpu.inst 3161 # number of ReadReq misses 740system.cpu.l2cache.ReadReq_misses::cpu.data 175546 # number of ReadReq misses 741system.cpu.l2cache.ReadReq_misses::total 178707 # number of ReadReq misses 742system.cpu.l2cache.UpgradeReq_misses::cpu.data 133955 # number of UpgradeReq misses 743system.cpu.l2cache.UpgradeReq_misses::total 133955 # number of UpgradeReq misses 744system.cpu.l2cache.ReadExReq_misses::cpu.data 206853 # number of ReadExReq misses 745system.cpu.l2cache.ReadExReq_misses::total 206853 # number of ReadExReq misses 746system.cpu.l2cache.demand_misses::cpu.inst 3161 # number of demand (read+write) misses | 728system.cpu.l2cache.UpgradeReq_hits::cpu.data 1446 # number of UpgradeReq hits 729system.cpu.l2cache.UpgradeReq_hits::total 1446 # number of UpgradeReq hits 730system.cpu.l2cache.ReadExReq_hits::cpu.data 564831 # number of ReadExReq hits 731system.cpu.l2cache.ReadExReq_hits::total 564831 # number of ReadExReq hits 732system.cpu.l2cache.demand_hits::cpu.inst 3670 # number of demand (read+write) hits 733system.cpu.l2cache.demand_hits::cpu.data 2151640 # number of demand (read+write) hits 734system.cpu.l2cache.demand_hits::total 2155310 # number of demand (read+write) hits 735system.cpu.l2cache.overall_hits::cpu.inst 3670 # number of overall hits 736system.cpu.l2cache.overall_hits::cpu.data 2151640 # number of overall hits 737system.cpu.l2cache.overall_hits::total 2155310 # number of overall hits 738system.cpu.l2cache.ReadReq_misses::cpu.inst 3159 # number of ReadReq misses 739system.cpu.l2cache.ReadReq_misses::cpu.data 175542 # number of ReadReq misses 740system.cpu.l2cache.ReadReq_misses::total 178701 # number of ReadReq misses 741system.cpu.l2cache.UpgradeReq_misses::cpu.data 134263 # number of UpgradeReq misses 742system.cpu.l2cache.UpgradeReq_misses::total 134263 # number of UpgradeReq misses 743system.cpu.l2cache.ReadExReq_misses::cpu.data 206857 # number of ReadExReq misses 744system.cpu.l2cache.ReadExReq_misses::total 206857 # number of ReadExReq misses 745system.cpu.l2cache.demand_misses::cpu.inst 3159 # number of demand (read+write) misses |
| 747system.cpu.l2cache.demand_misses::cpu.data 382399 # number of demand (read+write) misses | 746system.cpu.l2cache.demand_misses::cpu.data 382399 # number of demand (read+write) misses |
| 748system.cpu.l2cache.demand_misses::total 385560 # number of demand (read+write) misses 749system.cpu.l2cache.overall_misses::cpu.inst 3161 # number of overall misses | 747system.cpu.l2cache.demand_misses::total 385558 # number of demand (read+write) misses 748system.cpu.l2cache.overall_misses::cpu.inst 3159 # number of overall misses |
| 750system.cpu.l2cache.overall_misses::cpu.data 382399 # number of overall misses | 749system.cpu.l2cache.overall_misses::cpu.data 382399 # number of overall misses |
| 751system.cpu.l2cache.overall_misses::total 385560 # number of overall misses 752system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 241484750 # number of ReadReq miss cycles 753system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13186181960 # number of ReadReq miss cycles 754system.cpu.l2cache.ReadReq_miss_latency::total 13427666710 # number of ReadReq miss cycles 755system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6452723 # number of UpgradeReq miss cycles 756system.cpu.l2cache.UpgradeReq_miss_latency::total 6452723 # number of UpgradeReq miss cycles 757system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15146167475 # number of ReadExReq miss cycles 758system.cpu.l2cache.ReadExReq_miss_latency::total 15146167475 # number of ReadExReq miss cycles 759system.cpu.l2cache.demand_miss_latency::cpu.inst 241484750 # number of demand (read+write) miss cycles 760system.cpu.l2cache.demand_miss_latency::cpu.data 28332349435 # number of demand (read+write) miss cycles 761system.cpu.l2cache.demand_miss_latency::total 28573834185 # number of demand (read+write) miss cycles 762system.cpu.l2cache.overall_miss_latency::cpu.inst 241484750 # number of overall miss cycles 763system.cpu.l2cache.overall_miss_latency::cpu.data 28332349435 # number of overall miss cycles 764system.cpu.l2cache.overall_miss_latency::total 28573834185 # number of overall miss cycles 765system.cpu.l2cache.ReadReq_accesses::cpu.inst 6813 # number of ReadReq accesses(hits+misses) 766system.cpu.l2cache.ReadReq_accesses::cpu.data 1762286 # number of ReadReq accesses(hits+misses) 767system.cpu.l2cache.ReadReq_accesses::total 1769099 # number of ReadReq accesses(hits+misses) | 750system.cpu.l2cache.overall_misses::total 385558 # number of overall misses 751system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240297250 # number of ReadReq miss cycles 752system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13188147460 # number of ReadReq miss cycles 753system.cpu.l2cache.ReadReq_miss_latency::total 13428444710 # number of ReadReq miss cycles 754system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6534219 # number of UpgradeReq miss cycles 755system.cpu.l2cache.UpgradeReq_miss_latency::total 6534219 # number of UpgradeReq miss cycles 756system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15150269977 # number of ReadExReq miss cycles 757system.cpu.l2cache.ReadExReq_miss_latency::total 15150269977 # number of ReadExReq miss cycles 758system.cpu.l2cache.demand_miss_latency::cpu.inst 240297250 # number of demand (read+write) miss cycles 759system.cpu.l2cache.demand_miss_latency::cpu.data 28338417437 # number of demand (read+write) miss cycles 760system.cpu.l2cache.demand_miss_latency::total 28578714687 # number of demand (read+write) miss cycles 761system.cpu.l2cache.overall_miss_latency::cpu.inst 240297250 # number of overall miss cycles 762system.cpu.l2cache.overall_miss_latency::cpu.data 28338417437 # number of overall miss cycles 763system.cpu.l2cache.overall_miss_latency::total 28578714687 # number of overall miss cycles 764system.cpu.l2cache.ReadReq_accesses::cpu.inst 6829 # number of ReadReq accesses(hits+misses) 765system.cpu.l2cache.ReadReq_accesses::cpu.data 1762351 # number of ReadReq accesses(hits+misses) 766system.cpu.l2cache.ReadReq_accesses::total 1769180 # number of ReadReq accesses(hits+misses) |
| 768system.cpu.l2cache.Writeback_accesses::writebacks 2330749 # number of Writeback accesses(hits+misses) 769system.cpu.l2cache.Writeback_accesses::total 2330749 # number of Writeback accesses(hits+misses) | 767system.cpu.l2cache.Writeback_accesses::writebacks 2330749 # number of Writeback accesses(hits+misses) 768system.cpu.l2cache.Writeback_accesses::total 2330749 # number of Writeback accesses(hits+misses) |
| 770system.cpu.l2cache.UpgradeReq_accesses::cpu.data 135378 # number of UpgradeReq accesses(hits+misses) 771system.cpu.l2cache.UpgradeReq_accesses::total 135378 # number of UpgradeReq accesses(hits+misses) 772system.cpu.l2cache.ReadExReq_accesses::cpu.data 771770 # number of ReadExReq accesses(hits+misses) 773system.cpu.l2cache.ReadExReq_accesses::total 771770 # number of ReadExReq accesses(hits+misses) 774system.cpu.l2cache.demand_accesses::cpu.inst 6813 # number of demand (read+write) accesses 775system.cpu.l2cache.demand_accesses::cpu.data 2534056 # number of demand (read+write) accesses 776system.cpu.l2cache.demand_accesses::total 2540869 # number of demand (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.inst 6813 # number of overall (read+write) accesses 778system.cpu.l2cache.overall_accesses::cpu.data 2534056 # number of overall (read+write) accesses 779system.cpu.l2cache.overall_accesses::total 2540869 # number of overall (read+write) accesses 780system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463966 # miss rate for ReadReq accesses 781system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099613 # miss rate for ReadReq accesses 782system.cpu.l2cache.ReadReq_miss_rate::total 0.101016 # miss rate for ReadReq accesses 783system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989489 # miss rate for UpgradeReq accesses 784system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989489 # miss rate for UpgradeReq accesses 785system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268024 # miss rate for ReadExReq accesses 786system.cpu.l2cache.ReadExReq_miss_rate::total 0.268024 # miss rate for ReadExReq accesses 787system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463966 # miss rate for demand accesses 788system.cpu.l2cache.demand_miss_rate::cpu.data 0.150904 # miss rate for demand accesses | 769system.cpu.l2cache.UpgradeReq_accesses::cpu.data 135709 # number of UpgradeReq accesses(hits+misses) 770system.cpu.l2cache.UpgradeReq_accesses::total 135709 # number of UpgradeReq accesses(hits+misses) 771system.cpu.l2cache.ReadExReq_accesses::cpu.data 771688 # number of ReadExReq accesses(hits+misses) 772system.cpu.l2cache.ReadExReq_accesses::total 771688 # number of ReadExReq accesses(hits+misses) 773system.cpu.l2cache.demand_accesses::cpu.inst 6829 # number of demand (read+write) accesses 774system.cpu.l2cache.demand_accesses::cpu.data 2534039 # number of demand (read+write) accesses 775system.cpu.l2cache.demand_accesses::total 2540868 # number of demand (read+write) accesses 776system.cpu.l2cache.overall_accesses::cpu.inst 6829 # number of overall (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.data 2534039 # number of overall (read+write) accesses 778system.cpu.l2cache.overall_accesses::total 2540868 # number of overall (read+write) accesses 779system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462586 # miss rate for ReadReq accesses 780system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099607 # miss rate for ReadReq accesses 781system.cpu.l2cache.ReadReq_miss_rate::total 0.101008 # miss rate for ReadReq accesses 782system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989345 # miss rate for UpgradeReq accesses 783system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989345 # miss rate for UpgradeReq accesses 784system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268058 # miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_miss_rate::total 0.268058 # miss rate for ReadExReq accesses 786system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462586 # miss rate for demand accesses 787system.cpu.l2cache.demand_miss_rate::cpu.data 0.150905 # miss rate for demand accesses |
| 789system.cpu.l2cache.demand_miss_rate::total 0.151743 # miss rate for demand accesses | 788system.cpu.l2cache.demand_miss_rate::total 0.151743 # miss rate for demand accesses |
| 790system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463966 # miss rate for overall accesses 791system.cpu.l2cache.overall_miss_rate::cpu.data 0.150904 # miss rate for overall accesses | 789system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462586 # miss rate for overall accesses 790system.cpu.l2cache.overall_miss_rate::cpu.data 0.150905 # miss rate for overall accesses |
| 792system.cpu.l2cache.overall_miss_rate::total 0.151743 # miss rate for overall accesses | 791system.cpu.l2cache.overall_miss_rate::total 0.151743 # miss rate for overall accesses |
| 793system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76395.049035 # average ReadReq miss latency 794system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.251615 # average ReadReq miss latency 795system.cpu.l2cache.ReadReq_avg_miss_latency::total 75137.888891 # average ReadReq miss latency 796system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48.170826 # average UpgradeReq miss latency 797system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48.170826 # average UpgradeReq miss latency 798system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73221.889337 # average ReadExReq miss latency 799system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73221.889337 # average ReadExReq miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76395.049035 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74091.065706 # average overall miss latency 802system.cpu.l2cache.demand_avg_miss_latency::total 74109.954832 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76395.049035 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74091.065706 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::total 74109.954832 # average overall miss latency | 792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76067.505540 # average ReadReq miss latency 793system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75128.159985 # average ReadReq miss latency 794system.cpu.l2cache.ReadReq_avg_miss_latency::total 75144.765334 # average ReadReq miss latency 795system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48.667310 # average UpgradeReq miss latency 796system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48.667310 # average UpgradeReq miss latency 797system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73240.305994 # average ReadExReq miss latency 798system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73240.305994 # average ReadExReq miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76067.505540 # average overall miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74106.933954 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::total 74122.997544 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76067.505540 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74106.933954 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::total 74122.997544 # average overall miss latency |
| 806system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.l2cache.fast_writes 0 # number of fast writes performed 813system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 805system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 809system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 811system.cpu.l2cache.fast_writes 0 # number of fast writes performed 812system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 814system.cpu.l2cache.writebacks::writebacks 293571 # number of writebacks 815system.cpu.l2cache.writebacks::total 293571 # number of writebacks 816system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3161 # number of ReadReq MSHR misses 817system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175546 # number of ReadReq MSHR misses 818system.cpu.l2cache.ReadReq_mshr_misses::total 178707 # number of ReadReq MSHR misses 819system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 133955 # number of UpgradeReq MSHR misses 820system.cpu.l2cache.UpgradeReq_mshr_misses::total 133955 # number of UpgradeReq MSHR misses 821system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206853 # number of ReadExReq MSHR misses 822system.cpu.l2cache.ReadExReq_mshr_misses::total 206853 # number of ReadExReq MSHR misses 823system.cpu.l2cache.demand_mshr_misses::cpu.inst 3161 # number of demand (read+write) MSHR misses | 813system.cpu.l2cache.writebacks::writebacks 293551 # number of writebacks 814system.cpu.l2cache.writebacks::total 293551 # number of writebacks 815system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 816system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 817system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 818system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 819system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 820system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 821system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3158 # number of ReadReq MSHR misses 822system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175542 # number of ReadReq MSHR misses 823system.cpu.l2cache.ReadReq_mshr_misses::total 178700 # number of ReadReq MSHR misses 824system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 134263 # number of UpgradeReq MSHR misses 825system.cpu.l2cache.UpgradeReq_mshr_misses::total 134263 # number of UpgradeReq MSHR misses 826system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206857 # number of ReadExReq MSHR misses 827system.cpu.l2cache.ReadExReq_mshr_misses::total 206857 # number of ReadExReq MSHR misses 828system.cpu.l2cache.demand_mshr_misses::cpu.inst 3158 # number of demand (read+write) MSHR misses |
| 824system.cpu.l2cache.demand_mshr_misses::cpu.data 382399 # number of demand (read+write) MSHR misses | 829system.cpu.l2cache.demand_mshr_misses::cpu.data 382399 # number of demand (read+write) MSHR misses |
| 825system.cpu.l2cache.demand_mshr_misses::total 385560 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.overall_mshr_misses::cpu.inst 3161 # number of overall MSHR misses | 830system.cpu.l2cache.demand_mshr_misses::total 385557 # number of demand (read+write) MSHR misses 831system.cpu.l2cache.overall_mshr_misses::cpu.inst 3158 # number of overall MSHR misses |
| 827system.cpu.l2cache.overall_mshr_misses::cpu.data 382399 # number of overall MSHR misses | 832system.cpu.l2cache.overall_mshr_misses::cpu.data 382399 # number of overall MSHR misses |
| 828system.cpu.l2cache.overall_mshr_misses::total 385560 # number of overall MSHR misses 829system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 201970750 # number of ReadReq MSHR miss cycles 830system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10947076960 # number of ReadReq MSHR miss cycles 831system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11149047710 # number of ReadReq MSHR miss cycles 832system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1342825429 # number of UpgradeReq MSHR miss cycles 833system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1342825429 # number of UpgradeReq MSHR miss cycles 834system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12520595025 # number of ReadExReq MSHR miss cycles 835system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12520595025 # number of ReadExReq MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 201970750 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23467671985 # number of demand (read+write) MSHR miss cycles 838system.cpu.l2cache.demand_mshr_miss_latency::total 23669642735 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 201970750 # number of overall MSHR miss cycles 840system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23467671985 # number of overall MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::total 23669642735 # number of overall MSHR miss cycles 842system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463966 # mshr miss rate for ReadReq accesses 843system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099613 # mshr miss rate for ReadReq accesses 844system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101016 # mshr miss rate for ReadReq accesses 845system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989489 # mshr miss rate for UpgradeReq accesses 846system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989489 # mshr miss rate for UpgradeReq accesses 847system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268024 # mshr miss rate for ReadExReq accesses 848system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268024 # mshr miss rate for ReadExReq accesses 849system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463966 # mshr miss rate for demand accesses 850system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150904 # mshr miss rate for demand accesses 851system.cpu.l2cache.demand_mshr_miss_rate::total 0.151743 # mshr miss rate for demand accesses 852system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463966 # mshr miss rate for overall accesses 853system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150904 # mshr miss rate for overall accesses 854system.cpu.l2cache.overall_mshr_miss_rate::total 0.151743 # mshr miss rate for overall accesses 855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63894.574502 # average ReadReq mshr miss latency 856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62360.161781 # average ReadReq mshr miss latency 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62387.302736 # average ReadReq mshr miss latency 858system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.451711 # average UpgradeReq mshr miss latency 859system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.451711 # average UpgradeReq mshr miss latency 860system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60528.950632 # average ReadExReq mshr miss latency 861system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60528.950632 # average ReadExReq mshr miss latency 862system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63894.574502 # average overall mshr miss latency 863system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61369.595593 # average overall mshr miss latency 864system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61390.296543 # average overall mshr miss latency 865system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63894.574502 # average overall mshr miss latency 866system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61369.595593 # average overall mshr miss latency 867system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61390.296543 # average overall mshr miss latency | 833system.cpu.l2cache.overall_mshr_misses::total 385557 # number of overall MSHR misses 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200687250 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10949056460 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11149743710 # number of ReadReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1346042939 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1346042939 # number of UpgradeReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12524505023 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12524505023 # number of ReadExReq MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200687250 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23473561483 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 23674248733 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200687250 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23473561483 # number of overall MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::total 23674248733 # number of overall MSHR miss cycles 847system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462440 # mshr miss rate for ReadReq accesses 848system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099607 # mshr miss rate for ReadReq accesses 849system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101007 # mshr miss rate for ReadReq accesses 850system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989345 # mshr miss rate for UpgradeReq accesses 851system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989345 # mshr miss rate for UpgradeReq accesses 852system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268058 # mshr miss rate for ReadExReq accesses 853system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268058 # mshr miss rate for ReadExReq accesses 854system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462440 # mshr miss rate for demand accesses 855system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150905 # mshr miss rate for demand accesses 856system.cpu.l2cache.demand_mshr_miss_rate::total 0.151742 # mshr miss rate for demand accesses 857system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462440 # mshr miss rate for overall accesses 858system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150905 # mshr miss rate for overall accesses 859system.cpu.l2cache.overall_mshr_miss_rate::total 0.151742 # mshr miss rate for overall accesses 860system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63548.844205 # average ReadReq mshr miss latency 861system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62372.859259 # average ReadReq mshr miss latency 862system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62393.641354 # average ReadReq mshr miss latency 863system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.419803 # average UpgradeReq mshr miss latency 864system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.419803 # average UpgradeReq mshr miss latency 865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60546.682119 # average ReadExReq mshr miss latency 866system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60546.682119 # average ReadExReq mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63548.844205 # average overall mshr miss latency 868system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61384.997040 # average overall mshr miss latency 869system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.720565 # average overall mshr miss latency 870system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63548.844205 # average overall mshr miss latency 871system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61384.997040 # average overall mshr miss latency 872system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.720565 # average overall mshr miss latency |
| 868system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 873system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 869system.cpu.dcache.tags.replacements 2529960 # number of replacements 870system.cpu.dcache.tags.tagsinuse 4088.243311 # Cycle average of tags in use 871system.cpu.dcache.tags.total_refs 395939715 # Total number of references to valid blocks. 872system.cpu.dcache.tags.sampled_refs 2534056 # Sample count of references to valid blocks. 873system.cpu.dcache.tags.avg_refs 156.247421 # Average number of references to valid blocks. | 874system.cpu.dcache.tags.replacements 2529943 # number of replacements 875system.cpu.dcache.tags.tagsinuse 4088.243531 # Cycle average of tags in use 876system.cpu.dcache.tags.total_refs 396026298 # Total number of references to valid blocks. 877system.cpu.dcache.tags.sampled_refs 2534039 # Sample count of references to valid blocks. 878system.cpu.dcache.tags.avg_refs 156.282637 # Average number of references to valid blocks. |
| 874system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. | 879system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. |
| 875system.cpu.dcache.tags.occ_blocks::cpu.data 4088.243311 # Average occupied blocks per requestor | 880system.cpu.dcache.tags.occ_blocks::cpu.data 4088.243531 # Average occupied blocks per requestor |
| 876system.cpu.dcache.tags.occ_percent::cpu.data 0.998106 # Average percentage of cache occupancy 877system.cpu.dcache.tags.occ_percent::total 0.998106 # Average percentage of cache occupancy 878system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 881system.cpu.dcache.tags.occ_percent::cpu.data 0.998106 # Average percentage of cache occupancy 882system.cpu.dcache.tags.occ_percent::total 0.998106 # Average percentage of cache occupancy 883system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 879system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 880system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 881system.cpu.dcache.tags.age_task_id_blocks_1024::2 739 # Occupied blocks per task id 882system.cpu.dcache.tags.age_task_id_blocks_1024::3 3316 # Occupied blocks per task id | 884system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 885system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 886system.cpu.dcache.tags.age_task_id_blocks_1024::2 730 # Occupied blocks per task id 887system.cpu.dcache.tags.age_task_id_blocks_1024::3 3318 # Occupied blocks per task id |
| 883system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 888system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 884system.cpu.dcache.tags.tag_accesses 801001196 # Number of tag accesses 885system.cpu.dcache.tags.data_accesses 801001196 # Number of data accesses 886system.cpu.dcache.ReadReq_hits::cpu.data 247190433 # number of ReadReq hits 887system.cpu.dcache.ReadReq_hits::total 247190433 # number of ReadReq hits 888system.cpu.dcache.WriteReq_hits::cpu.data 148236290 # number of WriteReq hits 889system.cpu.dcache.WriteReq_hits::total 148236290 # number of WriteReq hits 890system.cpu.dcache.demand_hits::cpu.data 395426723 # number of demand (read+write) hits 891system.cpu.dcache.demand_hits::total 395426723 # number of demand (read+write) hits 892system.cpu.dcache.overall_hits::cpu.data 395426723 # number of overall hits 893system.cpu.dcache.overall_hits::total 395426723 # number of overall hits 894system.cpu.dcache.ReadReq_misses::cpu.data 2882935 # number of ReadReq misses 895system.cpu.dcache.ReadReq_misses::total 2882935 # number of ReadReq misses 896system.cpu.dcache.WriteReq_misses::cpu.data 923912 # number of WriteReq misses 897system.cpu.dcache.WriteReq_misses::total 923912 # number of WriteReq misses 898system.cpu.dcache.demand_misses::cpu.data 3806847 # number of demand (read+write) misses 899system.cpu.dcache.demand_misses::total 3806847 # number of demand (read+write) misses 900system.cpu.dcache.overall_misses::cpu.data 3806847 # number of overall misses 901system.cpu.dcache.overall_misses::total 3806847 # number of overall misses 902system.cpu.dcache.ReadReq_miss_latency::cpu.data 58045368359 # number of ReadReq miss cycles 903system.cpu.dcache.ReadReq_miss_latency::total 58045368359 # number of ReadReq miss cycles 904system.cpu.dcache.WriteReq_miss_latency::cpu.data 26823619163 # number of WriteReq miss cycles 905system.cpu.dcache.WriteReq_miss_latency::total 26823619163 # number of WriteReq miss cycles 906system.cpu.dcache.demand_miss_latency::cpu.data 84868987522 # number of demand (read+write) miss cycles 907system.cpu.dcache.demand_miss_latency::total 84868987522 # number of demand (read+write) miss cycles 908system.cpu.dcache.overall_miss_latency::cpu.data 84868987522 # number of overall miss cycles 909system.cpu.dcache.overall_miss_latency::total 84868987522 # number of overall miss cycles 910system.cpu.dcache.ReadReq_accesses::cpu.data 250073368 # number of ReadReq accesses(hits+misses) 911system.cpu.dcache.ReadReq_accesses::total 250073368 # number of ReadReq accesses(hits+misses) | 889system.cpu.dcache.tags.tag_accesses 801176347 # Number of tag accesses 890system.cpu.dcache.tags.data_accesses 801176347 # Number of data accesses 891system.cpu.dcache.ReadReq_hits::cpu.data 247278807 # number of ReadReq hits 892system.cpu.dcache.ReadReq_hits::total 247278807 # number of ReadReq hits 893system.cpu.dcache.WriteReq_hits::cpu.data 148236045 # number of WriteReq hits 894system.cpu.dcache.WriteReq_hits::total 148236045 # number of WriteReq hits 895system.cpu.dcache.demand_hits::cpu.data 395514852 # number of demand (read+write) hits 896system.cpu.dcache.demand_hits::total 395514852 # number of demand (read+write) hits 897system.cpu.dcache.overall_hits::cpu.data 395514852 # number of overall hits 898system.cpu.dcache.overall_hits::total 395514852 # number of overall hits 899system.cpu.dcache.ReadReq_misses::cpu.data 2882145 # number of ReadReq misses 900system.cpu.dcache.ReadReq_misses::total 2882145 # number of ReadReq misses 901system.cpu.dcache.WriteReq_misses::cpu.data 924157 # number of WriteReq misses 902system.cpu.dcache.WriteReq_misses::total 924157 # number of WriteReq misses 903system.cpu.dcache.demand_misses::cpu.data 3806302 # number of demand (read+write) misses 904system.cpu.dcache.demand_misses::total 3806302 # number of demand (read+write) misses 905system.cpu.dcache.overall_misses::cpu.data 3806302 # number of overall misses 906system.cpu.dcache.overall_misses::total 3806302 # number of overall misses 907system.cpu.dcache.ReadReq_miss_latency::cpu.data 58050756258 # number of ReadReq miss cycles 908system.cpu.dcache.ReadReq_miss_latency::total 58050756258 # number of ReadReq miss cycles 909system.cpu.dcache.WriteReq_miss_latency::cpu.data 26834846719 # number of WriteReq miss cycles 910system.cpu.dcache.WriteReq_miss_latency::total 26834846719 # number of WriteReq miss cycles 911system.cpu.dcache.demand_miss_latency::cpu.data 84885602977 # number of demand (read+write) miss cycles 912system.cpu.dcache.demand_miss_latency::total 84885602977 # number of demand (read+write) miss cycles 913system.cpu.dcache.overall_miss_latency::cpu.data 84885602977 # number of overall miss cycles 914system.cpu.dcache.overall_miss_latency::total 84885602977 # number of overall miss cycles 915system.cpu.dcache.ReadReq_accesses::cpu.data 250160952 # number of ReadReq accesses(hits+misses) 916system.cpu.dcache.ReadReq_accesses::total 250160952 # number of ReadReq accesses(hits+misses) |
| 912system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 913system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) | 917system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 918system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) |
| 914system.cpu.dcache.demand_accesses::cpu.data 399233570 # number of demand (read+write) accesses 915system.cpu.dcache.demand_accesses::total 399233570 # number of demand (read+write) accesses 916system.cpu.dcache.overall_accesses::cpu.data 399233570 # number of overall (read+write) accesses 917system.cpu.dcache.overall_accesses::total 399233570 # number of overall (read+write) accesses 918system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011528 # miss rate for ReadReq accesses 919system.cpu.dcache.ReadReq_miss_rate::total 0.011528 # miss rate for ReadReq accesses 920system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006194 # miss rate for WriteReq accesses 921system.cpu.dcache.WriteReq_miss_rate::total 0.006194 # miss rate for WriteReq accesses 922system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses 923system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses 924system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses 925system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses 926system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.123162 # average ReadReq miss latency 927system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.123162 # average ReadReq miss latency 928system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29032.655884 # average WriteReq miss latency 929system.cpu.dcache.WriteReq_avg_miss_latency::total 29032.655884 # average WriteReq miss latency 930system.cpu.dcache.demand_avg_miss_latency::cpu.data 22293.774224 # average overall miss latency 931system.cpu.dcache.demand_avg_miss_latency::total 22293.774224 # average overall miss latency 932system.cpu.dcache.overall_avg_miss_latency::cpu.data 22293.774224 # average overall miss latency 933system.cpu.dcache.overall_avg_miss_latency::total 22293.774224 # average overall miss latency 934system.cpu.dcache.blocked_cycles::no_mshrs 6982 # number of cycles access was blocked | 919system.cpu.dcache.demand_accesses::cpu.data 399321154 # number of demand (read+write) accesses 920system.cpu.dcache.demand_accesses::total 399321154 # number of demand (read+write) accesses 921system.cpu.dcache.overall_accesses::cpu.data 399321154 # number of overall (read+write) accesses 922system.cpu.dcache.overall_accesses::total 399321154 # number of overall (read+write) accesses 923system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011521 # miss rate for ReadReq accesses 924system.cpu.dcache.ReadReq_miss_rate::total 0.011521 # miss rate for ReadReq accesses 925system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006196 # miss rate for WriteReq accesses 926system.cpu.dcache.WriteReq_miss_rate::total 0.006196 # miss rate for WriteReq accesses 927system.cpu.dcache.demand_miss_rate::cpu.data 0.009532 # miss rate for demand accesses 928system.cpu.dcache.demand_miss_rate::total 0.009532 # miss rate for demand accesses 929system.cpu.dcache.overall_miss_rate::cpu.data 0.009532 # miss rate for overall accesses 930system.cpu.dcache.overall_miss_rate::total 0.009532 # miss rate for overall accesses 931system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20141.511360 # average ReadReq miss latency 932system.cpu.dcache.ReadReq_avg_miss_latency::total 20141.511360 # average ReadReq miss latency 933system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29037.108109 # average WriteReq miss latency 934system.cpu.dcache.WriteReq_avg_miss_latency::total 29037.108109 # average WriteReq miss latency 935system.cpu.dcache.demand_avg_miss_latency::cpu.data 22301.331575 # average overall miss latency 936system.cpu.dcache.demand_avg_miss_latency::total 22301.331575 # average overall miss latency 937system.cpu.dcache.overall_avg_miss_latency::cpu.data 22301.331575 # average overall miss latency 938system.cpu.dcache.overall_avg_miss_latency::total 22301.331575 # average overall miss latency 939system.cpu.dcache.blocked_cycles::no_mshrs 7238 # number of cycles access was blocked |
| 935system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 940system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 936system.cpu.dcache.blocked::no_mshrs 660 # number of cycles access was blocked | 941system.cpu.dcache.blocked::no_mshrs 664 # number of cycles access was blocked |
| 937system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 942system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 938system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.578788 # average number of cycles each access was blocked | 943system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.900602 # average number of cycles each access was blocked |
| 939system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 940system.cpu.dcache.fast_writes 0 # number of fast writes performed 941system.cpu.dcache.cache_copies 0 # number of cache copies performed 942system.cpu.dcache.writebacks::writebacks 2330749 # number of writebacks 943system.cpu.dcache.writebacks::total 2330749 # number of writebacks | 944system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 945system.cpu.dcache.fast_writes 0 # number of fast writes performed 946system.cpu.dcache.cache_copies 0 # number of cache copies performed 947system.cpu.dcache.writebacks::writebacks 2330749 # number of writebacks 948system.cpu.dcache.writebacks::total 2330749 # number of writebacks |
| 944system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120394 # number of ReadReq MSHR hits 945system.cpu.dcache.ReadReq_mshr_hits::total 1120394 # number of ReadReq MSHR hits 946system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits 947system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits 948system.cpu.dcache.demand_mshr_hits::cpu.data 1137413 # number of demand (read+write) MSHR hits 949system.cpu.dcache.demand_mshr_hits::total 1137413 # number of demand (read+write) MSHR hits 950system.cpu.dcache.overall_mshr_hits::cpu.data 1137413 # number of overall MSHR hits 951system.cpu.dcache.overall_mshr_hits::total 1137413 # number of overall MSHR hits 952system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762541 # number of ReadReq MSHR misses 953system.cpu.dcache.ReadReq_mshr_misses::total 1762541 # number of ReadReq MSHR misses 954system.cpu.dcache.WriteReq_mshr_misses::cpu.data 906893 # number of WriteReq MSHR misses 955system.cpu.dcache.WriteReq_mshr_misses::total 906893 # number of WriteReq MSHR misses 956system.cpu.dcache.demand_mshr_misses::cpu.data 2669434 # number of demand (read+write) MSHR misses 957system.cpu.dcache.demand_mshr_misses::total 2669434 # number of demand (read+write) MSHR misses 958system.cpu.dcache.overall_mshr_misses::cpu.data 2669434 # number of overall MSHR misses 959system.cpu.dcache.overall_mshr_misses::total 2669434 # number of overall MSHR misses 960system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30851541255 # number of ReadReq MSHR miss cycles 961system.cpu.dcache.ReadReq_mshr_miss_latency::total 30851541255 # number of ReadReq MSHR miss cycles 962system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24700633087 # number of WriteReq MSHR miss cycles 963system.cpu.dcache.WriteReq_mshr_miss_latency::total 24700633087 # number of WriteReq MSHR miss cycles 964system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55552174342 # number of demand (read+write) MSHR miss cycles 965system.cpu.dcache.demand_mshr_miss_latency::total 55552174342 # number of demand (read+write) MSHR miss cycles 966system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55552174342 # number of overall MSHR miss cycles 967system.cpu.dcache.overall_mshr_miss_latency::total 55552174342 # number of overall MSHR miss cycles 968system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007048 # mshr miss rate for ReadReq accesses 969system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007048 # mshr miss rate for ReadReq accesses 970system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006080 # mshr miss rate for WriteReq accesses 971system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006080 # mshr miss rate for WriteReq accesses | 949system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1119535 # number of ReadReq MSHR hits 950system.cpu.dcache.ReadReq_mshr_hits::total 1119535 # number of ReadReq MSHR hits 951system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17020 # number of WriteReq MSHR hits 952system.cpu.dcache.WriteReq_mshr_hits::total 17020 # number of WriteReq MSHR hits 953system.cpu.dcache.demand_mshr_hits::cpu.data 1136555 # number of demand (read+write) MSHR hits 954system.cpu.dcache.demand_mshr_hits::total 1136555 # number of demand (read+write) MSHR hits 955system.cpu.dcache.overall_mshr_hits::cpu.data 1136555 # number of overall MSHR hits 956system.cpu.dcache.overall_mshr_hits::total 1136555 # number of overall MSHR hits 957system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762610 # number of ReadReq MSHR misses 958system.cpu.dcache.ReadReq_mshr_misses::total 1762610 # number of ReadReq MSHR misses 959system.cpu.dcache.WriteReq_mshr_misses::cpu.data 907137 # number of WriteReq MSHR misses 960system.cpu.dcache.WriteReq_mshr_misses::total 907137 # number of WriteReq MSHR misses 961system.cpu.dcache.demand_mshr_misses::cpu.data 2669747 # number of demand (read+write) MSHR misses 962system.cpu.dcache.demand_mshr_misses::total 2669747 # number of demand (read+write) MSHR misses 963system.cpu.dcache.overall_mshr_misses::cpu.data 2669747 # number of overall MSHR misses 964system.cpu.dcache.overall_mshr_misses::total 2669747 # number of overall MSHR misses 965system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30854243503 # number of ReadReq MSHR miss cycles 966system.cpu.dcache.ReadReq_mshr_miss_latency::total 30854243503 # number of ReadReq MSHR miss cycles 967system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24711423781 # number of WriteReq MSHR miss cycles 968system.cpu.dcache.WriteReq_mshr_miss_latency::total 24711423781 # number of WriteReq MSHR miss cycles 969system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55565667284 # number of demand (read+write) MSHR miss cycles 970system.cpu.dcache.demand_mshr_miss_latency::total 55565667284 # number of demand (read+write) MSHR miss cycles 971system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55565667284 # number of overall MSHR miss cycles 972system.cpu.dcache.overall_mshr_miss_latency::total 55565667284 # number of overall MSHR miss cycles 973system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007046 # mshr miss rate for ReadReq accesses 974system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007046 # mshr miss rate for ReadReq accesses 975system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006082 # mshr miss rate for WriteReq accesses 976system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006082 # mshr miss rate for WriteReq accesses |
| 972system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for demand accesses 973system.cpu.dcache.demand_mshr_miss_rate::total 0.006686 # mshr miss rate for demand accesses 974system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for overall accesses 975system.cpu.dcache.overall_mshr_miss_rate::total 0.006686 # mshr miss rate for overall accesses | 977system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for demand accesses 978system.cpu.dcache.demand_mshr_miss_rate::total 0.006686 # mshr miss rate for demand accesses 979system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for overall accesses 980system.cpu.dcache.overall_mshr_miss_rate::total 0.006686 # mshr miss rate for overall accesses |
| 976system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.013385 # average ReadReq mshr miss latency 977system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.013385 # average ReadReq mshr miss latency 978system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27236.546193 # average WriteReq mshr miss latency 979system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27236.546193 # average WriteReq mshr miss latency 980system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20810.469314 # average overall mshr miss latency 981system.cpu.dcache.demand_avg_mshr_miss_latency::total 20810.469314 # average overall mshr miss latency 982system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20810.469314 # average overall mshr miss latency 983system.cpu.dcache.overall_avg_mshr_miss_latency::total 20810.469314 # average overall mshr miss latency | 981system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.861259 # average ReadReq mshr miss latency 982system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.861259 # average ReadReq mshr miss latency 983system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27241.115489 # average WriteReq mshr miss latency 984system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27241.115489 # average WriteReq mshr miss latency 985system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.083518 # average overall mshr miss latency 986system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.083518 # average overall mshr miss latency 987system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.083518 # average overall mshr miss latency 988system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.083518 # average overall mshr miss latency |
| 984system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 985 986---------- End Simulation Statistics ---------- | 989system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 990 991---------- End Simulation Statistics ---------- |