7,11c7,11
< host_inst_rate 75971 # Simulator instruction rate (inst/s)
< host_op_rate 140479 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 42257715 # Simulator tick rate (ticks/s)
< host_mem_usage 287264 # Number of bytes of host memory used
< host_seconds 10884.11 # Real time elapsed on the host
---
> host_inst_rate 70939 # Simulator instruction rate (inst/s)
> host_op_rate 131174 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 39458742 # Simulator tick rate (ticks/s)
> host_mem_usage 264492 # Number of bytes of host memory used
> host_seconds 11656.16 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 37483008 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 26316864 # Number of bytes written to this memory
< system.physmem.num_reads 585672 # Number of read requests responded to by this memory
< system.physmem.num_writes 411201 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory
> system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory
> system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s)
325a339
> system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses
326a341
> system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses
327a343
> system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses
328a345
> system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency
329a347
> system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency
330a349
> system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency
359a379
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses
360a381
> system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses
361a383
> system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses
362a385
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency
363a387
> system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
364a389
> system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
407a433
> system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses
408a435
> system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses
409a437
> system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses
410a439
> system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses
411a441
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency
412a443
> system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency
413a445
> system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency
414a447
> system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency
449a483
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses
450a485
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses
451a487
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses
452a489
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses
453a491
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency
454a493
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency
455a495
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
456a497
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
528a570
> system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses
529a572
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses
530a574
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses
532a577
> system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses
534a580
> system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses
536a583
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency
537a585
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency
538a587
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency
540a590
> system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency
542a593
> system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency
580a632
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses
581a634
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses
582a636
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses
584a639
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses
586a642
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses
588a645
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency
589a647
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency
590a649
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency
592a652
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
594a655
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
< host_inst_rate 75971 # Simulator instruction rate (inst/s)
< host_op_rate 140479 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 42257715 # Simulator tick rate (ticks/s)
< host_mem_usage 287264 # Number of bytes of host memory used
< host_seconds 10884.11 # Real time elapsed on the host
---
> host_inst_rate 70939 # Simulator instruction rate (inst/s)
> host_op_rate 131174 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 39458742 # Simulator tick rate (ticks/s)
> host_mem_usage 264492 # Number of bytes of host memory used
> host_seconds 11656.16 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 37483008 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 26316864 # Number of bytes written to this memory
< system.physmem.num_reads 585672 # Number of read requests responded to by this memory
< system.physmem.num_writes 411201 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory
> system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory
> system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s)
325a339
> system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses
326a341
> system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses
327a343
> system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses
328a345
> system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency
329a347
> system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency
330a349
> system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency
359a379
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses
360a381
> system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses
361a383
> system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses
362a385
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency
363a387
> system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
364a389
> system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
407a433
> system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses
408a435
> system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses
409a437
> system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses
410a439
> system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses
411a441
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency
412a443
> system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency
413a445
> system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency
414a447
> system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency
449a483
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses
450a485
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses
451a487
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses
452a489
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses
453a491
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency
454a493
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency
455a495
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
456a497
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
528a570
> system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses
529a572
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses
530a574
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses
532a577
> system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses
534a580
> system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses
536a583
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency
537a585
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency
538a587
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency
540a590
> system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency
542a593
> system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency
580a632
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses
581a634
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses
582a636
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses
584a639
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses
586a642
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses
588a645
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency
589a647
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency
590a649
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency
592a652
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
594a655
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency