3,5c3,5
< sim_seconds 0.481958 # Number of seconds simulated
< sim_ticks 481957625500 # Number of ticks simulated
< final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.482382 # Number of seconds simulated
> sim_ticks 482382057000 # Number of ticks simulated
> final_tick 482382057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 109870 # Simulator instruction rate (inst/s)
< host_op_rate 203315 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 64041688 # Simulator tick rate (ticks/s)
< host_mem_usage 315224 # Number of bytes of host memory used
< host_seconds 7525.69 # Real time elapsed on the host
---
> host_inst_rate 90853 # Simulator instruction rate (inst/s)
> host_op_rate 168124 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 53003549 # Simulator tick rate (ticks/s)
> host_mem_usage 321140 # Number of bytes of host memory used
> host_seconds 9100.94 # Real time elapsed on the host
16,49c16,49
< system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory
< system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory
< system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 386855 # Number of read requests accepted
< system.physmem.writeReqs 294920 # Number of write requests accepted
< system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue
< system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24650752 # Number of bytes read from this memory
> system.physmem.bytes_read::total 24805888 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory
> system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 385168 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 387592 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 321604 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 51102133 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51423737 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 321604 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 321604 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 39204244 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 39204244 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 39204244 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 321604 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 51102133 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 90627981 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 387592 # Number of read requests accepted
> system.physmem.writeReqs 295491 # Number of write requests accepted
> system.physmem.readBursts 387592 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 24786816 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue
> system.physmem.bytesWritten 18910464 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 24805888 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue
52,83c52,83
< system.physmem.perBankRdBursts::0 24516 # Per bank write bursts
< system.physmem.perBankRdBursts::1 26460 # Per bank write bursts
< system.physmem.perBankRdBursts::2 24685 # Per bank write bursts
< system.physmem.perBankRdBursts::3 24442 # Per bank write bursts
< system.physmem.perBankRdBursts::4 23203 # Per bank write bursts
< system.physmem.perBankRdBursts::5 23588 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24636 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24397 # Per bank write bursts
< system.physmem.perBankRdBursts::8 23786 # Per bank write bursts
< system.physmem.perBankRdBursts::9 23509 # Per bank write bursts
< system.physmem.perBankRdBursts::10 24817 # Per bank write bursts
< system.physmem.perBankRdBursts::11 23975 # Per bank write bursts
< system.physmem.perBankRdBursts::12 23290 # Per bank write bursts
< system.physmem.perBankRdBursts::13 22963 # Per bank write bursts
< system.physmem.perBankRdBursts::14 23965 # Per bank write bursts
< system.physmem.perBankRdBursts::15 24296 # Per bank write bursts
< system.physmem.perBankWrBursts::0 18881 # Per bank write bursts
< system.physmem.perBankWrBursts::1 19925 # Per bank write bursts
< system.physmem.perBankWrBursts::2 19022 # Per bank write bursts
< system.physmem.perBankWrBursts::3 18969 # Per bank write bursts
< system.physmem.perBankWrBursts::4 18086 # Per bank write bursts
< system.physmem.perBankWrBursts::5 18421 # Per bank write bursts
< system.physmem.perBankWrBursts::6 19142 # Per bank write bursts
< system.physmem.perBankWrBursts::7 19085 # Per bank write bursts
< system.physmem.perBankWrBursts::8 18675 # Per bank write bursts
< system.physmem.perBankWrBursts::9 17903 # Per bank write bursts
< system.physmem.perBankWrBursts::10 18899 # Per bank write bursts
< system.physmem.perBankWrBursts::11 17761 # Per bank write bursts
< system.physmem.perBankWrBursts::12 17398 # Per bank write bursts
< system.physmem.perBankWrBursts::13 16983 # Per bank write bursts
< system.physmem.perBankWrBursts::14 17797 # Per bank write bursts
< system.physmem.perBankWrBursts::15 17948 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 24694 # Per bank write bursts
> system.physmem.perBankRdBursts::1 26457 # Per bank write bursts
> system.physmem.perBankRdBursts::2 24696 # Per bank write bursts
> system.physmem.perBankRdBursts::3 24495 # Per bank write bursts
> system.physmem.perBankRdBursts::4 23285 # Per bank write bursts
> system.physmem.perBankRdBursts::5 23614 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24693 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24448 # Per bank write bursts
> system.physmem.perBankRdBursts::8 23844 # Per bank write bursts
> system.physmem.perBankRdBursts::9 23582 # Per bank write bursts
> system.physmem.perBankRdBursts::10 24812 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24004 # Per bank write bursts
> system.physmem.perBankRdBursts::12 23312 # Per bank write bursts
> system.physmem.perBankRdBursts::13 22998 # Per bank write bursts
> system.physmem.perBankRdBursts::14 24024 # Per bank write bursts
> system.physmem.perBankRdBursts::15 24336 # Per bank write bursts
> system.physmem.perBankWrBursts::0 19003 # Per bank write bursts
> system.physmem.perBankWrBursts::1 19960 # Per bank write bursts
> system.physmem.perBankWrBursts::2 19024 # Per bank write bursts
> system.physmem.perBankWrBursts::3 18975 # Per bank write bursts
> system.physmem.perBankWrBursts::4 18152 # Per bank write bursts
> system.physmem.perBankWrBursts::5 18441 # Per bank write bursts
> system.physmem.perBankWrBursts::6 19161 # Per bank write bursts
> system.physmem.perBankWrBursts::7 19119 # Per bank write bursts
> system.physmem.perBankWrBursts::8 18726 # Per bank write bursts
> system.physmem.perBankWrBursts::9 17970 # Per bank write bursts
> system.physmem.perBankWrBursts::10 18928 # Per bank write bursts
> system.physmem.perBankWrBursts::11 17785 # Per bank write bursts
> system.physmem.perBankWrBursts::12 17418 # Per bank write bursts
> system.physmem.perBankWrBursts::13 16994 # Per bank write bursts
> system.physmem.perBankWrBursts::14 17838 # Per bank write bursts
> system.physmem.perBankWrBursts::15 17982 # Per bank write bursts
86c86
< system.physmem.totGap 481957508500 # Total gap between requests
---
> system.physmem.totGap 482381969500 # Total gap between requests
93c93
< system.physmem.readPktSize::6 386855 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 387592 # Read request sizes (log2)
100,102c100,102
< system.physmem.writePktSize::6 294920 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 295491 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 381809 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 5176 # What read queue length does an incoming req see
104,105c104,105
< system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
148,174c148,174
< system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 6410 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 6707 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 17432 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 17622 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 17641 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 17648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 17656 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 17701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 17669 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 17671 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 17699 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 17719 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 17664 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 17663 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 17636 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
197,215c197,217
< system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 146280 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 298.722669 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 176.940489 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.258352 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 52888 36.16% 36.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 40462 27.66% 63.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14063 9.61% 73.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7664 5.24% 78.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 5102 3.49% 82.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3857 2.64% 84.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2918 1.99% 86.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2773 1.90% 88.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 16553 11.32% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 146280 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 17634 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 21.962913 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 18.199318 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 216.461189 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 17628 99.97% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
218,241c220,236
< system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads
< system.physmem.totQLat 4249579000 # Total ticks spent queuing
< system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 17634 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 17633 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.755969 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.728033 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.977832 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 10918 61.92% 61.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 278 1.58% 63.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 6268 35.55% 99.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 161 0.91% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 7 0.04% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 17633 # Writes before turning the bus around for reads
> system.physmem.totQLat 4311135000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11572897500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1936470000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11131.43 # Average queueing delay per DRAM burst
243,247c238,242
< system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29881.43 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 51.38 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 39.20 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 51.42 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 39.20 # Average system write bandwidth in MiByte/s
252,270c247,265
< system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing
< system.physmem.readRowHits 315674 # Number of row buffer hits during reads
< system.physmem.writeRowHits 215465 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes
< system.physmem.avgGap 706915.78 # Average gap between requests
< system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ)
< system.physmem_0.averagePower 690.294629 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states
---
> system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 21.28 # Average write queue length when enqueuing
> system.physmem.readRowHits 315765 # Number of row buffer hits during reads
> system.physmem.writeRowHits 220723 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
> system.physmem.avgGap 706183.54 # Average gap between requests
> system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 566682480 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 309201750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1531779600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 983877840 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 69780771990 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 228217880250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 332897011590 # Total energy per rank (pJ)
> system.physmem_0.averagePower 690.111043 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 379065618250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 16107780000 # Time in different power states
272c267
< system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 87208649000 # Time in different power states
274,284c269,279
< system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ)
< system.physmem_1.averagePower 689.434954 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states
---
> system.physmem_1.actEnergy 539164080 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 294186750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1489098000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 930690000 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 67080778605 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 230586295500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 332427030615 # Total energy per rank (pJ)
> system.physmem_1.averagePower 689.136751 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 383030551000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 16107780000 # Time in different power states
286c281
< system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 83243489000 # Time in different power states
288,292c283,287
< system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 297786504 # Number of BP lookups
< system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups
---
> system.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 297919436 # Number of BP lookups
> system.cpu.branchPred.condPredicted 297919436 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 23611614 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 229854393 # Number of BTB lookups
296,301c291,296
< system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.usedRAS 40311454 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 4410387 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 229854393 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 119921311 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 109933082 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 11586406 # Number of mispredicted indirect branches.
303c298
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
305,306c300,301
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
308,309c303,304
< system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 963915252 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 964764115 # number of cpu cycles simulated
312,324c307,319
< system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed
---
> system.cpu.fetch.icacheStallCycles 229640733 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1587519909 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 297919436 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 160232765 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 710474501 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 48125197 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 1838 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 31961 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 395431 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 7638 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 216406816 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 6303131 # Number of outstanding Icache misses that were squashed
326,328c321,323
< system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 964614734 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 3.081549 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.494827 # Number of instructions fetched each cycle (Total)
330,338c325,333
< system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 473031835 49.04% 49.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 36413294 3.77% 52.81% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 36207947 3.75% 56.57% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 33239258 3.45% 60.01% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 28476947 2.95% 62.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 30017172 3.11% 66.08% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 40187194 4.17% 70.24% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 37484755 3.89% 74.13% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 249556332 25.87% 100.00% # Number of instructions fetched each cycle (Total)
342,365c337,360
< system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 964614734 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.308800 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.645501 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 165560291 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 381637451 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 312327895 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 81026499 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 24062598 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 2744008679 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 24062598 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 201558349 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 194036216 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 13250 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 351418098 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 193526223 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2626516746 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 906315 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 120859920 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 22304361 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 41770089 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 2707207684 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 6591914084 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 4206827635 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 2574467 # Number of floating rename lookups
367,384c362,379
< system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 921 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 1090246112 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1066 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 982 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 368286677 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 608256588 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 244134978 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 253265740 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 76368619 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 2419508786 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 132419 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1999186857 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 3656712 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 889558685 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 1510180986 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 131867 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 964614734 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.072524 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.106121 # Number of insts issued each cycle
386,394c381,389
< system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 336173556 34.85% 34.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 135262022 14.02% 48.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 129832579 13.46% 62.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 119015920 12.34% 74.67% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 98090682 10.17% 84.84% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 67084509 6.95% 91.79% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 45576707 4.72% 96.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 22663670 2.35% 98.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 10915089 1.13% 100.00% # Number of insts issued each cycle
398c393
< system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 964614734 # Number of insts issued each cycle
400,430c395,425
< system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 11249182 43.29% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 11894821 45.77% 89.06% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 2844033 10.94% 100.00% # attempts to use FU when none available
433,437c428,432
< system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 2910415 0.15% 0.15% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 1333514799 66.70% 66.85% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 358060 0.02% 66.87% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 4798571 0.24% 67.11% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 67.11% # Type of FU issued
463,464c458,459
< system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 471222917 23.57% 90.68% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 186382093 9.32% 100.00% # Type of FU issued
467,479c462,474
< system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued
< system.cpu.iq.rate 2.074089 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1999186857 # Type of FU issued
> system.cpu.iq.rate 2.072203 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 25988036 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.012999 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 4991322155 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 3305635589 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1923777377 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 1311041 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 4133688 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 240317 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 2021708405 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 556073 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 179295064 # Number of loads that had data forwarded from stores
481,484c476,479
< system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 224173511 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 339017 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 636964 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 94976783 # Number of stores squashed
487,488c482,483
< system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 31958 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked
490,506c485,501
< system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 24062598 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 144797851 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 6250562 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 2419641205 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 1306710 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 608256824 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 244134978 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 45669 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1454928 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 3966770 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 636964 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 8731316 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 20649413 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 29380729 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1945668790 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 456756594 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 53518067 # Number of squashed instructions skipped in execute
509,519c504,514
< system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed
< system.cpu.iew.exec_branches 185171662 # Number of branches executed
< system.cpu.iew.exec_stores 178831439 # Number of stores executed
< system.cpu.iew.exec_rate 2.018648 # Inst execution rate
< system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1457092334 # num instructions producing a value
< system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 635598570 # number of memory reference insts executed
> system.cpu.iew.exec_branches 185172751 # Number of branches executed
> system.cpu.iew.exec_stores 178841976 # Number of stores executed
> system.cpu.iew.exec_rate 2.016730 # Inst execution rate
> system.cpu.iew.wb_sent 1934534562 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1924017694 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1456930726 # num instructions producing a value
> system.cpu.iew.wb_consumers 2203703226 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.994288 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.661128 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 889633438 # The number of squashed insts skipped by commit
521,524c516,519
< system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 23642184 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 831915086 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.839229 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.465352 # Number of insts commited each cycle
526,534c521,529
< system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 352165945 42.33% 42.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 184695932 22.20% 64.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 57945588 6.97% 71.50% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 87210863 10.48% 81.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 30437769 3.66% 85.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 26536432 3.19% 88.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 10472867 1.26% 90.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 9005135 1.08% 91.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 73444555 8.83% 100.00% # Number of insts commited each cycle
538c533
< system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 831915086 # Number of insts commited each cycle
584,588c579,583
< system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 3177371770 # The number of ROB reads
< system.cpu.rob.rob_writes 4973814894 # The number of ROB writes
< system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 73444555 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 3178186489 # The number of ROB reads
> system.cpu.rob.rob_writes 4973800859 # The number of ROB writes
> system.cpu.timesIdled 2058 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 149381 # Total number of cycles that the CPU has spent unscheduled due to idling
591,601c586,596
< system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads
< system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes
< system.cpu.fp_regfile_reads 239177 # number of floating regfile reads
< system.cpu.fp_regfile_writes 8 # number of floating regfile writes
< system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads
< system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes
< system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads
---
> system.cpu.cpi 1.166798 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.166798 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.857046 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.857046 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 2928420991 # number of integer regfile reads
> system.cpu.int_regfile_writes 1576721018 # number of integer regfile writes
> system.cpu.fp_regfile_reads 241306 # number of floating regfile reads
> system.cpu.fp_regfile_writes 1 # number of floating regfile writes
> system.cpu.cc_regfile_reads 617864492 # number of cc regfile reads
> system.cpu.cc_regfile_writes 419924545 # number of cc regfile writes
> system.cpu.misc_regfile_reads 1064270268 # number of misc regfile reads
603,612c598,607
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 2545945 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 2546182 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4087.922606 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 421485651 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2550278 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 165.270473 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 1898151500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4087.922606 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.998028 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.998028 # Average percentage of cache occupancy
615,617c610,613
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 3454 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
619,647c615,643
< system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits
< system.cpu.dcache.overall_hits::total 421064470 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses
< system.cpu.dcache.overall_misses::total 3357607 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.tag_accesses 852234240 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 852234240 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 273116230 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 273116230 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 148366946 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 148366946 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 421483176 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 421483176 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 421483176 # number of overall hits
> system.cpu.dcache.overall_hits::total 421483176 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2567540 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2567540 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 791265 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 791265 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 3358805 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3358805 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3358805 # number of overall misses
> system.cpu.dcache.overall_misses::total 3358805 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 57574934000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 57574934000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24743790498 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24743790498 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 82318724498 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 82318724498 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 82318724498 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 82318724498 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 275683770 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 275683770 # number of ReadReq accesses(hits+misses)
650,655c646,651
< system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 424841981 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 424841981 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 424841981 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 424841981 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009313 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.009313 # miss rate for ReadReq accesses
658,703c654,699
< system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks
< system.cpu.dcache.writebacks::total 2337968 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.007906 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.007906 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.007906 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.007906 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 24508.336893 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 24508.336893 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 1268 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 857 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.301050 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 105.666667 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 2337859 # number of writebacks
> system.cpu.dcache.writebacks::total 2337859 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 801102 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 801102 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5848 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 5848 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 806950 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 806950 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 806950 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 806950 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766438 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1766438 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785417 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 785417 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2551855 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2551855 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2551855 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2551855 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33894644000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 33894644000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23857134999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 23857134999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57751778999 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 57751778999 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57751778999 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 57751778999 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006407 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006407 # mshr miss rate for ReadReq accesses
706,723c702,719
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 4014 # number of replacements
< system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006007 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006007 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19188.131143 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19188.131143 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30375.119203 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30375.119203 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 4041 # number of replacements
> system.cpu.icache.tags.tagsinuse 1081.856161 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 216396902 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 5745 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 37666.997737 # Average number of references to valid blocks.
725,729c721,725
< system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.529250 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1724 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1081.856161 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.528250 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.528250 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1704 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
732,761c728,757
< system.cpu.icache.tags.age_task_id_blocks_1024::3 78 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits
< system.cpu.icache.overall_hits::total 216344175 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 9672 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 9672 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 9672 # number of overall misses
< system.cpu.icache.overall_misses::total 9672 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 343660500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 343660500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 343660500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 343660500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 343660500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 343660500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 216353847 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 216353847 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 216353847 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 216353847 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 216353847 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 216353847 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.832031 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 432820961 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 432820961 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 216397172 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 216397172 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 216397172 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 216397172 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 216397172 # number of overall hits
> system.cpu.icache.overall_hits::total 216397172 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses
> system.cpu.icache.overall_misses::total 9643 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 354601499 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 354601499 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 354601499 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 354601499 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 354601499 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 354601499 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 216406815 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 216406815 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 216406815 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 216406815 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 216406815 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 216406815 # number of overall (read+write) accesses
768,774c764,770
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35531.482630 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 35531.482630 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 35531.482630 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36772.944001 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 36772.944001 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 36772.944001 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 36772.944001 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked
776c772
< system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
778c774
< system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked
780,799c776,795
< system.cpu.icache.writebacks::writebacks 4014 # number of writebacks
< system.cpu.icache.writebacks::total 4014 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 7390 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243725000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 243725000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243725000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 243725000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243725000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 243725000 # number of overall MSHR miss cycles
---
> system.cpu.icache.writebacks::writebacks 4041 # number of writebacks
> system.cpu.icache.writebacks::total 4041 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2312 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2312 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2312 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2312 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2312 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2312 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7331 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 7331 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 7331 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 7331 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 7331 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251236999 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 251236999 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251236999 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 251236999 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251236999 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 251236999 # number of overall MSHR miss cycles
806,827c802,823
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 355161 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 8445.972818 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.639730 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005983 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.257751 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.903464 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 32366 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34270.495021 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34270.495021 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34270.495021 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34270.495021 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 356021 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 30615.396519 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4712767 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 388789 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.121657 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 82695006000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 70.818761 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.778038 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 30348.799719 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.002161 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005975 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.926172 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.934308 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
829,927c825,923
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11314 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 3923 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 577397 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 577397 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3252 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 3252 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588195 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1588195 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 3252 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2165592 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2168844 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 3252 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2165592 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2168844 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1342 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1342 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 206686 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 206686 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2416 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 2416 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 177763 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 177763 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 2416 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 384449 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 386865 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2416 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 384449 # number of overall misses
< system.cpu.l2cache.overall_misses::total 386865 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2044500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 2044500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16338042000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 16338042000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195535500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 195535500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14302139500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 14302139500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 195535500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 30640181500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30835717000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 195535500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 30640181500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30835717000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337968 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 2337968 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 3923 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 3923 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1659 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1659 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 784083 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 784083 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5668 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 5668 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765958 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1765958 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 5668 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2550041 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2555709 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 5668 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2550041 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2555709 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808921 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808921 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263602 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.263602 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.426253 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.426253 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100661 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100661 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.426253 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.150762 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.151373 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.426253 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.150762 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.151373 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1523.472429 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1523.472429 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79047.647156 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79047.647156 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80933.567881 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80933.567881 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80456.222611 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80456.222611 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79706.659946 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946 # average overall miss latency
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 165 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31150 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 41201341 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 41201341 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 2337859 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 2337859 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 3935 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 3935 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 1572 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 1572 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 577284 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 577284 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3232 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 3232 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587825 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1587825 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 3232 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2165109 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2168341 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 3232 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2165109 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2168341 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 206802 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 206802 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2424 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 2424 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178367 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 178367 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 2424 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 385169 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 387593 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2424 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 385169 # number of overall misses
> system.cpu.l2cache.overall_misses::total 387593 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 61000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 61000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16603167500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 16603167500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 203550000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 203550000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14526809000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 14526809000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 203550000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 31129976500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31333526500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 203550000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 31129976500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31333526500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337859 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 2337859 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 3935 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 3935 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1577 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1577 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 784086 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 784086 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5656 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 5656 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766192 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1766192 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 5656 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2550278 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2555934 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 5656 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2550278 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2555934 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003171 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003171 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263749 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.263749 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.428571 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.428571 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100990 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100990 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.428571 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.151030 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.151644 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.428571 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.151030 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.151644 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12200 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12200 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80285.333314 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80285.333314 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83972.772277 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83972.772277 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81443.366766 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81443.366766 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83972.772277 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80821.604283 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80841.311634 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83972.772277 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80821.604283 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80841.311634 # average overall miss latency
934,965c930,961
< system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks
< system.cpu.l2cache.writebacks::total 294920 # number of writebacks
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1342 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1342 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206686 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 206686 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2416 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2416 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 177763 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 177763 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2416 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 384449 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 386865 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2416 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 384449 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 386865 # number of overall MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 25553999 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 25553999 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14271182000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14271182000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171375500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171375500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12524509500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12524509500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171375500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26795691500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26967067000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171375500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26795691500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26967067000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks
> system.cpu.l2cache.writebacks::total 295491 # number of writebacks
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206802 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 206802 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2424 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2424 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178367 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178367 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 385169 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 387593 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 385169 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 387593 # number of overall MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14535147500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14535147500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179310000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179310000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12743139000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12743139000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179310000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27278286500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 27457596500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179310000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27278286500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 27457596500 # number of overall MSHR miss cycles
968,1023c964,1019
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 356883 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 18985088 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003171 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263749 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263749 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428571 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100990 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100990 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.151644 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.151644 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70285.333314 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70285.333314 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73972.772277 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73972.772277 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 5109409 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551871 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7932 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2949 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2946 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 1773523 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 2633350 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 4041 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 268853 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 1577 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 1577 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 784086 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 784086 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 7331 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766192 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17028 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649892 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7666920 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 620608 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312840768 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 313461376 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 357696 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 19018624 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 2915207 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.004295 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.065414 # Request fanout histogram
1025,1027c1021,1023
< system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2902688 99.57% 99.57% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 12516 0.43% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
1031,1032c1027,1028
< system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2915207 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4896659390 # Layer occupancy (ticks)
1034c1030
< system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 10998496 # Layer occupancy (ticks)
1036c1032
< system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3826206608 # Layer occupancy (ticks)
1038,1051c1034,1053
< system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 180179 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution
< system.membus.trans_dist::CleanEvict 57436 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution
< system.membus.trans_dist::ReadExReq 206676 # Transaction distribution
< system.membus.trans_dist::ReadExResp 206676 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 740700 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 353605 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 180791 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution
> system.membus.trans_dist::CleanEvict 57611 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
> system.membus.trans_dist::ReadExReq 206801 # Transaction distribution
> system.membus.trans_dist::ReadExResp 206801 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 180791 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128292 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128292 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1128292 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43717312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43717312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 43717312 # Cumulative packet size per connected master and slave (bytes)
1054c1056
< system.membus.snoop_fanout::samples 740563 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 387598 # Request fanout histogram
1058c1060
< system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 387598 100.00% 100.00% # Request fanout histogram
1063,1064c1065,1066
< system.membus.snoop_fanout::total 740563 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 387598 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1995849000 # Layer occupancy (ticks)
1066c1068
< system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2051150500 # Layer occupancy (ticks)