3,5c3,5
< sim_seconds 0.403707 # Number of seconds simulated
< sim_ticks 403706643500 # Number of ticks simulated
< final_tick 403706643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.403931 # Number of seconds simulated
> sim_ticks 403931323500 # Number of ticks simulated
> final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 76271 # Simulator instruction rate (inst/s)
< host_op_rate 141034 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37237827 # Simulator tick rate (ticks/s)
< host_mem_usage 423672 # Number of bytes of host memory used
< host_seconds 10841.31 # Real time elapsed on the host
---
> host_inst_rate 95186 # Simulator instruction rate (inst/s)
> host_op_rate 176009 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 46498470 # Simulator tick rate (ticks/s)
> host_mem_usage 433064 # Number of bytes of host memory used
> host_seconds 8686.98 # Real time elapsed on the host
16,48c16,48
< system.physmem.bytes_read::cpu.inst 216320 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24497408 # Number of bytes read from this memory
< system.physmem.bytes_read::total 24713728 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 216320 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 216320 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 18869312 # Number of bytes written to this memory
< system.physmem.bytes_written::total 18869312 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3380 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 382772 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 386152 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 294833 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 294833 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 535835 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 60681211 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 61217046 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 535835 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 535835 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 46740157 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 46740157 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 46740157 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 535835 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 60681211 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 107957203 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 386152 # Number of read requests accepted
< system.physmem.writeReqs 294833 # Number of write requests accepted
< system.physmem.readBursts 386152 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 294833 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 24695616 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue
< system.physmem.bytesWritten 18867776 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 24713728 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 18869312 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory
> system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory
> system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 386228 # Number of read requests accepted
> system.physmem.writeReqs 294838 # Number of write requests accepted
> system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue
> system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue
50,82c50,82
< system.physmem.neitherReadNorWriteReqs 195189 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 24028 # Per bank write bursts
< system.physmem.perBankRdBursts::1 26400 # Per bank write bursts
< system.physmem.perBankRdBursts::2 24980 # Per bank write bursts
< system.physmem.perBankRdBursts::3 24600 # Per bank write bursts
< system.physmem.perBankRdBursts::4 23395 # Per bank write bursts
< system.physmem.perBankRdBursts::5 23728 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24595 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24357 # Per bank write bursts
< system.physmem.perBankRdBursts::8 23707 # Per bank write bursts
< system.physmem.perBankRdBursts::9 23543 # Per bank write bursts
< system.physmem.perBankRdBursts::10 24760 # Per bank write bursts
< system.physmem.perBankRdBursts::11 23969 # Per bank write bursts
< system.physmem.perBankRdBursts::12 23156 # Per bank write bursts
< system.physmem.perBankRdBursts::13 22899 # Per bank write bursts
< system.physmem.perBankRdBursts::14 23872 # Per bank write bursts
< system.physmem.perBankRdBursts::15 23880 # Per bank write bursts
< system.physmem.perBankWrBursts::0 18605 # Per bank write bursts
< system.physmem.perBankWrBursts::1 19929 # Per bank write bursts
< system.physmem.perBankWrBursts::2 19196 # Per bank write bursts
< system.physmem.perBankWrBursts::3 18982 # Per bank write bursts
< system.physmem.perBankWrBursts::4 18144 # Per bank write bursts
< system.physmem.perBankWrBursts::5 18488 # Per bank write bursts
< system.physmem.perBankWrBursts::6 19136 # Per bank write bursts
< system.physmem.perBankWrBursts::7 19077 # Per bank write bursts
< system.physmem.perBankWrBursts::8 18672 # Per bank write bursts
< system.physmem.perBankWrBursts::9 17940 # Per bank write bursts
< system.physmem.perBankWrBursts::10 18886 # Per bank write bursts
< system.physmem.perBankWrBursts::11 17736 # Per bank write bursts
< system.physmem.perBankWrBursts::12 17372 # Per bank write bursts
< system.physmem.perBankWrBursts::13 16987 # Per bank write bursts
< system.physmem.perBankWrBursts::14 17811 # Per bank write bursts
< system.physmem.perBankWrBursts::15 17848 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 24062 # Per bank write bursts
> system.physmem.perBankRdBursts::1 26430 # Per bank write bursts
> system.physmem.perBankRdBursts::2 24903 # Per bank write bursts
> system.physmem.perBankRdBursts::3 24577 # Per bank write bursts
> system.physmem.perBankRdBursts::4 23181 # Per bank write bursts
> system.physmem.perBankRdBursts::5 23704 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24550 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24303 # Per bank write bursts
> system.physmem.perBankRdBursts::8 23663 # Per bank write bursts
> system.physmem.perBankRdBursts::9 23568 # Per bank write bursts
> system.physmem.perBankRdBursts::10 24789 # Per bank write bursts
> system.physmem.perBankRdBursts::11 23975 # Per bank write bursts
> system.physmem.perBankRdBursts::12 23330 # Per bank write bursts
> system.physmem.perBankRdBursts::13 22932 # Per bank write bursts
> system.physmem.perBankRdBursts::14 24089 # Per bank write bursts
> system.physmem.perBankRdBursts::15 23873 # Per bank write bursts
> system.physmem.perBankWrBursts::0 18604 # Per bank write bursts
> system.physmem.perBankWrBursts::1 19922 # Per bank write bursts
> system.physmem.perBankWrBursts::2 19191 # Per bank write bursts
> system.physmem.perBankWrBursts::3 18985 # Per bank write bursts
> system.physmem.perBankWrBursts::4 18090 # Per bank write bursts
> system.physmem.perBankWrBursts::5 18485 # Per bank write bursts
> system.physmem.perBankWrBursts::6 19138 # Per bank write bursts
> system.physmem.perBankWrBursts::7 19082 # Per bank write bursts
> system.physmem.perBankWrBursts::8 18642 # Per bank write bursts
> system.physmem.perBankWrBursts::9 17946 # Per bank write bursts
> system.physmem.perBankWrBursts::10 18887 # Per bank write bursts
> system.physmem.perBankWrBursts::11 17737 # Per bank write bursts
> system.physmem.perBankWrBursts::12 17398 # Per bank write bursts
> system.physmem.perBankWrBursts::13 16988 # Per bank write bursts
> system.physmem.perBankWrBursts::14 17875 # Per bank write bursts
> system.physmem.perBankWrBursts::15 17843 # Per bank write bursts
85c85
< system.physmem.totGap 403706602500 # Total gap between requests
---
> system.physmem.totGap 403931308500 # Total gap between requests
92c92
< system.physmem.readPktSize::6 386152 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 386228 # Read request sizes (log2)
99,105c99,105
< system.physmem.writePktSize::6 294833 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 380965 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 4554 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 304 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 294838 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
147,177c147,177
< system.physmem.wrQLenPdf::15 6120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 6530 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 16981 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 17547 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 17622 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 17651 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 17636 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 17673 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 17680 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 17702 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 17653 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 17736 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 17738 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 17711 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 17905 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 17556 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
196,214c196,214
< system.physmem.bytesPerActivate::samples 146765 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 296.814963 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 175.408246 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 322.979648 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 54126 36.88% 36.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 39824 27.13% 64.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13787 9.39% 73.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7512 5.12% 78.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 5608 3.82% 82.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3872 2.64% 84.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3087 2.10% 87.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 2794 1.90% 88.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 16155 11.01% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 146765 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 17509 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 22.037923 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 218.270562 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 17499 99.94% 99.94% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes
218,244c218,246
< system.physmem.rdPerTurnAround::total 17509 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 17509 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.837569 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.769084 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 2.527211 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 17319 98.91% 98.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 139 0.79% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 19 0.11% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 11 0.06% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 2 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 2 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 2 0.01% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 5 0.03% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 2 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 17509 # Writes before turning the bus around for reads
< system.physmem.totQLat 4289653250 # Total ticks spent queuing
< system.physmem.totMemAccLat 11524697000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1929345000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11116.86 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads
> system.physmem.totQLat 4291077750 # Total ticks spent queuing
> system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst
246,250c248,252
< system.physmem.avgMemAccLat 29866.86 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 61.17 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 46.74 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 61.22 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 46.74 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s
254c256
< system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes
---
> system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
256,258c258,260
< system.physmem.avgWrQLen 20.93 # Average write queue length when enqueuing
< system.physmem.readRowHits 317973 # Number of row buffer hits during reads
< system.physmem.writeRowHits 215927 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing
> system.physmem.readRowHits 317989 # Number of row buffer hits during reads
> system.physmem.writeRowHits 215873 # Number of row buffer hits during writes
260,273c262,275
< system.physmem.writeRowHitRate 73.24 # Row buffer hit rate for writes
< system.physmem.avgGap 592827.45 # Average gap between requests
< system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 569094120 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 310517625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1529307000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 981933840 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 62417540205 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 187468813500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 279645025170 # Total energy per rank (pJ)
< system.physmem_0.averagePower 692.702062 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 311319479750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 13480480000 # Time in different power states
---
> system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes
> system.physmem.avgGap 593086.88 # Average gap between requests
> system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ)
> system.physmem_0.averagePower 692.623817 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states
275c277
< system.physmem_0.memoryStateTime::ACT 78902125750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states
277,287c279,289
< system.physmem_1.actEnergy 540041040 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 294665250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1479816000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 928013760 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 60324869565 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 189304489500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 279239713995 # Total energy per rank (pJ)
< system.physmem_1.averagePower 691.698075 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 314381404750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 13480480000 # Time in different power states
---
> system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ)
> system.physmem_1.averagePower 691.740141 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states
289c291
< system.physmem_1.memoryStateTime::ACT 75839865250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states
291,295c293,297
< system.cpu.branchPred.lookups 219316547 # Number of BP lookups
< system.cpu.branchPred.condPredicted 219316547 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 8533340 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 124021938 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 121820147 # Number of BTB hits
---
> system.cpu.branchPred.lookups 219314839 # Number of BP lookups
> system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits
297,299c299,301
< system.cpu.branchPred.BTBHitPct 98.224676 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 27066490 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1406992 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions.
303c305
< system.cpu.numCycles 807413288 # number of cpu cycles simulated
---
> system.cpu.numCycles 807862648 # number of cpu cycles simulated
306,322c308,324
< system.cpu.fetch.icacheStallCycles 175921222 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1208610344 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 219316547 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 148886637 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 621541997 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 17781141 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 241 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 95442 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 760366 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 1422 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 170776115 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 2324492 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 807211301 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.786075 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.367353 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total)
324,332c326,334
< system.cpu.fetch.rateDist::0 417064653 51.67% 51.67% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 32628603 4.04% 55.71% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 31895320 3.95% 59.66% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 32734486 4.06% 63.72% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 26590994 3.29% 67.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 26897855 3.33% 70.34% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 35141039 4.35% 74.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 31437377 3.89% 78.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 172820974 21.41% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total)
336,359c338,361
< system.cpu.fetch.rateDist::total 807211301 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.271629 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.496892 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 120518152 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 370503139 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 225214950 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 82084490 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 8890570 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 2132165876 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 8890570 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 152539883 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 150620560 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 39985 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 271567858 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 223552445 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2088589695 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 134600 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 138169190 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 24839349 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 50537004 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 2190785289 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 5278493147 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 3357262511 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 59407 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups
361,378c363,380
< system.cpu.rename.UndoneMaps 576744435 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 3185 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2908 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 421985771 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 507135954 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 200817604 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 229019753 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 68232285 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 2023164418 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 22990 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1789038207 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 420221 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 494198707 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 833041498 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 22438 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 807211301 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.216320 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.070566 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle
380,388c382,390
< system.cpu.iq.issued_per_cycle::0 238530872 29.55% 29.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 123621910 15.31% 44.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 118898033 14.73% 59.59% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 107819129 13.36% 72.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 89545218 11.09% 84.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 60296093 7.47% 91.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 42279085 5.24% 96.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 18940691 2.35% 99.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 7280270 0.90% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle
392c394
< system.cpu.iq.issued_per_cycle::total 807211301 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle
394,424c396,426
< system.cpu.iq.fu_full::IntAlu 11520759 42.69% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 12368193 45.83% 88.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 3098262 11.48% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available
427,431c429,433
< system.cpu.iq.FU_type_0::No_OpClass 2718353 0.15% 0.15% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 1183132640 66.13% 66.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 368609 0.02% 66.30% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 3881115 0.22% 66.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued
434,435c436,437
< system.cpu.iq.FU_type_0::FloatMult 64 0.00% 66.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 344 0.00% 66.52% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued
457,458c459,460
< system.cpu.iq.FU_type_0::MemRead 428541213 23.95% 90.48% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 170395732 9.52% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued
461,473c463,475
< system.cpu.iq.FU_type_0::total 1789038207 # Type of FU issued
< system.cpu.iq.rate 2.215765 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 26987214 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.015085 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 4412665624 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 2517635859 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1762385104 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 29526 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 68682 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 5548 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1813294148 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 12920 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 186084957 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued
> system.cpu.iq.rate 2.214396 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores
475,478c477,480
< system.cpu.iew.lsq.thread0.squashedLoads 123036250 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 211434 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 371907 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 51657418 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed
481,482c483,484
< system.cpu.iew.lsq.thread0.rescheduledLoads 23176 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 1099 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked
484,500c486,502
< system.cpu.iew.iewSquashCycles 8890570 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 97719419 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 6134161 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 2023187408 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 375929 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 507138407 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 200817604 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 7250 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1817237 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 3413935 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 371907 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 4848104 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 4143061 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 8991165 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1770021029 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 423153321 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 19017178 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute
503,510c505,512
< system.cpu.iew.exec_refs 590346194 # number of memory reference insts executed
< system.cpu.iew.exec_branches 168990321 # Number of branches executed
< system.cpu.iew.exec_stores 167192873 # Number of stores executed
< system.cpu.iew.exec_rate 2.192212 # Inst execution rate
< system.cpu.iew.wb_sent 1766892997 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1762390652 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1339756908 # num instructions producing a value
< system.cpu.iew.wb_consumers 2049972766 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed
> system.cpu.iew.exec_branches 168980249 # Number of branches executed
> system.cpu.iew.exec_stores 167188538 # Number of stores executed
> system.cpu.iew.exec_rate 2.190883 # Inst execution rate
> system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1339663552 # num instructions producing a value
> system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value
512,513c514,515
< system.cpu.iew.wb_rate 2.182762 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.653549 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back
515c517
< system.cpu.commit.commitSquashedInsts 494260386 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit
517,520c519,522
< system.cpu.commit.branchMispredicts 8618895 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 739988037 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.066234 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.575521 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle
522,530c524,532
< system.cpu.commit.committed_per_cycle::0 275878158 37.28% 37.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 172126899 23.26% 60.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 55937459 7.56% 68.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 86300571 11.66% 79.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 25876597 3.50% 83.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 26568843 3.59% 86.85% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 9870767 1.33% 88.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 8919978 1.21% 89.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 78508765 10.61% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle
534c536
< system.cpu.commit.committed_per_cycle::total 739988037 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle
580,584c582,586
< system.cpu.commit.bw_lim_events 78508765 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 2684728359 # The number of ROB reads
< system.cpu.rob.rob_writes 4113896609 # The number of ROB writes
< system.cpu.timesIdled 2328 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 201987 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 2685200393 # The number of ROB reads
> system.cpu.rob.rob_writes 4113829657 # The number of ROB writes
> system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling
587,597c589,599
< system.cpu.cpi 0.976461 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.976461 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.024106 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.024106 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 2722667059 # number of integer regfile reads
< system.cpu.int_regfile_writes 1435857659 # number of integer regfile writes
< system.cpu.fp_regfile_reads 5817 # number of floating regfile reads
< system.cpu.fp_regfile_writes 496 # number of floating regfile writes
< system.cpu.cc_regfile_reads 596670071 # number of cc regfile reads
< system.cpu.cc_regfile_writes 405476387 # number of cc regfile writes
< system.cpu.misc_regfile_reads 971632449 # number of misc regfile reads
---
> system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads
> system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes
> system.cpu.fp_regfile_reads 5969 # number of floating regfile reads
> system.cpu.fp_regfile_writes 521 # number of floating regfile writes
> system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads
> system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes
> system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads
599,603c601,605
< system.cpu.dcache.tags.replacements 2530789 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4087.813367 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 381875640 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2534885 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 150.648112 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 2530897 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks.
605,607c607,609
< system.cpu.dcache.tags.occ_blocks::cpu.data 4087.813367 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy
609,612c611,614
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 3172 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id
614,641c616,643
< system.cpu.dcache.tags.tag_accesses 772839713 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 772839713 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 233227342 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 233227342 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 148173773 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 148173773 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 381401115 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 381401115 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 381401115 # number of overall hits
< system.cpu.dcache.overall_hits::total 381401115 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2764870 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2764870 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 986429 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 986429 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 3751299 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3751299 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3751299 # number of overall misses
< system.cpu.dcache.overall_misses::total 3751299 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 58802289500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 58802289500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 31059853996 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 31059853996 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 89862143496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 89862143496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 89862143496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 89862143496 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 235992212 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 235992212 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits
> system.cpu.dcache.overall_hits::total 381356978 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses
> system.cpu.dcache.overall_misses::total 3761732 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses)
644,669c646,671
< system.cpu.dcache.demand_accesses::cpu.data 385152414 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 385152414 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 385152414 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 385152414 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011716 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.011716 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21267.650739 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 21267.650739 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31487.166330 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31487.166330 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23954.940274 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23954.940274 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 9795 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1045 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.373206 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked
672,713c674,715
< system.cpu.dcache.writebacks::writebacks 2330774 # number of writebacks
< system.cpu.dcache.writebacks::total 2330774 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000095 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1000095 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19339 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 19339 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1019434 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1019434 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1019434 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1019434 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764775 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1764775 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967090 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 967090 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2731865 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2731865 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2731865 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2731865 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33541518000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 33541518000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29840523997 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 29840523997 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63382041997 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 63382041997 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63382041997 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 63382041997 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007478 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007478 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19006.115794 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19006.115794 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30855.994785 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30855.994785 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks
> system.cpu.dcache.writebacks::total 2330787 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency
715,719c717,721
< system.cpu.icache.tags.replacements 6640 # number of replacements
< system.cpu.icache.tags.tagsinuse 1037.923261 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 170565267 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 8248 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 20679.591052 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 6655 # number of replacements
> system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks.
721,728c723,730
< system.cpu.icache.tags.occ_blocks::cpu.inst 1037.923261 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.506798 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.506798 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id
730,769c732,771
< system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 341757570 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 341757570 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 170568161 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 170568161 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 170568161 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 170568161 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 170568161 # number of overall hits
< system.cpu.icache.overall_hits::total 170568161 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 207953 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 207953 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 207953 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 207953 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 207953 # number of overall misses
< system.cpu.icache.overall_misses::total 207953 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 1300977000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 1300977000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 1300977000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 1300977000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 1300977000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 1300977000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 170776114 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 170776114 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 170776114 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 170776114 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 170776114 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 170776114 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001218 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.001218 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.001218 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.001218 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.001218 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.001218 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6256.110756 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 6256.110756 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 6256.110756 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 6256.110756 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 718 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits
> system.cpu.icache.overall_hits::total 170580521 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses
> system.cpu.icache.overall_misses::total 208882 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked
773c775
< system.cpu.icache.avg_blocked_cycles::no_mshrs 59.833333 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked
777,806c779,808
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2609 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2609 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2609 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2609 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2609 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2609 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205344 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 205344 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 205344 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 205344 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 205344 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 205344 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 976991000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 976991000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 976991000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 976991000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 976991000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 976991000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4757.825892 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4757.825892 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency
808,822c810,824
< system.cpu.l2cache.tags.replacements 353471 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 29618.497788 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3892615 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 385807 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 10.089540 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 189374171500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 20946.463818 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.310071 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 8431.723899 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.639235 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007334 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.257316 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.903885 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 32336 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.replacements 353544 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.903914 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
824,825c826,827
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 218 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13380 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13379 # Occupied blocks per task id
827,917c829,919
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986816 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 43290247 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 43290247 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 2330774 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 2330774 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 1839 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 1839 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 563945 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 563945 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4854 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 4854 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588121 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1588121 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 4854 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2152066 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2156920 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 4854 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2152066 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2156920 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 195142 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 195142 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 206554 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 206554 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3382 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 3382 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176265 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 176265 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 382819 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 386201 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 382819 # number of overall misses
< system.cpu.l2cache.overall_misses::total 386201 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13466000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 13466000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16374024500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 16374024500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275872500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 275872500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14180580000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 14180580000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 275872500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 30554604500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30830477000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 275872500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 30554604500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30830477000 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 2330774 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 2330774 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196981 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 196981 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 770499 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 770499 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8236 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 8236 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764386 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1764386 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 8236 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2534885 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2543121 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 8236 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2534885 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2543121 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990664 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990664 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268078 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.268078 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.410636 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.410636 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099902 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099902 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.410636 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.151020 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.151861 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.410636 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.151020 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.151861 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.006160 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.006160 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79272.367032 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79272.367032 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81570.816085 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81570.816085 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80450.344652 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80450.344652 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81570.816085 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79814.754492 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79830.132496 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81570.816085 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79814.754492 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79830.132496 # average overall miss latency
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986633 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 43295860 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 43295860 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 2330787 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 2330787 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 1834 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 1834 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 563915 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 563915 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4843 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 4843 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588207 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1588207 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 4843 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2152122 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2156965 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 4843 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2152122 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2156965 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 196078 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 196078 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 206573 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 206573 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3410 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 3410 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176298 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 176298 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 3410 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 382871 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 386281 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3410 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 382871 # number of overall misses
> system.cpu.l2cache.overall_misses::total 386281 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13890000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 13890000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16378927500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 16378927500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 280136500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 280136500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14178823000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 14178823000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 280136500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 30557750500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 30837887000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 280136500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 30557750500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 30837887000 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 2330787 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 2330787 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 197912 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 197912 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 770488 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 770488 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8253 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 8253 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764505 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1764505 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 8253 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2534993 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2543246 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 8253 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2534993 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2543246 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990733 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990733 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268107 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.268107 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.413183 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.413183 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099914 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099914 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.413183 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.151034 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.151885 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.413183 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.151034 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.151885 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 70.839156 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 70.839156 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79288.810735 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79288.810735 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82151.466276 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82151.466276 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80425.319629 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80425.319629 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82151.466276 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79812.131240 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79832.782353 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82151.466276 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79812.131240 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79832.782353 # average overall miss latency
926,963c928,965
< system.cpu.l2cache.writebacks::writebacks 294833 # number of writebacks
< system.cpu.l2cache.writebacks::total 294833 # number of writebacks
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1941 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 1941 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195142 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 195142 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206554 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 206554 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3381 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3381 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176265 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176265 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3381 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 382819 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 386200 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3381 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 382819 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 386200 # number of overall MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4107801604 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4107801604 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14308484500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14308484500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 242006000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 242006000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12417930000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12417930000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 242006000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26726414500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26968420500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 242006000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26726414500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26968420500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.writebacks::writebacks 294838 # number of writebacks
> system.cpu.l2cache.writebacks::total 294838 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1958 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 1958 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 196078 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 196078 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206573 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 206573 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3408 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3408 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176298 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176298 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3408 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 382871 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 386279 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3408 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 382871 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 386279 # number of overall MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4323708271 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4323708271 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14313197500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14313197500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 245909500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 245909500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12415843000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12415843000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245909500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26729040500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26974950000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245909500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26729040500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26974950000 # number of overall MSHR miss cycles
966,993c968,995
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990664 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990664 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268078 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268078 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.410515 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099902 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099902 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.151861 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.151861 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21050.320300 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21050.320300 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69272.367032 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69272.367032 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71578.231293 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71578.231293 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70450.344652 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70450.344652 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency
995,1013c997,1021
< system.cpu.toL2Bus.trans_dist::ReadResp 1969728 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 2625607 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 254220 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 196981 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 196981 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 770499 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 770499 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 205344 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764386 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219812 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7983854 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8203666 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 526976 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311402176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 311929152 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 550579 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 5828110 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.060649 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.238686 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 551588 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram
1015,1017c1023,1025
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5474639 93.94% 93.94% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 353471 6.06% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1019,1022c1027,1030
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 5828110 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5096523027 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks)
1024c1032
< system.cpu.toL2Bus.respLayer0.occupancy 308017990 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks)
1026c1034
< system.cpu.toL2Bus.respLayer1.occupancy 3900818077 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks)
1028,1041c1036,1049
< system.membus.trans_dist::ReadResp 179644 # Transaction distribution
< system.membus.trans_dist::Writeback 294833 # Transaction distribution
< system.membus.trans_dist::CleanEvict 57066 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 195189 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 195189 # Transaction distribution
< system.membus.trans_dist::ReadExReq 206507 # Transaction distribution
< system.membus.trans_dist::ReadExResp 206507 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 179645 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514580 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514580 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1514580 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582976 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43582976 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 43582976 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadResp 179703 # Transaction distribution
> system.membus.trans_dist::Writeback 294838 # Transaction distribution
> system.membus.trans_dist::CleanEvict 57117 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution
> system.membus.trans_dist::ReadExReq 206523 # Transaction distribution
> system.membus.trans_dist::ReadExResp 206523 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes)
1043c1051
< system.membus.snoop_fanout::samples 933240 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 934311 # Request fanout histogram
1047c1055
< system.membus.snoop_fanout::0 933240 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram
1052,1053c1060,1061
< system.membus.snoop_fanout::total 933240 # Request fanout histogram
< system.membus.reqLayer0.occupancy 2243803396 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 934311 # Request fanout histogram
> system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks)
1055c1063
< system.membus.respLayer1.occupancy 2433027599 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks)