1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.459938 # Number of seconds simulated
4sim_ticks 459937575500 # Number of ticks simulated
5final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.459938 # Number of seconds simulated
4sim_ticks 459937575500 # Number of ticks simulated
5final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 75971 # Simulator instruction rate (inst/s)
8host_op_rate 140479 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42257715 # Simulator tick rate (ticks/s)
10host_mem_usage 287264 # Number of bytes of host memory used
11host_seconds 10884.11 # Real time elapsed on the host
| 7host_inst_rate 70939 # Simulator instruction rate (inst/s)
8host_op_rate 131174 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 39458742 # Simulator tick rate (ticks/s)
10host_mem_usage 264492 # Number of bytes of host memory used
11host_seconds 11656.16 # Real time elapsed on the host
|
12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
| 12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read 37483008 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 26316864 # Number of bytes written to this memory
17system.physmem.num_reads 585672 # Number of read requests responded to by this memory
18system.physmem.num_writes 411201 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory
16system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory
20system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s)
|
24system.cpu.workload.num_syscalls 551 # Number of system calls
25system.cpu.numCycles 919875152 # number of cpu cycles simulated
26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
28system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups
29system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted
30system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect
31system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups
32system.cpu.BPredUnit.BTBHits 155872353 # Number of BTB hits
33system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
34system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
35system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
36system.cpu.fetch.icacheStallCycles 191636234 # Number of cycles fetch is stalled on an Icache miss
37system.cpu.fetch.Insts 1263077256 # Number of instructions fetch has processed
38system.cpu.fetch.Branches 225607243 # Number of branches that fetch encountered
39system.cpu.fetch.predictedBranches 155872353 # Number of branches that fetch has predicted taken
40system.cpu.fetch.Cycles 392059630 # Number of cycles fetch has run and was not squashing or blocked
41system.cpu.fetch.SquashCycles 98480346 # Number of cycles fetch has spent squashing
42system.cpu.fetch.BlockedCycles 233495655 # Number of cycles fetch has spent blocked
43system.cpu.fetch.MiscStallCycles 26883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
44system.cpu.fetch.PendingTrapStallCycles 277282 # Number of stall cycles due to pending traps
45system.cpu.fetch.CacheLines 183482871 # Number of cache lines fetched
46system.cpu.fetch.IcacheSquashes 3659349 # Number of outstanding Icache misses that were squashed
47system.cpu.fetch.rateDist::samples 901432928 # Number of instructions fetched each cycle (Total)
48system.cpu.fetch.rateDist::mean 2.597231 # Number of instructions fetched each cycle (Total)
49system.cpu.fetch.rateDist::stdev 3.389695 # Number of instructions fetched each cycle (Total)
50system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
51system.cpu.fetch.rateDist::0 513839664 57.00% 57.00% # Number of instructions fetched each cycle (Total)
52system.cpu.fetch.rateDist::1 25974503 2.88% 59.88% # Number of instructions fetched each cycle (Total)
53system.cpu.fetch.rateDist::2 29108148 3.23% 63.11% # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::3 30308604 3.36% 66.48% # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::4 19639160 2.18% 68.65% # Number of instructions fetched each cycle (Total)
56system.cpu.fetch.rateDist::5 25619098 2.84% 71.50% # Number of instructions fetched each cycle (Total)
57system.cpu.fetch.rateDist::6 32630243 3.62% 75.12% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::7 30828862 3.42% 78.54% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::8 193484646 21.46% 100.00% # Number of instructions fetched each cycle (Total)
60system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.rateDist::total 901432928 # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.branchRate 0.245259 # Number of branch fetches per cycle
65system.cpu.fetch.rate 1.373096 # Number of inst fetches per cycle
66system.cpu.decode.IdleCycles 252952155 # Number of cycles decode is idle
67system.cpu.decode.BlockedCycles 185449202 # Number of cycles decode is blocked
68system.cpu.decode.RunCycles 329948666 # Number of cycles decode is running
69system.cpu.decode.UnblockCycles 49145661 # Number of cycles decode is unblocking
70system.cpu.decode.SquashCycles 83937244 # Number of cycles decode is squashing
71system.cpu.decode.DecodedInsts 2290194252 # Number of instructions handled by decode
72system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
73system.cpu.rename.SquashCycles 83937244 # Number of cycles rename is squashing
74system.cpu.rename.IdleCycles 289581235 # Number of cycles rename is idle
75system.cpu.rename.BlockCycles 42452690 # Number of cycles rename is blocking
76system.cpu.rename.serializeStallCycles 14732 # count of cycles rename stalled for serializing inst
77system.cpu.rename.RunCycles 340327979 # Number of cycles rename is running
78system.cpu.rename.UnblockCycles 145119048 # Number of cycles rename is unblocking
79system.cpu.rename.RenamedInsts 2240246263 # Number of instructions processed by rename
80system.cpu.rename.ROBFullEvents 3253 # Number of times rename has blocked due to ROB full
81system.cpu.rename.IQFullEvents 23409384 # Number of times rename has blocked due to IQ full
82system.cpu.rename.LSQFullEvents 104435988 # Number of times rename has blocked due to LSQ full
83system.cpu.rename.FullRegisterEvents 12914 # Number of times there has been no free registers
84system.cpu.rename.RenamedOperands 2886886923 # Number of destination operands rename has renamed
85system.cpu.rename.RenameLookups 6492696430 # Number of register rename lookups that rename has made
86system.cpu.rename.int_rename_lookups 6491823905 # Number of integer rename lookups
87system.cpu.rename.fp_rename_lookups 872525 # Number of floating rename lookups
88system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed
89system.cpu.rename.UndoneMaps 893809439 # Number of HB maps that are undone due to squashing
90system.cpu.rename.serializingInsts 1297 # count of serializing insts renamed
91system.cpu.rename.tempSerializingInsts 1279 # count of temporary serializing insts renamed
92system.cpu.rename.skidInsts 347581498 # count of insts added to the skid buffer
93system.cpu.memDep0.insertedLoads 540130264 # Number of loads inserted to the mem dependence unit.
94system.cpu.memDep0.insertedStores 217339026 # Number of stores inserted to the mem dependence unit.
95system.cpu.memDep0.conflictingLoads 215698631 # Number of conflicting loads.
96system.cpu.memDep0.conflictingStores 63624557 # Number of conflicting stores.
97system.cpu.iq.iqInstsAdded 2143116411 # Number of instructions added to the IQ (excludes non-spec)
98system.cpu.iq.iqNonSpecInstsAdded 61984 # Number of non-speculative instructions added to the IQ
99system.cpu.iq.iqInstsIssued 1846710444 # Number of instructions issued
100system.cpu.iq.iqSquashedInstsIssued 1594990 # Number of squashed instructions issued
101system.cpu.iq.iqSquashedInstsExamined 612455576 # Number of squashed instructions iterated over during squash; mainly for profiling
102system.cpu.iq.iqSquashedOperandsExamined 1230055220 # Number of squashed operands that are examined and possibly removed from graph
103system.cpu.iq.iqSquashedNonSpecRemoved 61431 # Number of squashed non-spec instructions that were removed
104system.cpu.iq.issued_per_cycle::samples 901432928 # Number of insts issued each cycle
105system.cpu.iq.issued_per_cycle::mean 2.048639 # Number of insts issued each cycle
106system.cpu.iq.issued_per_cycle::stdev 1.805034 # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::0 246353790 27.33% 27.33% # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::1 156616035 17.37% 44.70% # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::2 150729220 16.72% 61.42% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::3 147768173 16.39% 77.82% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::4 103385508 11.47% 89.29% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::5 58828894 6.53% 95.81% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::6 27652970 3.07% 98.88% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::7 9059576 1.01% 99.88% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::8 1038762 0.12% 100.00% # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
120system.cpu.iq.issued_per_cycle::total 901432928 # Number of insts issued each cycle
121system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
122system.cpu.iq.fu_full::IntAlu 2653442 16.77% 16.77% # attempts to use FU when none available
123system.cpu.iq.fu_full::IntMult 0 0.00% 16.77% # attempts to use FU when none available
124system.cpu.iq.fu_full::IntDiv 0 0.00% 16.77% # attempts to use FU when none available
125system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.77% # attempts to use FU when none available
126system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.77% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.77% # attempts to use FU when none available
128system.cpu.iq.fu_full::FloatMult 0 0.00% 16.77% # attempts to use FU when none available
129system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.77% # attempts to use FU when none available
130system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
131system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.77% # attempts to use FU when none available
132system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.77% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.77% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.77% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.77% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.77% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdMult 0 0.00% 16.77% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.77% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdShift 0 0.00% 16.77% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.77% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.77% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.77% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.77% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.77% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.77% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.77% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.77% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.77% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.77% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
151system.cpu.iq.fu_full::MemRead 9987443 63.11% 79.88% # attempts to use FU when none available
152system.cpu.iq.fu_full::MemWrite 3184017 20.12% 100.00% # attempts to use FU when none available
153system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
154system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
155system.cpu.iq.FU_type_0::No_OpClass 2723282 0.15% 0.15% # Type of FU issued
156system.cpu.iq.FU_type_0::IntAlu 1219442774 66.03% 66.18% # Type of FU issued
157system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued
158system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued
159system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued
160system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
162system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
163system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
164system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
165system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
166system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
185system.cpu.iq.FU_type_0::MemRead 447111847 24.21% 90.39% # Type of FU issued
186system.cpu.iq.FU_type_0::MemWrite 177432541 9.61% 100.00% # Type of FU issued
187system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
188system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
189system.cpu.iq.FU_type_0::total 1846710444 # Type of FU issued
190system.cpu.iq.rate 2.007566 # Inst issue rate
191system.cpu.iq.fu_busy_cnt 15824902 # FU busy when requested
192system.cpu.iq.fu_busy_rate 0.008569 # FU busy rate (busy events/executed inst)
193system.cpu.iq.int_inst_queue_reads 4612265736 # Number of integer instruction queue reads
194system.cpu.iq.int_inst_queue_writes 2755596507 # Number of integer instruction queue writes
195system.cpu.iq.int_inst_queue_wakeup_accesses 1806213833 # Number of integer instruction queue wakeup accesses
196system.cpu.iq.fp_inst_queue_reads 7972 # Number of floating instruction queue reads
197system.cpu.iq.fp_inst_queue_writes 299756 # Number of floating instruction queue writes
198system.cpu.iq.fp_inst_queue_wakeup_accesses 262 # Number of floating instruction queue wakeup accesses
199system.cpu.iq.int_alu_accesses 1859809264 # Number of integer alu accesses
200system.cpu.iq.fp_alu_accesses 2800 # Number of floating point alu accesses
201system.cpu.iew.lsq.thread0.forwLoads 168051220 # Number of loads that had data forwarded from stores
202system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
203system.cpu.iew.lsq.thread0.squashedLoads 156028104 # Number of loads squashed
204system.cpu.iew.lsq.thread0.ignoredResponses 428762 # Number of memory responses ignored because the instruction is squashed
205system.cpu.iew.lsq.thread0.memOrderViolation 273999 # Number of memory ordering violations
206system.cpu.iew.lsq.thread0.squashedStores 68179105 # Number of stores squashed
207system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
208system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
209system.cpu.iew.lsq.thread0.rescheduledLoads 6544 # Number of loads that were rescheduled
210system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
211system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
212system.cpu.iew.iewSquashCycles 83937244 # Number of cycles IEW is squashing
213system.cpu.iew.iewBlockCycles 7052726 # Number of cycles IEW is blocking
214system.cpu.iew.iewUnblockCycles 1164788 # Number of cycles IEW is unblocking
215system.cpu.iew.iewDispatchedInsts 2143178395 # Number of instructions dispatched to IQ
216system.cpu.iew.iewDispSquashedInsts 2770813 # Number of squashed instructions skipped by dispatch
217system.cpu.iew.iewDispLoadInsts 540130264 # Number of dispatched load instructions
218system.cpu.iew.iewDispStoreInsts 217339290 # Number of dispatched store instructions
219system.cpu.iew.iewDispNonSpecInsts 5780 # Number of dispatched non-speculative instructions
220system.cpu.iew.iewIQFullEvents 918370 # Number of times the IQ has become full, causing a stall
221system.cpu.iew.iewLSQFullEvents 16344 # Number of times the LSQ has become full, causing a stall
222system.cpu.iew.memOrderViolationEvents 273999 # Number of memory order violations
223system.cpu.iew.predictedTakenIncorrect 10084956 # Number of branches that were predicted taken incorrectly
224system.cpu.iew.predictedNotTakenIncorrect 5239444 # Number of branches that were predicted not taken incorrectly
225system.cpu.iew.branchMispredicts 15324400 # Number of branch mispredicts detected at execute
226system.cpu.iew.iewExecutedInsts 1818728049 # Number of executed instructions
227system.cpu.iew.iewExecLoadInsts 438648218 # Number of load instructions executed
228system.cpu.iew.iewExecSquashedInsts 27982395 # Number of squashed instructions skipped in execute
229system.cpu.iew.exec_swp 0 # number of swp insts executed
230system.cpu.iew.exec_nop 0 # number of nop insts executed
231system.cpu.iew.exec_refs 610505515 # number of memory reference insts executed
232system.cpu.iew.exec_branches 170830738 # Number of branches executed
233system.cpu.iew.exec_stores 171857297 # Number of stores executed
234system.cpu.iew.exec_rate 1.977147 # Inst execution rate
235system.cpu.iew.wb_sent 1813502289 # cumulative count of insts sent to commit
236system.cpu.iew.wb_count 1806214095 # cumulative count of insts written-back
237system.cpu.iew.wb_producers 1379770015 # num instructions producing a value
238system.cpu.iew.wb_consumers 2939115295 # num instructions consuming a value
239system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
240system.cpu.iew.wb_rate 1.963543 # insts written-back per cycle
241system.cpu.iew.wb_fanout 0.469451 # average fanout of values written-back
242system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
243system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
244system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
245system.cpu.commit.commitSquashedInsts 614215075 # The number of squashed insts skipped by commit
246system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
247system.cpu.commit.branchMispredicts 14315916 # The number of times a branch was mispredicted
248system.cpu.commit.committed_per_cycle::samples 817495684 # Number of insts commited each cycle
249system.cpu.commit.committed_per_cycle::mean 1.870333 # Number of insts commited each cycle
250system.cpu.commit.committed_per_cycle::stdev 2.327982 # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::0 301315612 36.86% 36.86% # Number of insts commited each cycle
253system.cpu.commit.committed_per_cycle::1 204371597 25.00% 61.86% # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::2 73328146 8.97% 70.83% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::3 95079836 11.63% 82.46% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::4 30908814 3.78% 86.24% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::5 28772319 3.52% 89.76% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::6 16400347 2.01% 91.77% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::7 11729678 1.43% 93.20% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::8 55589335 6.80% 100.00% # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
264system.cpu.commit.committed_per_cycle::total 817495684 # Number of insts commited each cycle
265system.cpu.commit.committedInsts 826877144 # Number of instructions committed
266system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
267system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
268system.cpu.commit.refs 533262345 # Number of memory references committed
269system.cpu.commit.loads 384102160 # Number of loads committed
270system.cpu.commit.membars 0 # Number of memory barriers committed
271system.cpu.commit.branches 149758588 # Number of branches committed
272system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
273system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
274system.cpu.commit.function_calls 0 # Number of function calls committed.
275system.cpu.commit.bw_lim_events 55589335 # number cycles where commit BW limit reached
276system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
277system.cpu.rob.rob_reads 2905110180 # The number of ROB reads
278system.cpu.rob.rob_writes 4370460169 # The number of ROB writes
279system.cpu.timesIdled 411218 # Number of times that the entire CPU went into an idle state and unscheduled itself
280system.cpu.idleCycles 18442224 # Total number of cycles that the CPU has spent unscheduled due to idling
281system.cpu.committedInsts 826877144 # Number of Instructions Simulated
282system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
283system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
284system.cpu.cpi 1.112469 # CPI: Cycles Per Instruction
285system.cpu.cpi_total 1.112469 # CPI: Total CPI of All Threads
286system.cpu.ipc 0.898901 # IPC: Instructions Per Cycle
287system.cpu.ipc_total 0.898901 # IPC: Total IPC of All Threads
288system.cpu.int_regfile_reads 4004380471 # number of integer regfile reads
289system.cpu.int_regfile_writes 2286341091 # number of integer regfile writes
290system.cpu.fp_regfile_reads 262 # number of floating regfile reads
291system.cpu.misc_regfile_reads 1001920300 # number of misc regfile reads
292system.cpu.icache.replacements 10653 # number of replacements
293system.cpu.icache.tagsinuse 997.180863 # Cycle average of tags in use
294system.cpu.icache.total_refs 183252097 # Total number of references to valid blocks.
295system.cpu.icache.sampled_refs 12174 # Sample count of references to valid blocks.
296system.cpu.icache.avg_refs 15052.743305 # Average number of references to valid blocks.
297system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
298system.cpu.icache.occ_blocks::cpu.inst 997.180863 # Average occupied blocks per requestor
299system.cpu.icache.occ_percent::cpu.inst 0.486905 # Average percentage of cache occupancy
300system.cpu.icache.occ_percent::total 0.486905 # Average percentage of cache occupancy
301system.cpu.icache.ReadReq_hits::cpu.inst 183258482 # number of ReadReq hits
302system.cpu.icache.ReadReq_hits::total 183258482 # number of ReadReq hits
303system.cpu.icache.demand_hits::cpu.inst 183258482 # number of demand (read+write) hits
304system.cpu.icache.demand_hits::total 183258482 # number of demand (read+write) hits
305system.cpu.icache.overall_hits::cpu.inst 183258482 # number of overall hits
306system.cpu.icache.overall_hits::total 183258482 # number of overall hits
307system.cpu.icache.ReadReq_misses::cpu.inst 224389 # number of ReadReq misses
308system.cpu.icache.ReadReq_misses::total 224389 # number of ReadReq misses
309system.cpu.icache.demand_misses::cpu.inst 224389 # number of demand (read+write) misses
310system.cpu.icache.demand_misses::total 224389 # number of demand (read+write) misses
311system.cpu.icache.overall_misses::cpu.inst 224389 # number of overall misses
312system.cpu.icache.overall_misses::total 224389 # number of overall misses
313system.cpu.icache.ReadReq_miss_latency::cpu.inst 1641701500 # number of ReadReq miss cycles
314system.cpu.icache.ReadReq_miss_latency::total 1641701500 # number of ReadReq miss cycles
315system.cpu.icache.demand_miss_latency::cpu.inst 1641701500 # number of demand (read+write) miss cycles
316system.cpu.icache.demand_miss_latency::total 1641701500 # number of demand (read+write) miss cycles
317system.cpu.icache.overall_miss_latency::cpu.inst 1641701500 # number of overall miss cycles
318system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles
319system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses)
321system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses
322system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses
323system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses
324system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses
325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
| 37system.cpu.workload.num_syscalls 551 # Number of system calls
38system.cpu.numCycles 919875152 # number of cpu cycles simulated
39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups
42system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted
43system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect
44system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups
45system.cpu.BPredUnit.BTBHits 155872353 # Number of BTB hits
46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
49system.cpu.fetch.icacheStallCycles 191636234 # Number of cycles fetch is stalled on an Icache miss
50system.cpu.fetch.Insts 1263077256 # Number of instructions fetch has processed
51system.cpu.fetch.Branches 225607243 # Number of branches that fetch encountered
52system.cpu.fetch.predictedBranches 155872353 # Number of branches that fetch has predicted taken
53system.cpu.fetch.Cycles 392059630 # Number of cycles fetch has run and was not squashing or blocked
54system.cpu.fetch.SquashCycles 98480346 # Number of cycles fetch has spent squashing
55system.cpu.fetch.BlockedCycles 233495655 # Number of cycles fetch has spent blocked
56system.cpu.fetch.MiscStallCycles 26883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
57system.cpu.fetch.PendingTrapStallCycles 277282 # Number of stall cycles due to pending traps
58system.cpu.fetch.CacheLines 183482871 # Number of cache lines fetched
59system.cpu.fetch.IcacheSquashes 3659349 # Number of outstanding Icache misses that were squashed
60system.cpu.fetch.rateDist::samples 901432928 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::mean 2.597231 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::stdev 3.389695 # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.rateDist::0 513839664 57.00% 57.00% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::1 25974503 2.88% 59.88% # Number of instructions fetched each cycle (Total)
66system.cpu.fetch.rateDist::2 29108148 3.23% 63.11% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::3 30308604 3.36% 66.48% # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::4 19639160 2.18% 68.65% # Number of instructions fetched each cycle (Total)
69system.cpu.fetch.rateDist::5 25619098 2.84% 71.50% # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.rateDist::6 32630243 3.62% 75.12% # Number of instructions fetched each cycle (Total)
71system.cpu.fetch.rateDist::7 30828862 3.42% 78.54% # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::8 193484646 21.46% 100.00% # Number of instructions fetched each cycle (Total)
73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
76system.cpu.fetch.rateDist::total 901432928 # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.branchRate 0.245259 # Number of branch fetches per cycle
78system.cpu.fetch.rate 1.373096 # Number of inst fetches per cycle
79system.cpu.decode.IdleCycles 252952155 # Number of cycles decode is idle
80system.cpu.decode.BlockedCycles 185449202 # Number of cycles decode is blocked
81system.cpu.decode.RunCycles 329948666 # Number of cycles decode is running
82system.cpu.decode.UnblockCycles 49145661 # Number of cycles decode is unblocking
83system.cpu.decode.SquashCycles 83937244 # Number of cycles decode is squashing
84system.cpu.decode.DecodedInsts 2290194252 # Number of instructions handled by decode
85system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
86system.cpu.rename.SquashCycles 83937244 # Number of cycles rename is squashing
87system.cpu.rename.IdleCycles 289581235 # Number of cycles rename is idle
88system.cpu.rename.BlockCycles 42452690 # Number of cycles rename is blocking
89system.cpu.rename.serializeStallCycles 14732 # count of cycles rename stalled for serializing inst
90system.cpu.rename.RunCycles 340327979 # Number of cycles rename is running
91system.cpu.rename.UnblockCycles 145119048 # Number of cycles rename is unblocking
92system.cpu.rename.RenamedInsts 2240246263 # Number of instructions processed by rename
93system.cpu.rename.ROBFullEvents 3253 # Number of times rename has blocked due to ROB full
94system.cpu.rename.IQFullEvents 23409384 # Number of times rename has blocked due to IQ full
95system.cpu.rename.LSQFullEvents 104435988 # Number of times rename has blocked due to LSQ full
96system.cpu.rename.FullRegisterEvents 12914 # Number of times there has been no free registers
97system.cpu.rename.RenamedOperands 2886886923 # Number of destination operands rename has renamed
98system.cpu.rename.RenameLookups 6492696430 # Number of register rename lookups that rename has made
99system.cpu.rename.int_rename_lookups 6491823905 # Number of integer rename lookups
100system.cpu.rename.fp_rename_lookups 872525 # Number of floating rename lookups
101system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed
102system.cpu.rename.UndoneMaps 893809439 # Number of HB maps that are undone due to squashing
103system.cpu.rename.serializingInsts 1297 # count of serializing insts renamed
104system.cpu.rename.tempSerializingInsts 1279 # count of temporary serializing insts renamed
105system.cpu.rename.skidInsts 347581498 # count of insts added to the skid buffer
106system.cpu.memDep0.insertedLoads 540130264 # Number of loads inserted to the mem dependence unit.
107system.cpu.memDep0.insertedStores 217339026 # Number of stores inserted to the mem dependence unit.
108system.cpu.memDep0.conflictingLoads 215698631 # Number of conflicting loads.
109system.cpu.memDep0.conflictingStores 63624557 # Number of conflicting stores.
110system.cpu.iq.iqInstsAdded 2143116411 # Number of instructions added to the IQ (excludes non-spec)
111system.cpu.iq.iqNonSpecInstsAdded 61984 # Number of non-speculative instructions added to the IQ
112system.cpu.iq.iqInstsIssued 1846710444 # Number of instructions issued
113system.cpu.iq.iqSquashedInstsIssued 1594990 # Number of squashed instructions issued
114system.cpu.iq.iqSquashedInstsExamined 612455576 # Number of squashed instructions iterated over during squash; mainly for profiling
115system.cpu.iq.iqSquashedOperandsExamined 1230055220 # Number of squashed operands that are examined and possibly removed from graph
116system.cpu.iq.iqSquashedNonSpecRemoved 61431 # Number of squashed non-spec instructions that were removed
117system.cpu.iq.issued_per_cycle::samples 901432928 # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::mean 2.048639 # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::stdev 1.805034 # Number of insts issued each cycle
120system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
121system.cpu.iq.issued_per_cycle::0 246353790 27.33% 27.33% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::1 156616035 17.37% 44.70% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::2 150729220 16.72% 61.42% # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::3 147768173 16.39% 77.82% # Number of insts issued each cycle
125system.cpu.iq.issued_per_cycle::4 103385508 11.47% 89.29% # Number of insts issued each cycle
126system.cpu.iq.issued_per_cycle::5 58828894 6.53% 95.81% # Number of insts issued each cycle
127system.cpu.iq.issued_per_cycle::6 27652970 3.07% 98.88% # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::7 9059576 1.01% 99.88% # Number of insts issued each cycle
129system.cpu.iq.issued_per_cycle::8 1038762 0.12% 100.00% # Number of insts issued each cycle
130system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
131system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
132system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
133system.cpu.iq.issued_per_cycle::total 901432928 # Number of insts issued each cycle
134system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
135system.cpu.iq.fu_full::IntAlu 2653442 16.77% 16.77% # attempts to use FU when none available
136system.cpu.iq.fu_full::IntMult 0 0.00% 16.77% # attempts to use FU when none available
137system.cpu.iq.fu_full::IntDiv 0 0.00% 16.77% # attempts to use FU when none available
138system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.77% # attempts to use FU when none available
139system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.77% # attempts to use FU when none available
140system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.77% # attempts to use FU when none available
141system.cpu.iq.fu_full::FloatMult 0 0.00% 16.77% # attempts to use FU when none available
142system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.77% # attempts to use FU when none available
143system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.77% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.77% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.77% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.77% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.77% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.77% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdMult 0 0.00% 16.77% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.77% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdShift 0 0.00% 16.77% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.77% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.77% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.77% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.77% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.77% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.77% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.77% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.77% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.77% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.77% # attempts to use FU when none available
163system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
164system.cpu.iq.fu_full::MemRead 9987443 63.11% 79.88% # attempts to use FU when none available
165system.cpu.iq.fu_full::MemWrite 3184017 20.12% 100.00% # attempts to use FU when none available
166system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
167system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
168system.cpu.iq.FU_type_0::No_OpClass 2723282 0.15% 0.15% # Type of FU issued
169system.cpu.iq.FU_type_0::IntAlu 1219442774 66.03% 66.18% # Type of FU issued
170system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued
171system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued
172system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued
173system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
174system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
175system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
176system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
177system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
197system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
198system.cpu.iq.FU_type_0::MemRead 447111847 24.21% 90.39% # Type of FU issued
199system.cpu.iq.FU_type_0::MemWrite 177432541 9.61% 100.00% # Type of FU issued
200system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
201system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
202system.cpu.iq.FU_type_0::total 1846710444 # Type of FU issued
203system.cpu.iq.rate 2.007566 # Inst issue rate
204system.cpu.iq.fu_busy_cnt 15824902 # FU busy when requested
205system.cpu.iq.fu_busy_rate 0.008569 # FU busy rate (busy events/executed inst)
206system.cpu.iq.int_inst_queue_reads 4612265736 # Number of integer instruction queue reads
207system.cpu.iq.int_inst_queue_writes 2755596507 # Number of integer instruction queue writes
208system.cpu.iq.int_inst_queue_wakeup_accesses 1806213833 # Number of integer instruction queue wakeup accesses
209system.cpu.iq.fp_inst_queue_reads 7972 # Number of floating instruction queue reads
210system.cpu.iq.fp_inst_queue_writes 299756 # Number of floating instruction queue writes
211system.cpu.iq.fp_inst_queue_wakeup_accesses 262 # Number of floating instruction queue wakeup accesses
212system.cpu.iq.int_alu_accesses 1859809264 # Number of integer alu accesses
213system.cpu.iq.fp_alu_accesses 2800 # Number of floating point alu accesses
214system.cpu.iew.lsq.thread0.forwLoads 168051220 # Number of loads that had data forwarded from stores
215system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
216system.cpu.iew.lsq.thread0.squashedLoads 156028104 # Number of loads squashed
217system.cpu.iew.lsq.thread0.ignoredResponses 428762 # Number of memory responses ignored because the instruction is squashed
218system.cpu.iew.lsq.thread0.memOrderViolation 273999 # Number of memory ordering violations
219system.cpu.iew.lsq.thread0.squashedStores 68179105 # Number of stores squashed
220system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
221system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
222system.cpu.iew.lsq.thread0.rescheduledLoads 6544 # Number of loads that were rescheduled
223system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
224system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
225system.cpu.iew.iewSquashCycles 83937244 # Number of cycles IEW is squashing
226system.cpu.iew.iewBlockCycles 7052726 # Number of cycles IEW is blocking
227system.cpu.iew.iewUnblockCycles 1164788 # Number of cycles IEW is unblocking
228system.cpu.iew.iewDispatchedInsts 2143178395 # Number of instructions dispatched to IQ
229system.cpu.iew.iewDispSquashedInsts 2770813 # Number of squashed instructions skipped by dispatch
230system.cpu.iew.iewDispLoadInsts 540130264 # Number of dispatched load instructions
231system.cpu.iew.iewDispStoreInsts 217339290 # Number of dispatched store instructions
232system.cpu.iew.iewDispNonSpecInsts 5780 # Number of dispatched non-speculative instructions
233system.cpu.iew.iewIQFullEvents 918370 # Number of times the IQ has become full, causing a stall
234system.cpu.iew.iewLSQFullEvents 16344 # Number of times the LSQ has become full, causing a stall
235system.cpu.iew.memOrderViolationEvents 273999 # Number of memory order violations
236system.cpu.iew.predictedTakenIncorrect 10084956 # Number of branches that were predicted taken incorrectly
237system.cpu.iew.predictedNotTakenIncorrect 5239444 # Number of branches that were predicted not taken incorrectly
238system.cpu.iew.branchMispredicts 15324400 # Number of branch mispredicts detected at execute
239system.cpu.iew.iewExecutedInsts 1818728049 # Number of executed instructions
240system.cpu.iew.iewExecLoadInsts 438648218 # Number of load instructions executed
241system.cpu.iew.iewExecSquashedInsts 27982395 # Number of squashed instructions skipped in execute
242system.cpu.iew.exec_swp 0 # number of swp insts executed
243system.cpu.iew.exec_nop 0 # number of nop insts executed
244system.cpu.iew.exec_refs 610505515 # number of memory reference insts executed
245system.cpu.iew.exec_branches 170830738 # Number of branches executed
246system.cpu.iew.exec_stores 171857297 # Number of stores executed
247system.cpu.iew.exec_rate 1.977147 # Inst execution rate
248system.cpu.iew.wb_sent 1813502289 # cumulative count of insts sent to commit
249system.cpu.iew.wb_count 1806214095 # cumulative count of insts written-back
250system.cpu.iew.wb_producers 1379770015 # num instructions producing a value
251system.cpu.iew.wb_consumers 2939115295 # num instructions consuming a value
252system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
253system.cpu.iew.wb_rate 1.963543 # insts written-back per cycle
254system.cpu.iew.wb_fanout 0.469451 # average fanout of values written-back
255system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
256system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
257system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
258system.cpu.commit.commitSquashedInsts 614215075 # The number of squashed insts skipped by commit
259system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
260system.cpu.commit.branchMispredicts 14315916 # The number of times a branch was mispredicted
261system.cpu.commit.committed_per_cycle::samples 817495684 # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::mean 1.870333 # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::stdev 2.327982 # Number of insts commited each cycle
264system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::0 301315612 36.86% 36.86% # Number of insts commited each cycle
266system.cpu.commit.committed_per_cycle::1 204371597 25.00% 61.86% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::2 73328146 8.97% 70.83% # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::3 95079836 11.63% 82.46% # Number of insts commited each cycle
269system.cpu.commit.committed_per_cycle::4 30908814 3.78% 86.24% # Number of insts commited each cycle
270system.cpu.commit.committed_per_cycle::5 28772319 3.52% 89.76% # Number of insts commited each cycle
271system.cpu.commit.committed_per_cycle::6 16400347 2.01% 91.77% # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::7 11729678 1.43% 93.20% # Number of insts commited each cycle
273system.cpu.commit.committed_per_cycle::8 55589335 6.80% 100.00% # Number of insts commited each cycle
274system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
275system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
276system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
277system.cpu.commit.committed_per_cycle::total 817495684 # Number of insts commited each cycle
278system.cpu.commit.committedInsts 826877144 # Number of instructions committed
279system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
280system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
281system.cpu.commit.refs 533262345 # Number of memory references committed
282system.cpu.commit.loads 384102160 # Number of loads committed
283system.cpu.commit.membars 0 # Number of memory barriers committed
284system.cpu.commit.branches 149758588 # Number of branches committed
285system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
286system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
287system.cpu.commit.function_calls 0 # Number of function calls committed.
288system.cpu.commit.bw_lim_events 55589335 # number cycles where commit BW limit reached
289system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
290system.cpu.rob.rob_reads 2905110180 # The number of ROB reads
291system.cpu.rob.rob_writes 4370460169 # The number of ROB writes
292system.cpu.timesIdled 411218 # Number of times that the entire CPU went into an idle state and unscheduled itself
293system.cpu.idleCycles 18442224 # Total number of cycles that the CPU has spent unscheduled due to idling
294system.cpu.committedInsts 826877144 # Number of Instructions Simulated
295system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
296system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
297system.cpu.cpi 1.112469 # CPI: Cycles Per Instruction
298system.cpu.cpi_total 1.112469 # CPI: Total CPI of All Threads
299system.cpu.ipc 0.898901 # IPC: Instructions Per Cycle
300system.cpu.ipc_total 0.898901 # IPC: Total IPC of All Threads
301system.cpu.int_regfile_reads 4004380471 # number of integer regfile reads
302system.cpu.int_regfile_writes 2286341091 # number of integer regfile writes
303system.cpu.fp_regfile_reads 262 # number of floating regfile reads
304system.cpu.misc_regfile_reads 1001920300 # number of misc regfile reads
305system.cpu.icache.replacements 10653 # number of replacements
306system.cpu.icache.tagsinuse 997.180863 # Cycle average of tags in use
307system.cpu.icache.total_refs 183252097 # Total number of references to valid blocks.
308system.cpu.icache.sampled_refs 12174 # Sample count of references to valid blocks.
309system.cpu.icache.avg_refs 15052.743305 # Average number of references to valid blocks.
310system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
311system.cpu.icache.occ_blocks::cpu.inst 997.180863 # Average occupied blocks per requestor
312system.cpu.icache.occ_percent::cpu.inst 0.486905 # Average percentage of cache occupancy
313system.cpu.icache.occ_percent::total 0.486905 # Average percentage of cache occupancy
314system.cpu.icache.ReadReq_hits::cpu.inst 183258482 # number of ReadReq hits
315system.cpu.icache.ReadReq_hits::total 183258482 # number of ReadReq hits
316system.cpu.icache.demand_hits::cpu.inst 183258482 # number of demand (read+write) hits
317system.cpu.icache.demand_hits::total 183258482 # number of demand (read+write) hits
318system.cpu.icache.overall_hits::cpu.inst 183258482 # number of overall hits
319system.cpu.icache.overall_hits::total 183258482 # number of overall hits
320system.cpu.icache.ReadReq_misses::cpu.inst 224389 # number of ReadReq misses
321system.cpu.icache.ReadReq_misses::total 224389 # number of ReadReq misses
322system.cpu.icache.demand_misses::cpu.inst 224389 # number of demand (read+write) misses
323system.cpu.icache.demand_misses::total 224389 # number of demand (read+write) misses
324system.cpu.icache.overall_misses::cpu.inst 224389 # number of overall misses
325system.cpu.icache.overall_misses::total 224389 # number of overall misses
326system.cpu.icache.ReadReq_miss_latency::cpu.inst 1641701500 # number of ReadReq miss cycles
327system.cpu.icache.ReadReq_miss_latency::total 1641701500 # number of ReadReq miss cycles
328system.cpu.icache.demand_miss_latency::cpu.inst 1641701500 # number of demand (read+write) miss cycles
329system.cpu.icache.demand_miss_latency::total 1641701500 # number of demand (read+write) miss cycles
330system.cpu.icache.overall_miss_latency::cpu.inst 1641701500 # number of overall miss cycles
331system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles
332system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses)
333system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses
335system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses
336system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses
337system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses
338system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
|
| 339system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses
|
326system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
| 340system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
|
| 341system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses
|
327system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
| 342system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
|
| 343system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses
|
328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency
| 344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency
|
| 345system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency
|
329system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
| 346system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
|
| 347system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency
|
330system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
| 348system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
|
| 349system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency
|
331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
337system.cpu.icache.fast_writes 0 # number of fast writes performed
338system.cpu.icache.cache_copies 0 # number of cache copies performed
339system.cpu.icache.writebacks::writebacks 8 # number of writebacks
340system.cpu.icache.writebacks::total 8 # number of writebacks
341system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2536 # number of ReadReq MSHR hits
342system.cpu.icache.ReadReq_mshr_hits::total 2536 # number of ReadReq MSHR hits
343system.cpu.icache.demand_mshr_hits::cpu.inst 2536 # number of demand (read+write) MSHR hits
344system.cpu.icache.demand_mshr_hits::total 2536 # number of demand (read+write) MSHR hits
345system.cpu.icache.overall_mshr_hits::cpu.inst 2536 # number of overall MSHR hits
346system.cpu.icache.overall_mshr_hits::total 2536 # number of overall MSHR hits
347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221853 # number of ReadReq MSHR misses
348system.cpu.icache.ReadReq_mshr_misses::total 221853 # number of ReadReq MSHR misses
349system.cpu.icache.demand_mshr_misses::cpu.inst 221853 # number of demand (read+write) MSHR misses
350system.cpu.icache.demand_mshr_misses::total 221853 # number of demand (read+write) MSHR misses
351system.cpu.icache.overall_mshr_misses::cpu.inst 221853 # number of overall MSHR misses
352system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses
353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles
354system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles
355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles
356system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles
357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles
358system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles
359system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses
| 350system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
351system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
352system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
353system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
354system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
355system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
356system.cpu.icache.fast_writes 0 # number of fast writes performed
357system.cpu.icache.cache_copies 0 # number of cache copies performed
358system.cpu.icache.writebacks::writebacks 8 # number of writebacks
359system.cpu.icache.writebacks::total 8 # number of writebacks
360system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2536 # number of ReadReq MSHR hits
361system.cpu.icache.ReadReq_mshr_hits::total 2536 # number of ReadReq MSHR hits
362system.cpu.icache.demand_mshr_hits::cpu.inst 2536 # number of demand (read+write) MSHR hits
363system.cpu.icache.demand_mshr_hits::total 2536 # number of demand (read+write) MSHR hits
364system.cpu.icache.overall_mshr_hits::cpu.inst 2536 # number of overall MSHR hits
365system.cpu.icache.overall_mshr_hits::total 2536 # number of overall MSHR hits
366system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221853 # number of ReadReq MSHR misses
367system.cpu.icache.ReadReq_mshr_misses::total 221853 # number of ReadReq MSHR misses
368system.cpu.icache.demand_mshr_misses::cpu.inst 221853 # number of demand (read+write) MSHR misses
369system.cpu.icache.demand_mshr_misses::total 221853 # number of demand (read+write) MSHR misses
370system.cpu.icache.overall_mshr_misses::cpu.inst 221853 # number of overall MSHR misses
371system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses
372system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles
373system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles
374system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles
375system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles
376system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles
377system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles
378system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses
|
| 379system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses
|
360system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses
| 380system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses
|
| 381system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses
|
361system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses
| 382system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses
|
| 383system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses
|
362system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency
| 384system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency
|
| 385system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency
|
363system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
| 386system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
|
| 387system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
|
364system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
| 388system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
|
| 389system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
|
365system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
366system.cpu.dcache.replacements 2527239 # number of replacements
367system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use
368system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks.
369system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks.
370system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks.
371system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit.
372system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor
373system.cpu.dcache.occ_percent::cpu.data 0.997808 # Average percentage of cache occupancy
374system.cpu.dcache.occ_percent::total 0.997808 # Average percentage of cache occupancy
375system.cpu.dcache.ReadReq_hits::cpu.data 266287966 # number of ReadReq hits
376system.cpu.dcache.ReadReq_hits::total 266287966 # number of ReadReq hits
377system.cpu.dcache.WriteReq_hits::cpu.data 148171236 # number of WriteReq hits
378system.cpu.dcache.WriteReq_hits::total 148171236 # number of WriteReq hits
379system.cpu.dcache.demand_hits::cpu.data 414459202 # number of demand (read+write) hits
380system.cpu.dcache.demand_hits::total 414459202 # number of demand (read+write) hits
381system.cpu.dcache.overall_hits::cpu.data 414459202 # number of overall hits
382system.cpu.dcache.overall_hits::total 414459202 # number of overall hits
383system.cpu.dcache.ReadReq_misses::cpu.data 2669585 # number of ReadReq misses
384system.cpu.dcache.ReadReq_misses::total 2669585 # number of ReadReq misses
385system.cpu.dcache.WriteReq_misses::cpu.data 988965 # number of WriteReq misses
386system.cpu.dcache.WriteReq_misses::total 988965 # number of WriteReq misses
387system.cpu.dcache.demand_misses::cpu.data 3658550 # number of demand (read+write) misses
388system.cpu.dcache.demand_misses::total 3658550 # number of demand (read+write) misses
389system.cpu.dcache.overall_misses::cpu.data 3658550 # number of overall misses
390system.cpu.dcache.overall_misses::total 3658550 # number of overall misses
391system.cpu.dcache.ReadReq_miss_latency::cpu.data 39016731000 # number of ReadReq miss cycles
392system.cpu.dcache.ReadReq_miss_latency::total 39016731000 # number of ReadReq miss cycles
393system.cpu.dcache.WriteReq_miss_latency::cpu.data 20136479000 # number of WriteReq miss cycles
394system.cpu.dcache.WriteReq_miss_latency::total 20136479000 # number of WriteReq miss cycles
395system.cpu.dcache.demand_miss_latency::cpu.data 59153210000 # number of demand (read+write) miss cycles
396system.cpu.dcache.demand_miss_latency::total 59153210000 # number of demand (read+write) miss cycles
397system.cpu.dcache.overall_miss_latency::cpu.data 59153210000 # number of overall miss cycles
398system.cpu.dcache.overall_miss_latency::total 59153210000 # number of overall miss cycles
399system.cpu.dcache.ReadReq_accesses::cpu.data 268957551 # number of ReadReq accesses(hits+misses)
400system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses)
401system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
402system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
403system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses
404system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses
405system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses
406system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses
407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses
| 390system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
391system.cpu.dcache.replacements 2527239 # number of replacements
392system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use
393system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks.
394system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks.
395system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks.
396system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit.
397system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor
398system.cpu.dcache.occ_percent::cpu.data 0.997808 # Average percentage of cache occupancy
399system.cpu.dcache.occ_percent::total 0.997808 # Average percentage of cache occupancy
400system.cpu.dcache.ReadReq_hits::cpu.data 266287966 # number of ReadReq hits
401system.cpu.dcache.ReadReq_hits::total 266287966 # number of ReadReq hits
402system.cpu.dcache.WriteReq_hits::cpu.data 148171236 # number of WriteReq hits
403system.cpu.dcache.WriteReq_hits::total 148171236 # number of WriteReq hits
404system.cpu.dcache.demand_hits::cpu.data 414459202 # number of demand (read+write) hits
405system.cpu.dcache.demand_hits::total 414459202 # number of demand (read+write) hits
406system.cpu.dcache.overall_hits::cpu.data 414459202 # number of overall hits
407system.cpu.dcache.overall_hits::total 414459202 # number of overall hits
408system.cpu.dcache.ReadReq_misses::cpu.data 2669585 # number of ReadReq misses
409system.cpu.dcache.ReadReq_misses::total 2669585 # number of ReadReq misses
410system.cpu.dcache.WriteReq_misses::cpu.data 988965 # number of WriteReq misses
411system.cpu.dcache.WriteReq_misses::total 988965 # number of WriteReq misses
412system.cpu.dcache.demand_misses::cpu.data 3658550 # number of demand (read+write) misses
413system.cpu.dcache.demand_misses::total 3658550 # number of demand (read+write) misses
414system.cpu.dcache.overall_misses::cpu.data 3658550 # number of overall misses
415system.cpu.dcache.overall_misses::total 3658550 # number of overall misses
416system.cpu.dcache.ReadReq_miss_latency::cpu.data 39016731000 # number of ReadReq miss cycles
417system.cpu.dcache.ReadReq_miss_latency::total 39016731000 # number of ReadReq miss cycles
418system.cpu.dcache.WriteReq_miss_latency::cpu.data 20136479000 # number of WriteReq miss cycles
419system.cpu.dcache.WriteReq_miss_latency::total 20136479000 # number of WriteReq miss cycles
420system.cpu.dcache.demand_miss_latency::cpu.data 59153210000 # number of demand (read+write) miss cycles
421system.cpu.dcache.demand_miss_latency::total 59153210000 # number of demand (read+write) miss cycles
422system.cpu.dcache.overall_miss_latency::cpu.data 59153210000 # number of overall miss cycles
423system.cpu.dcache.overall_miss_latency::total 59153210000 # number of overall miss cycles
424system.cpu.dcache.ReadReq_accesses::cpu.data 268957551 # number of ReadReq accesses(hits+misses)
425system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses)
426system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
427system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
428system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses
429system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses
430system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses
431system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses
432system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses
|
| 433system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses
|
408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses
| 434system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses
|
| 435system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses
|
409system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses
| 436system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses
|
| 437system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses
|
410system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses
| 438system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses
|
| 439system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses
|
411system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency
| 440system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency
|
| 441system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency
|
412system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency
| 442system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency
|
| 443system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency
|
413system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
| 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
|
| 445system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency
|
414system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
| 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
|
| 447system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency
|
415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
421system.cpu.dcache.fast_writes 0 # number of fast writes performed
422system.cpu.dcache.cache_copies 0 # number of cache copies performed
423system.cpu.dcache.writebacks::writebacks 2229248 # number of writebacks
424system.cpu.dcache.writebacks::total 2229248 # number of writebacks
425system.cpu.dcache.ReadReq_mshr_hits::cpu.data 908413 # number of ReadReq MSHR hits
426system.cpu.dcache.ReadReq_mshr_hits::total 908413 # number of ReadReq MSHR hits
427system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9153 # number of WriteReq MSHR hits
428system.cpu.dcache.WriteReq_mshr_hits::total 9153 # number of WriteReq MSHR hits
429system.cpu.dcache.demand_mshr_hits::cpu.data 917566 # number of demand (read+write) MSHR hits
430system.cpu.dcache.demand_mshr_hits::total 917566 # number of demand (read+write) MSHR hits
431system.cpu.dcache.overall_mshr_hits::cpu.data 917566 # number of overall MSHR hits
432system.cpu.dcache.overall_mshr_hits::total 917566 # number of overall MSHR hits
433system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761172 # number of ReadReq MSHR misses
434system.cpu.dcache.ReadReq_mshr_misses::total 1761172 # number of ReadReq MSHR misses
435system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979812 # number of WriteReq MSHR misses
436system.cpu.dcache.WriteReq_mshr_misses::total 979812 # number of WriteReq MSHR misses
437system.cpu.dcache.demand_mshr_misses::cpu.data 2740984 # number of demand (read+write) MSHR misses
438system.cpu.dcache.demand_mshr_misses::total 2740984 # number of demand (read+write) MSHR misses
439system.cpu.dcache.overall_mshr_misses::cpu.data 2740984 # number of overall MSHR misses
440system.cpu.dcache.overall_mshr_misses::total 2740984 # number of overall MSHR misses
441system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14912272500 # number of ReadReq MSHR miss cycles
442system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles
443system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles
444system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles
445system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles
446system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles
447system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles
448system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles
449system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses
| 448system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
450system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
452system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
454system.cpu.dcache.fast_writes 0 # number of fast writes performed
455system.cpu.dcache.cache_copies 0 # number of cache copies performed
456system.cpu.dcache.writebacks::writebacks 2229248 # number of writebacks
457system.cpu.dcache.writebacks::total 2229248 # number of writebacks
458system.cpu.dcache.ReadReq_mshr_hits::cpu.data 908413 # number of ReadReq MSHR hits
459system.cpu.dcache.ReadReq_mshr_hits::total 908413 # number of ReadReq MSHR hits
460system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9153 # number of WriteReq MSHR hits
461system.cpu.dcache.WriteReq_mshr_hits::total 9153 # number of WriteReq MSHR hits
462system.cpu.dcache.demand_mshr_hits::cpu.data 917566 # number of demand (read+write) MSHR hits
463system.cpu.dcache.demand_mshr_hits::total 917566 # number of demand (read+write) MSHR hits
464system.cpu.dcache.overall_mshr_hits::cpu.data 917566 # number of overall MSHR hits
465system.cpu.dcache.overall_mshr_hits::total 917566 # number of overall MSHR hits
466system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761172 # number of ReadReq MSHR misses
467system.cpu.dcache.ReadReq_mshr_misses::total 1761172 # number of ReadReq MSHR misses
468system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979812 # number of WriteReq MSHR misses
469system.cpu.dcache.WriteReq_mshr_misses::total 979812 # number of WriteReq MSHR misses
470system.cpu.dcache.demand_mshr_misses::cpu.data 2740984 # number of demand (read+write) MSHR misses
471system.cpu.dcache.demand_mshr_misses::total 2740984 # number of demand (read+write) MSHR misses
472system.cpu.dcache.overall_mshr_misses::cpu.data 2740984 # number of overall MSHR misses
473system.cpu.dcache.overall_mshr_misses::total 2740984 # number of overall MSHR misses
474system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14912272500 # number of ReadReq MSHR miss cycles
475system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles
476system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles
477system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles
478system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles
479system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles
480system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles
481system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles
482system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses
|
| 483system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses
|
450system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses
| 484system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses
|
| 485system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses
|
451system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
| 486system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
|
| 487system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses
|
452system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
| 488system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
|
| 489system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses
|
453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency
| 490system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency
|
| 491system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency
|
454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency
| 492system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency
|
| 493system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency
|
455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
| 494system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
|
| 495system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
|
456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
| 496system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
|
| 497system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
|
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.l2cache.replacements 574865 # number of replacements
459system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use
460system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks.
461system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks.
462system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks.
463system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit.
464system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor
465system.cpu.l2cache.occ_blocks::cpu.inst 63.333478 # Average occupied blocks per requestor
466system.cpu.l2cache.occ_blocks::cpu.data 7789.592760 # Average occupied blocks per requestor
467system.cpu.l2cache.occ_percent::writebacks 0.419945 # Average percentage of cache occupancy
468system.cpu.l2cache.occ_percent::cpu.inst 0.001933 # Average percentage of cache occupancy
469system.cpu.l2cache.occ_percent::cpu.data 0.237720 # Average percentage of cache occupancy
470system.cpu.l2cache.occ_percent::total 0.659598 # Average percentage of cache occupancy
471system.cpu.l2cache.ReadReq_hits::cpu.inst 6154 # number of ReadReq hits
472system.cpu.l2cache.ReadReq_hits::cpu.data 1427336 # number of ReadReq hits
473system.cpu.l2cache.ReadReq_hits::total 1433490 # number of ReadReq hits
474system.cpu.l2cache.Writeback_hits::writebacks 2229256 # number of Writeback hits
475system.cpu.l2cache.Writeback_hits::total 2229256 # number of Writeback hits
476system.cpu.l2cache.UpgradeReq_hits::cpu.data 1290 # number of UpgradeReq hits
477system.cpu.l2cache.UpgradeReq_hits::total 1290 # number of UpgradeReq hits
478system.cpu.l2cache.ReadExReq_hits::cpu.data 524130 # number of ReadExReq hits
479system.cpu.l2cache.ReadExReq_hits::total 524130 # number of ReadExReq hits
480system.cpu.l2cache.demand_hits::cpu.inst 6154 # number of demand (read+write) hits
481system.cpu.l2cache.demand_hits::cpu.data 1951466 # number of demand (read+write) hits
482system.cpu.l2cache.demand_hits::total 1957620 # number of demand (read+write) hits
483system.cpu.l2cache.overall_hits::cpu.inst 6154 # number of overall hits
484system.cpu.l2cache.overall_hits::cpu.data 1951466 # number of overall hits
485system.cpu.l2cache.overall_hits::total 1957620 # number of overall hits
486system.cpu.l2cache.ReadReq_misses::cpu.inst 5926 # number of ReadReq misses
487system.cpu.l2cache.ReadReq_misses::cpu.data 332758 # number of ReadReq misses
488system.cpu.l2cache.ReadReq_misses::total 338684 # number of ReadReq misses
489system.cpu.l2cache.UpgradeReq_misses::cpu.data 208352 # number of UpgradeReq misses
490system.cpu.l2cache.UpgradeReq_misses::total 208352 # number of UpgradeReq misses
491system.cpu.l2cache.ReadExReq_misses::cpu.data 247027 # number of ReadExReq misses
492system.cpu.l2cache.ReadExReq_misses::total 247027 # number of ReadExReq misses
493system.cpu.l2cache.demand_misses::cpu.inst 5926 # number of demand (read+write) misses
494system.cpu.l2cache.demand_misses::cpu.data 579785 # number of demand (read+write) misses
495system.cpu.l2cache.demand_misses::total 585711 # number of demand (read+write) misses
496system.cpu.l2cache.overall_misses::cpu.inst 5926 # number of overall misses
497system.cpu.l2cache.overall_misses::cpu.data 579785 # number of overall misses
498system.cpu.l2cache.overall_misses::total 585711 # number of overall misses
499system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 203005500 # number of ReadReq miss cycles
500system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11360844500 # number of ReadReq miss cycles
501system.cpu.l2cache.ReadReq_miss_latency::total 11563850000 # number of ReadReq miss cycles
502system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9809000 # number of UpgradeReq miss cycles
503system.cpu.l2cache.UpgradeReq_miss_latency::total 9809000 # number of UpgradeReq miss cycles
504system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8462790000 # number of ReadExReq miss cycles
505system.cpu.l2cache.ReadExReq_miss_latency::total 8462790000 # number of ReadExReq miss cycles
506system.cpu.l2cache.demand_miss_latency::cpu.inst 203005500 # number of demand (read+write) miss cycles
507system.cpu.l2cache.demand_miss_latency::cpu.data 19823634500 # number of demand (read+write) miss cycles
508system.cpu.l2cache.demand_miss_latency::total 20026640000 # number of demand (read+write) miss cycles
509system.cpu.l2cache.overall_miss_latency::cpu.inst 203005500 # number of overall miss cycles
510system.cpu.l2cache.overall_miss_latency::cpu.data 19823634500 # number of overall miss cycles
511system.cpu.l2cache.overall_miss_latency::total 20026640000 # number of overall miss cycles
512system.cpu.l2cache.ReadReq_accesses::cpu.inst 12080 # number of ReadReq accesses(hits+misses)
513system.cpu.l2cache.ReadReq_accesses::cpu.data 1760094 # number of ReadReq accesses(hits+misses)
514system.cpu.l2cache.ReadReq_accesses::total 1772174 # number of ReadReq accesses(hits+misses)
515system.cpu.l2cache.Writeback_accesses::writebacks 2229256 # number of Writeback accesses(hits+misses)
516system.cpu.l2cache.Writeback_accesses::total 2229256 # number of Writeback accesses(hits+misses)
517system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209642 # number of UpgradeReq accesses(hits+misses)
518system.cpu.l2cache.UpgradeReq_accesses::total 209642 # number of UpgradeReq accesses(hits+misses)
519system.cpu.l2cache.ReadExReq_accesses::cpu.data 771157 # number of ReadExReq accesses(hits+misses)
520system.cpu.l2cache.ReadExReq_accesses::total 771157 # number of ReadExReq accesses(hits+misses)
521system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses
522system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses
523system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses
524system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses
525system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses
526system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
527system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses
528system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses
| 498system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
499system.cpu.l2cache.replacements 574865 # number of replacements
500system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use
501system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks.
502system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks.
503system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks.
504system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit.
505system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor
506system.cpu.l2cache.occ_blocks::cpu.inst 63.333478 # Average occupied blocks per requestor
507system.cpu.l2cache.occ_blocks::cpu.data 7789.592760 # Average occupied blocks per requestor
508system.cpu.l2cache.occ_percent::writebacks 0.419945 # Average percentage of cache occupancy
509system.cpu.l2cache.occ_percent::cpu.inst 0.001933 # Average percentage of cache occupancy
510system.cpu.l2cache.occ_percent::cpu.data 0.237720 # Average percentage of cache occupancy
511system.cpu.l2cache.occ_percent::total 0.659598 # Average percentage of cache occupancy
512system.cpu.l2cache.ReadReq_hits::cpu.inst 6154 # number of ReadReq hits
513system.cpu.l2cache.ReadReq_hits::cpu.data 1427336 # number of ReadReq hits
514system.cpu.l2cache.ReadReq_hits::total 1433490 # number of ReadReq hits
515system.cpu.l2cache.Writeback_hits::writebacks 2229256 # number of Writeback hits
516system.cpu.l2cache.Writeback_hits::total 2229256 # number of Writeback hits
517system.cpu.l2cache.UpgradeReq_hits::cpu.data 1290 # number of UpgradeReq hits
518system.cpu.l2cache.UpgradeReq_hits::total 1290 # number of UpgradeReq hits
519system.cpu.l2cache.ReadExReq_hits::cpu.data 524130 # number of ReadExReq hits
520system.cpu.l2cache.ReadExReq_hits::total 524130 # number of ReadExReq hits
521system.cpu.l2cache.demand_hits::cpu.inst 6154 # number of demand (read+write) hits
522system.cpu.l2cache.demand_hits::cpu.data 1951466 # number of demand (read+write) hits
523system.cpu.l2cache.demand_hits::total 1957620 # number of demand (read+write) hits
524system.cpu.l2cache.overall_hits::cpu.inst 6154 # number of overall hits
525system.cpu.l2cache.overall_hits::cpu.data 1951466 # number of overall hits
526system.cpu.l2cache.overall_hits::total 1957620 # number of overall hits
527system.cpu.l2cache.ReadReq_misses::cpu.inst 5926 # number of ReadReq misses
528system.cpu.l2cache.ReadReq_misses::cpu.data 332758 # number of ReadReq misses
529system.cpu.l2cache.ReadReq_misses::total 338684 # number of ReadReq misses
530system.cpu.l2cache.UpgradeReq_misses::cpu.data 208352 # number of UpgradeReq misses
531system.cpu.l2cache.UpgradeReq_misses::total 208352 # number of UpgradeReq misses
532system.cpu.l2cache.ReadExReq_misses::cpu.data 247027 # number of ReadExReq misses
533system.cpu.l2cache.ReadExReq_misses::total 247027 # number of ReadExReq misses
534system.cpu.l2cache.demand_misses::cpu.inst 5926 # number of demand (read+write) misses
535system.cpu.l2cache.demand_misses::cpu.data 579785 # number of demand (read+write) misses
536system.cpu.l2cache.demand_misses::total 585711 # number of demand (read+write) misses
537system.cpu.l2cache.overall_misses::cpu.inst 5926 # number of overall misses
538system.cpu.l2cache.overall_misses::cpu.data 579785 # number of overall misses
539system.cpu.l2cache.overall_misses::total 585711 # number of overall misses
540system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 203005500 # number of ReadReq miss cycles
541system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11360844500 # number of ReadReq miss cycles
542system.cpu.l2cache.ReadReq_miss_latency::total 11563850000 # number of ReadReq miss cycles
543system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9809000 # number of UpgradeReq miss cycles
544system.cpu.l2cache.UpgradeReq_miss_latency::total 9809000 # number of UpgradeReq miss cycles
545system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8462790000 # number of ReadExReq miss cycles
546system.cpu.l2cache.ReadExReq_miss_latency::total 8462790000 # number of ReadExReq miss cycles
547system.cpu.l2cache.demand_miss_latency::cpu.inst 203005500 # number of demand (read+write) miss cycles
548system.cpu.l2cache.demand_miss_latency::cpu.data 19823634500 # number of demand (read+write) miss cycles
549system.cpu.l2cache.demand_miss_latency::total 20026640000 # number of demand (read+write) miss cycles
550system.cpu.l2cache.overall_miss_latency::cpu.inst 203005500 # number of overall miss cycles
551system.cpu.l2cache.overall_miss_latency::cpu.data 19823634500 # number of overall miss cycles
552system.cpu.l2cache.overall_miss_latency::total 20026640000 # number of overall miss cycles
553system.cpu.l2cache.ReadReq_accesses::cpu.inst 12080 # number of ReadReq accesses(hits+misses)
554system.cpu.l2cache.ReadReq_accesses::cpu.data 1760094 # number of ReadReq accesses(hits+misses)
555system.cpu.l2cache.ReadReq_accesses::total 1772174 # number of ReadReq accesses(hits+misses)
556system.cpu.l2cache.Writeback_accesses::writebacks 2229256 # number of Writeback accesses(hits+misses)
557system.cpu.l2cache.Writeback_accesses::total 2229256 # number of Writeback accesses(hits+misses)
558system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209642 # number of UpgradeReq accesses(hits+misses)
559system.cpu.l2cache.UpgradeReq_accesses::total 209642 # number of UpgradeReq accesses(hits+misses)
560system.cpu.l2cache.ReadExReq_accesses::cpu.data 771157 # number of ReadExReq accesses(hits+misses)
561system.cpu.l2cache.ReadExReq_accesses::total 771157 # number of ReadExReq accesses(hits+misses)
562system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses
563system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses
564system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses
565system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses
566system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses
567system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
568system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses
569system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses
|
| 570system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses
|
529system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses
| 571system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses
|
| 572system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses
|
530system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses
| 573system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses
|
| 574system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses
|
531system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses
532system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses
| 575system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses
576system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses
|
| 577system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses
|
533system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses
534system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses
| 578system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses
579system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses
|
| 580system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses
|
535system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency
536system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency
| 581system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency
582system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency
|
| 583system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency
|
537system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency
| 584system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency
|
| 585system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency
|
538system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency
| 586system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency
|
| 587system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency
|
539system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
540system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
| 588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
|
| 590system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency
|
541system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
| 591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
|
| 593system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency
|
543system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
544system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
545system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
546system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
547system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
548system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
549system.cpu.l2cache.fast_writes 0 # number of fast writes performed
550system.cpu.l2cache.cache_copies 0 # number of cache copies performed
551system.cpu.l2cache.writebacks::writebacks 411201 # number of writebacks
552system.cpu.l2cache.writebacks::total 411201 # number of writebacks
553system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5926 # number of ReadReq MSHR misses
554system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332758 # number of ReadReq MSHR misses
555system.cpu.l2cache.ReadReq_mshr_misses::total 338684 # number of ReadReq MSHR misses
556system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208352 # number of UpgradeReq MSHR misses
557system.cpu.l2cache.UpgradeReq_mshr_misses::total 208352 # number of UpgradeReq MSHR misses
558system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247027 # number of ReadExReq MSHR misses
559system.cpu.l2cache.ReadExReq_mshr_misses::total 247027 # number of ReadExReq MSHR misses
560system.cpu.l2cache.demand_mshr_misses::cpu.inst 5926 # number of demand (read+write) MSHR misses
561system.cpu.l2cache.demand_mshr_misses::cpu.data 579785 # number of demand (read+write) MSHR misses
562system.cpu.l2cache.demand_mshr_misses::total 585711 # number of demand (read+write) MSHR misses
563system.cpu.l2cache.overall_mshr_misses::cpu.inst 5926 # number of overall MSHR misses
564system.cpu.l2cache.overall_mshr_misses::cpu.data 579785 # number of overall MSHR misses
565system.cpu.l2cache.overall_mshr_misses::total 585711 # number of overall MSHR misses
566system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183905000 # number of ReadReq MSHR miss cycles
567system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10323225500 # number of ReadReq MSHR miss cycles
568system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10507130500 # number of ReadReq MSHR miss cycles
569system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6459209000 # number of UpgradeReq MSHR miss cycles
570system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6459209000 # number of UpgradeReq MSHR miss cycles
571system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658508000 # number of ReadExReq MSHR miss cycles
572system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658508000 # number of ReadExReq MSHR miss cycles
573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles
575system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles
579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses
580system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses
| 594system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
595system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
596system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
597system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
598system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
599system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
600system.cpu.l2cache.fast_writes 0 # number of fast writes performed
601system.cpu.l2cache.cache_copies 0 # number of cache copies performed
602system.cpu.l2cache.writebacks::writebacks 411201 # number of writebacks
603system.cpu.l2cache.writebacks::total 411201 # number of writebacks
604system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5926 # number of ReadReq MSHR misses
605system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332758 # number of ReadReq MSHR misses
606system.cpu.l2cache.ReadReq_mshr_misses::total 338684 # number of ReadReq MSHR misses
607system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208352 # number of UpgradeReq MSHR misses
608system.cpu.l2cache.UpgradeReq_mshr_misses::total 208352 # number of UpgradeReq MSHR misses
609system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247027 # number of ReadExReq MSHR misses
610system.cpu.l2cache.ReadExReq_mshr_misses::total 247027 # number of ReadExReq MSHR misses
611system.cpu.l2cache.demand_mshr_misses::cpu.inst 5926 # number of demand (read+write) MSHR misses
612system.cpu.l2cache.demand_mshr_misses::cpu.data 579785 # number of demand (read+write) MSHR misses
613system.cpu.l2cache.demand_mshr_misses::total 585711 # number of demand (read+write) MSHR misses
614system.cpu.l2cache.overall_mshr_misses::cpu.inst 5926 # number of overall MSHR misses
615system.cpu.l2cache.overall_mshr_misses::cpu.data 579785 # number of overall MSHR misses
616system.cpu.l2cache.overall_mshr_misses::total 585711 # number of overall MSHR misses
617system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183905000 # number of ReadReq MSHR miss cycles
618system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10323225500 # number of ReadReq MSHR miss cycles
619system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10507130500 # number of ReadReq MSHR miss cycles
620system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6459209000 # number of UpgradeReq MSHR miss cycles
621system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6459209000 # number of UpgradeReq MSHR miss cycles
622system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658508000 # number of ReadExReq MSHR miss cycles
623system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658508000 # number of ReadExReq MSHR miss cycles
624system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles
625system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles
626system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles
627system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles
628system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles
629system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles
630system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses
631system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses
|
| 632system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses
|
581system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses
| 633system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses
|
| 634system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses
|
582system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses
| 635system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses
|
| 636system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses
|
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses
| 637system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses
638system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses
|
| 639system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses
|
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses
| 640system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses
641system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses
|
| 642system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses
|
587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency
| 643system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency
644system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency
|
| 645system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency
|
589system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency
| 646system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency
|
| 647system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency
|
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency
| 648system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency
|
| 649system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency
|
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
| 650system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
651system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
|
| 652system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
|
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
| 653system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
|
| 655system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
|
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596
597---------- End Simulation Statistics ----------
| 656system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
657
658---------- End Simulation Statistics ----------
|