1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.458202 # Number of seconds simulated
4sim_ticks 458201684000 # Number of ticks simulated
5final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 77434 # Simulator instruction rate (inst/s)
8host_op_rate 143185 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42909026 # Simulator tick rate (ticks/s)
10host_mem_usage 338808 # Number of bytes of host memory used
11host_seconds 10678.45 # Real time elapsed on the host
12sim_insts 826877109 # Number of instructions simulated
13sim_ops 1528988701 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 24476096 # Number of bytes read from this memory
16system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 201408 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 201408 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 18788864 # Number of bytes written to this memory
20system.physmem.bytes_written::total 18788864 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3147 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 382439 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 293576 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 293576 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 439562 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 53417735 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 53857297 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 439562 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 439562 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 41005663 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 41005663 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 41005663 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 385586 # Total number of read requests accepted by DRAM controller
38system.physmem.writeReqs 293576 # Total number of write requests accepted by DRAM controller
39system.physmem.readBursts 385586 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
40system.physmem.writeBursts 293576 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
41system.physmem.bytesRead 24677504 # Total number of bytes read from memory
42system.physmem.bytesWritten 18788864 # Total number of bytes written to memory
43system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize()
44system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize()
45system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by write Q
46system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed
47system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::2 24657 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::3 24489 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::4 23219 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::5 23674 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::6 24391 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::7 24210 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::8 23623 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::9 23844 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::10 24783 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::11 24073 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::12 23240 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::13 22943 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::14 23791 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::15 24001 # Track reads on a per bank basis
63system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::1 19821 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::2 18940 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::3 18905 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::5 18411 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::6 18971 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::7 18943 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::9 18119 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::10 18810 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::11 17724 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::12 17345 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::13 16945 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::14 17717 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::15 17828 # Track writes on a per bank basis
79system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
80system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry
81system.physmem.totGap 458201657000 # Total gap between requests
82system.physmem.readPktSize::0 0 # Categorize read packet sizes
83system.physmem.readPktSize::1 0 # Categorize read packet sizes
84system.physmem.readPktSize::2 0 # Categorize read packet sizes
85system.physmem.readPktSize::3 0 # Categorize read packet sizes
86system.physmem.readPktSize::4 0 # Categorize read packet sizes
87system.physmem.readPktSize::5 0 # Categorize read packet sizes
88system.physmem.readPktSize::6 385586 # Categorize read packet sizes
89system.physmem.writePktSize::0 0 # Categorize write packet sizes
90system.physmem.writePktSize::1 0 # Categorize write packet sizes
91system.physmem.writePktSize::2 0 # Categorize write packet sizes
92system.physmem.writePktSize::3 0 # Categorize write packet sizes
93system.physmem.writePktSize::4 0 # Categorize write packet sizes
94system.physmem.writePktSize::5 0 # Categorize write packet sizes
95system.physmem.writePktSize::6 293576 # Categorize write packet sizes
96system.physmem.rdQLenPdf::0 380883 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 4226 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see

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120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128system.physmem.wrQLenPdf::0 12723 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::1 12732 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::4 12740 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::5 12743 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::6 12746 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::7 12748 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 12750 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 12764 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 12764 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 12764 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 12764 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 12764 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 12764 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 12764 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 12764 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 12764 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 12764 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 12764 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 12764 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 12764 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 12764 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 42 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
160system.physmem.bytesPerActivate::samples 125877 # Bytes accessed per row activation
161system.physmem.bytesPerActivate::mean 345.228437 # Bytes accessed per row activation
162system.physmem.bytesPerActivate::gmean 161.863436 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::stdev 669.217085 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::64-65 54117 42.99% 42.99% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::128-129 23349 18.55% 61.54% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::192-193 10530 8.37% 69.91% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::256-257 6425 5.10% 75.01% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::320-321 4023 3.20% 78.21% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::384-385 2874 2.28% 80.49% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::448-449 2162 1.72% 82.21% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::512-513 1748 1.39% 83.60% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::576-577 1399 1.11% 84.71% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::640-641 1145 0.91% 85.62% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::704-705 1227 0.97% 86.59% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::768-769 1117 0.89% 87.48% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::832-833 747 0.59% 88.07% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::896-897 630 0.50% 88.57% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::960-961 615 0.49% 89.06% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1024-1025 623 0.49% 89.56% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1088-1089 541 0.43% 89.99% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1152-1153 508 0.40% 90.39% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1216-1217 588 0.47% 90.86% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1280-1281 726 0.58% 91.43% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1344-1345 627 0.50% 91.93% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1408-1409 694 0.55% 92.48% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1472-1473 6218 4.94% 97.42% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1536-1537 497 0.39% 97.82% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1600-1601 336 0.27% 98.08% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1664-1665 279 0.22% 98.31% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1728-1729 216 0.17% 98.48% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1792-1793 162 0.13% 98.61% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1856-1857 151 0.12% 98.73% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1920-1921 121 0.10% 98.82% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1984-1985 106 0.08% 98.91% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2048-2049 85 0.07% 98.97% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::2112-2113 80 0.06% 99.04% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::2176-2177 63 0.05% 99.09% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.13% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2304-2305 41 0.03% 99.16% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::2368-2369 42 0.03% 99.20% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::2432-2433 32 0.03% 99.22% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.24% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::2560-2561 20 0.02% 99.26% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::2624-2625 25 0.02% 99.28% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::2688-2689 22 0.02% 99.30% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2752-2753 23 0.02% 99.32% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.33% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2880-2881 14 0.01% 99.34% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2944-2945 22 0.02% 99.36% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::3008-3009 12 0.01% 99.37% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::3072-3073 19 0.02% 99.38% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::3136-3137 11 0.01% 99.39% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::3200-3201 20 0.02% 99.41% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::3264-3265 17 0.01% 99.42% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::3328-3329 11 0.01% 99.43% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::3392-3393 14 0.01% 99.44% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::3456-3457 8 0.01% 99.45% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.46% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::3648-3649 8 0.01% 99.47% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3712-3713 7 0.01% 99.48% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.48% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3840-3841 14 0.01% 99.49% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3904-3905 8 0.01% 99.50% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.51% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.52% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::4224-4225 3 0.00% 99.52% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::4288-4289 6 0.00% 99.53% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::4352-4353 5 0.00% 99.53% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.54% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::4480-4481 3 0.00% 99.54% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::4544-4545 5 0.00% 99.54% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.54% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4672-4673 9 0.01% 99.55% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4800-4801 9 0.01% 99.56% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.57% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4928-4929 4 0.00% 99.57% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4992-4993 4 0.00% 99.57% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::5120-5121 3 0.00% 99.58% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::5184-5185 4 0.00% 99.58% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.59% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::5376-5377 4 0.00% 99.59% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.60% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::5504-5505 8 0.01% 99.60% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.61% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.61% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::5696-5697 5 0.00% 99.61% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.61% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.62% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.62% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.63% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.63% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.63% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.64% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::6336-6337 3 0.00% 99.64% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.64% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.64% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.65% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.65% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::6656-6657 10 0.01% 99.66% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.66% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.66% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.66% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.67% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.67% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.67% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.67% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::7296-7297 5 0.00% 99.68% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::7552-7553 4 0.00% 99.68% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::7680-7681 4 0.00% 99.69% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.69% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.69% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.69% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::7936-7937 4 0.00% 99.69% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.70% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::8192-8193 377 0.30% 100.00% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::total 125877 # Bytes accessed per row activation
289system.physmem.totQLat 3046093750 # Total cycles spent in queuing delays
290system.physmem.totMemAccLat 11221540000 # Sum of mem lat for all requests
291system.physmem.totBusLat 1927185000 # Total cycles spent in databus access
292system.physmem.totBankLat 6248261250 # Total cycles spent in bank access
293system.physmem.avgQLat 7902.96 # Average queueing delay per request
294system.physmem.avgBankLat 16210.85 # Average bank access latency per request
295system.physmem.avgBusLat 5000.00 # Average bus latency per request
296system.physmem.avgMemAccLat 29113.81 # Average memory access latency
297system.physmem.avgRdBW 53.86 # Average achieved read bandwidth in MB/s
298system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s
299system.physmem.avgConsumedRdBW 53.86 # Average consumed read bandwidth in MB/s
300system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s
301system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
302system.physmem.busUtil 0.74 # Data bus utilization in percentage
303system.physmem.avgRdQLen 0.02 # Average read queue length over time
304system.physmem.avgWrQLen 9.78 # Average write queue length over time
305system.physmem.readRowHits 346233 # Number of row buffer hits during reads
306system.physmem.writeRowHits 206899 # Number of row buffer hits during writes
307system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads
308system.physmem.writeRowHitRate 70.48 # Row buffer hit rate for writes
309system.physmem.avgGap 674657.38 # Average gap between requests
310system.membus.throughput 94862960 # Throughput (bytes/s)
311system.membus.trans_dist::ReadReq 178738 # Transaction distribution
312system.membus.trans_dist::ReadResp 178738 # Transaction distribution
313system.membus.trans_dist::Writeback 293576 # Transaction distribution
314system.membus.trans_dist::UpgradeReq 131239 # Transaction distribution
315system.membus.trans_dist::UpgradeResp 131239 # Transaction distribution
316system.membus.trans_dist::ReadExReq 206848 # Transaction distribution
317system.membus.trans_dist::ReadExResp 206848 # Transaction distribution
318system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes)
319system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes)
320system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes)
321system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes)
322system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes)
323system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes)
324system.membus.data_through_bus 43466368 # Total data (bytes)
325system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
326system.membus.reqLayer0.occupancy 3389530500 # Layer occupancy (ticks)
327system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
328system.membus.respLayer1.occupancy 3902075273 # Layer occupancy (ticks)
329system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
330system.cpu.branchPred.lookups 205568854 # Number of BP lookups
331system.cpu.branchPred.condPredicted 205568854 # Number of conditional branches predicted
332system.cpu.branchPred.condIncorrect 9898045 # Number of conditional branches incorrect
333system.cpu.branchPred.BTBLookups 117107860 # Number of BTB lookups
334system.cpu.branchPred.BTBHits 114698140 # Number of BTB hits
335system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
336system.cpu.branchPred.BTBHitPct 97.942307 # BTB Hit Percentage
337system.cpu.branchPred.usedRAS 25050036 # Number of times the RAS was used to get a target.
338system.cpu.branchPred.RASInCorrect 1792384 # Number of incorrect RAS predictions.
339system.cpu.workload.num_syscalls 551 # Number of system calls
340system.cpu.numCycles 916561947 # number of cpu cycles simulated
341system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
342system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
343system.cpu.fetch.icacheStallCycles 167337624 # Number of cycles fetch is stalled on an Icache miss
344system.cpu.fetch.Insts 1131632693 # Number of instructions fetch has processed
345system.cpu.fetch.Branches 205568854 # Number of branches that fetch encountered
346system.cpu.fetch.predictedBranches 139748176 # Number of branches that fetch has predicted taken
347system.cpu.fetch.Cycles 352252174 # Number of cycles fetch has run and was not squashing or blocked
348system.cpu.fetch.SquashCycles 71070724 # Number of cycles fetch has spent squashing
349system.cpu.fetch.BlockedCycles 303559378 # Number of cycles fetch has spent blocked
350system.cpu.fetch.MiscStallCycles 48756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
351system.cpu.fetch.PendingTrapStallCycles 256407 # Number of stall cycles due to pending traps
352system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
353system.cpu.fetch.CacheLines 161987307 # Number of cache lines fetched
354system.cpu.fetch.IcacheSquashes 2533545 # Number of outstanding Icache misses that were squashed
355system.cpu.fetch.rateDist::samples 884373851 # Number of instructions fetched each cycle (Total)
356system.cpu.fetch.rateDist::mean 2.380748 # Number of instructions fetched each cycle (Total)
357system.cpu.fetch.rateDist::stdev 3.325183 # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::0 536185326 60.63% 60.63% # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::1 23385873 2.64% 63.27% # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::2 25265986 2.86% 66.13% # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.rateDist::3 27892803 3.15% 69.28% # Number of instructions fetched each cycle (Total)
363system.cpu.fetch.rateDist::4 17753666 2.01% 71.29% # Number of instructions fetched each cycle (Total)
364system.cpu.fetch.rateDist::5 22918818 2.59% 73.88% # Number of instructions fetched each cycle (Total)
365system.cpu.fetch.rateDist::6 29434810 3.33% 77.21% # Number of instructions fetched each cycle (Total)
366system.cpu.fetch.rateDist::7 26635470 3.01% 80.22% # Number of instructions fetched each cycle (Total)
367system.cpu.fetch.rateDist::8 174901099 19.78% 100.00% # Number of instructions fetched each cycle (Total)
368system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
369system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
370system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
371system.cpu.fetch.rateDist::total 884373851 # Number of instructions fetched each cycle (Total)
372system.cpu.fetch.branchRate 0.224283 # Number of branch fetches per cycle
373system.cpu.fetch.rate 1.234649 # Number of inst fetches per cycle
374system.cpu.decode.IdleCycles 222568980 # Number of cycles decode is idle
375system.cpu.decode.BlockedCycles 258608644 # Number of cycles decode is blocked
376system.cpu.decode.RunCycles 295229836 # Number of cycles decode is running
377system.cpu.decode.UnblockCycles 47046921 # Number of cycles decode is unblocking
378system.cpu.decode.SquashCycles 60919470 # Number of cycles decode is squashing
379system.cpu.decode.DecodedInsts 2071205121 # Number of instructions handled by decode
380system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
381system.cpu.rename.SquashCycles 60919470 # Number of cycles rename is squashing
382system.cpu.rename.IdleCycles 255995647 # Number of cycles rename is idle
383system.cpu.rename.BlockCycles 114297250 # Number of cycles rename is blocking
384system.cpu.rename.serializeStallCycles 16886 # count of cycles rename stalled for serializing inst
385system.cpu.rename.RunCycles 306709824 # Number of cycles rename is running
386system.cpu.rename.UnblockCycles 146434774 # Number of cycles rename is unblocking
387system.cpu.rename.RenamedInsts 2035062210 # Number of instructions processed by rename
388system.cpu.rename.ROBFullEvents 18307 # Number of times rename has blocked due to ROB full
389system.cpu.rename.IQFullEvents 24837229 # Number of times rename has blocked due to IQ full
390system.cpu.rename.LSQFullEvents 106300367 # Number of times rename has blocked due to LSQ full
391system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers
392system.cpu.rename.RenamedOperands 2137993094 # Number of destination operands rename has renamed
393system.cpu.rename.RenameLookups 5150291705 # Number of register rename lookups that rename has made
394system.cpu.rename.int_rename_lookups 5150182226 # Number of integer rename lookups
395system.cpu.rename.fp_rename_lookups 109479 # Number of floating rename lookups
396system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
397system.cpu.rename.UndoneMaps 523952240 # Number of HB maps that are undone due to squashing
398system.cpu.rename.serializingInsts 1150 # count of serializing insts renamed
399system.cpu.rename.tempSerializingInsts 1079 # count of temporary serializing insts renamed
400system.cpu.rename.skidInsts 346047502 # count of insts added to the skid buffer
401system.cpu.memDep0.insertedLoads 495816702 # Number of loads inserted to the mem dependence unit.
402system.cpu.memDep0.insertedStores 194427613 # Number of stores inserted to the mem dependence unit.
403system.cpu.memDep0.conflictingLoads 195309908 # Number of conflicting loads.
404system.cpu.memDep0.conflictingStores 54766711 # Number of conflicting stores.
405system.cpu.iq.iqInstsAdded 1975264807 # Number of instructions added to the IQ (excludes non-spec)
406system.cpu.iq.iqNonSpecInstsAdded 13440 # Number of non-speculative instructions added to the IQ
407system.cpu.iq.iqInstsIssued 1772060023 # Number of instructions issued
408system.cpu.iq.iqSquashedInstsIssued 484597 # Number of squashed instructions issued
409system.cpu.iq.iqSquashedInstsExamined 441400489 # Number of squashed instructions iterated over during squash; mainly for profiling
410system.cpu.iq.iqSquashedOperandsExamined 734643480 # Number of squashed operands that are examined and possibly removed from graph
411system.cpu.iq.iqSquashedNonSpecRemoved 12888 # Number of squashed non-spec instructions that were removed
412system.cpu.iq.issued_per_cycle::samples 884373851 # Number of insts issued each cycle
413system.cpu.iq.issued_per_cycle::mean 2.003745 # Number of insts issued each cycle
414system.cpu.iq.issued_per_cycle::stdev 1.883277 # Number of insts issued each cycle
415system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::0 267848230 30.29% 30.29% # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::1 151701849 17.15% 47.44% # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::2 137335256 15.53% 62.97% # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::3 131820581 14.91% 77.87% # Number of insts issued each cycle
420system.cpu.iq.issued_per_cycle::4 91575970 10.35% 88.23% # Number of insts issued each cycle
421system.cpu.iq.issued_per_cycle::5 56038061 6.34% 94.57% # Number of insts issued each cycle
422system.cpu.iq.issued_per_cycle::6 34420312 3.89% 98.46% # Number of insts issued each cycle
423system.cpu.iq.issued_per_cycle::7 11858874 1.34% 99.80% # Number of insts issued each cycle
424system.cpu.iq.issued_per_cycle::8 1774718 0.20% 100.00% # Number of insts issued each cycle
425system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
426system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
427system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
428system.cpu.iq.issued_per_cycle::total 884373851 # Number of insts issued each cycle
429system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
430system.cpu.iq.fu_full::IntAlu 4913366 32.39% 32.39% # attempts to use FU when none available
431system.cpu.iq.fu_full::IntMult 0 0.00% 32.39% # attempts to use FU when none available
432system.cpu.iq.fu_full::IntDiv 0 0.00% 32.39% # attempts to use FU when none available
433system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.39% # attempts to use FU when none available
434system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.39% # attempts to use FU when none available
435system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.39% # attempts to use FU when none available
436system.cpu.iq.fu_full::FloatMult 0 0.00% 32.39% # attempts to use FU when none available
437system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.39% # attempts to use FU when none available
438system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.39% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.39% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.39% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.39% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.39% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.39% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.39% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdMult 0 0.00% 32.39% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.39% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdShift 0 0.00% 32.39% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.39% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.39% # attempts to use FU when none available
450system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.39% # attempts to use FU when none available
451system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.39% # attempts to use FU when none available
452system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.39% # attempts to use FU when none available
453system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.39% # attempts to use FU when none available
454system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.39% # attempts to use FU when none available
455system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.39% # attempts to use FU when none available
456system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.39% # attempts to use FU when none available
457system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.39% # attempts to use FU when none available
458system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.39% # attempts to use FU when none available
459system.cpu.iq.fu_full::MemRead 7647346 50.41% 82.79% # attempts to use FU when none available
460system.cpu.iq.fu_full::MemWrite 2610757 17.21% 100.00% # attempts to use FU when none available
461system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
462system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
463system.cpu.iq.FU_type_0::No_OpClass 2623506 0.15% 0.15% # Type of FU issued
464system.cpu.iq.FU_type_0::IntAlu 1165695577 65.78% 65.93% # Type of FU issued
465system.cpu.iq.FU_type_0::IntMult 352860 0.02% 65.95% # Type of FU issued
466system.cpu.iq.FU_type_0::IntDiv 3880836 0.22% 66.17% # Type of FU issued
467system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued
468system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
469system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
470system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
471system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
472system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued

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485system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
486system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
487system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
488system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
489system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
490system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
491system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
492system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
493system.cpu.iq.FU_type_0::MemRead 429278718 24.22% 90.39% # Type of FU issued
494system.cpu.iq.FU_type_0::MemWrite 170228526 9.61% 100.00% # Type of FU issued
495system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
496system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
497system.cpu.iq.FU_type_0::total 1772060023 # Type of FU issued
498system.cpu.iq.rate 1.933377 # Inst issue rate
499system.cpu.iq.fu_busy_cnt 15171469 # FU busy when requested
500system.cpu.iq.fu_busy_rate 0.008561 # FU busy rate (busy events/executed inst)
501system.cpu.iq.int_inst_queue_reads 4444135081 # Number of integer instruction queue reads
502system.cpu.iq.int_inst_queue_writes 2416902562 # Number of integer instruction queue writes
503system.cpu.iq.int_inst_queue_wakeup_accesses 1744830840 # Number of integer instruction queue wakeup accesses
504system.cpu.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads
505system.cpu.iq.fp_inst_queue_writes 32680 # Number of floating instruction queue writes
506system.cpu.iq.fp_inst_queue_wakeup_accesses 3547 # Number of floating instruction queue wakeup accesses
507system.cpu.iq.int_alu_accesses 1784600923 # Number of integer alu accesses
508system.cpu.iq.fp_alu_accesses 7063 # Number of floating point alu accesses
509system.cpu.iew.lsq.thread0.forwLoads 172561564 # Number of loads that had data forwarded from stores
510system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
511system.cpu.iew.lsq.thread0.squashedLoads 111714545 # Number of loads squashed
512system.cpu.iew.lsq.thread0.ignoredResponses 391852 # Number of memory responses ignored because the instruction is squashed
513system.cpu.iew.lsq.thread0.memOrderViolation 328370 # Number of memory ordering violations
514system.cpu.iew.lsq.thread0.squashedStores 45268501 # Number of stores squashed
515system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
516system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
517system.cpu.iew.lsq.thread0.rescheduledLoads 14755 # Number of loads that were rescheduled
518system.cpu.iew.lsq.thread0.cacheBlocked 580 # Number of times an access to memory failed due to the cache being blocked
519system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
520system.cpu.iew.iewSquashCycles 60919470 # Number of cycles IEW is squashing
521system.cpu.iew.iewBlockCycles 66677729 # Number of cycles IEW is blocking
522system.cpu.iew.iewUnblockCycles 7180416 # Number of cycles IEW is unblocking
523system.cpu.iew.iewDispatchedInsts 1975278247 # Number of instructions dispatched to IQ
524system.cpu.iew.iewDispSquashedInsts 784703 # Number of squashed instructions skipped by dispatch
525system.cpu.iew.iewDispLoadInsts 495816702 # Number of dispatched load instructions
526system.cpu.iew.iewDispStoreInsts 194428687 # Number of dispatched store instructions
527system.cpu.iew.iewDispNonSpecInsts 3345 # Number of dispatched non-speculative instructions
528system.cpu.iew.iewIQFullEvents 4482902 # Number of times the IQ has become full, causing a stall
529system.cpu.iew.iewLSQFullEvents 83440 # Number of times the LSQ has become full, causing a stall
530system.cpu.iew.memOrderViolationEvents 328370 # Number of memory order violations
531system.cpu.iew.predictedTakenIncorrect 5898868 # Number of branches that were predicted taken incorrectly
532system.cpu.iew.predictedNotTakenIncorrect 4425517 # Number of branches that were predicted not taken incorrectly
533system.cpu.iew.branchMispredicts 10324385 # Number of branch mispredicts detected at execute
534system.cpu.iew.iewExecutedInsts 1752929949 # Number of executed instructions
535system.cpu.iew.iewExecLoadInsts 424141217 # Number of load instructions executed
536system.cpu.iew.iewExecSquashedInsts 19130074 # Number of squashed instructions skipped in execute
537system.cpu.iew.exec_swp 0 # number of swp insts executed
538system.cpu.iew.exec_nop 0 # number of nop insts executed
539system.cpu.iew.exec_refs 590928526 # number of memory reference insts executed
540system.cpu.iew.exec_branches 167466016 # Number of branches executed
541system.cpu.iew.exec_stores 166787309 # Number of stores executed
542system.cpu.iew.exec_rate 1.912506 # Inst execution rate
543system.cpu.iew.wb_sent 1749673980 # cumulative count of insts sent to commit
544system.cpu.iew.wb_count 1744834387 # cumulative count of insts written-back
545system.cpu.iew.wb_producers 1325007870 # num instructions producing a value
546system.cpu.iew.wb_consumers 1945707966 # num instructions consuming a value
547system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
548system.cpu.iew.wb_rate 1.903673 # insts written-back per cycle
549system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back
550system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
551system.cpu.commit.commitSquashedInsts 446317369 # The number of squashed insts skipped by commit
552system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
553system.cpu.commit.branchMispredicts 9927482 # The number of times a branch was mispredicted
554system.cpu.commit.committed_per_cycle::samples 823454381 # Number of insts commited each cycle
555system.cpu.commit.committed_per_cycle::mean 1.856798 # Number of insts commited each cycle
556system.cpu.commit.committed_per_cycle::stdev 2.436978 # Number of insts commited each cycle
557system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
558system.cpu.commit.committed_per_cycle::0 331487662 40.26% 40.26% # Number of insts commited each cycle
559system.cpu.commit.committed_per_cycle::1 193224596 23.47% 63.72% # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::2 63171510 7.67% 71.39% # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::3 92561504 11.24% 82.63% # Number of insts commited each cycle
562system.cpu.commit.committed_per_cycle::4 24941236 3.03% 85.66% # Number of insts commited each cycle
563system.cpu.commit.committed_per_cycle::5 27475920 3.34% 89.00% # Number of insts commited each cycle
564system.cpu.commit.committed_per_cycle::6 9375370 1.14% 90.14% # Number of insts commited each cycle
565system.cpu.commit.committed_per_cycle::7 11392855 1.38% 91.52% # Number of insts commited each cycle
566system.cpu.commit.committed_per_cycle::8 69823728 8.48% 100.00% # Number of insts commited each cycle
567system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
568system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
569system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
570system.cpu.commit.committed_per_cycle::total 823454381 # Number of insts commited each cycle
571system.cpu.commit.committedInsts 826877109 # Number of instructions committed
572system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
573system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
574system.cpu.commit.refs 533262343 # Number of memory references committed
575system.cpu.commit.loads 384102157 # Number of loads committed
576system.cpu.commit.membars 0 # Number of memory barriers committed
577system.cpu.commit.branches 149758583 # Number of branches committed
578system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
579system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions.
580system.cpu.commit.function_calls 17673145 # Number of function calls committed.
581system.cpu.commit.bw_lim_events 69823728 # number cycles where commit BW limit reached
582system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
583system.cpu.rob.rob_reads 2728936723 # The number of ROB reads
584system.cpu.rob.rob_writes 4011692646 # The number of ROB writes
585system.cpu.timesIdled 3353511 # Number of times that the entire CPU went into an idle state and unscheduled itself
586system.cpu.idleCycles 32188096 # Total number of cycles that the CPU has spent unscheduled due to idling
587system.cpu.committedInsts 826877109 # Number of Instructions Simulated
588system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
589system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
590system.cpu.cpi 1.108462 # CPI: Cycles Per Instruction
591system.cpu.cpi_total 1.108462 # CPI: Total CPI of All Threads
592system.cpu.ipc 0.902151 # IPC: Instructions Per Cycle
593system.cpu.ipc_total 0.902151 # IPC: Total IPC of All Threads
594system.cpu.int_regfile_reads 3313440054 # number of integer regfile reads
595system.cpu.int_regfile_writes 1825840966 # number of integer regfile writes
596system.cpu.fp_regfile_reads 3533 # number of floating regfile reads
597system.cpu.fp_regfile_writes 16 # number of floating regfile writes
598system.cpu.misc_regfile_reads 964658774 # number of misc regfile reads
599system.cpu.misc_regfile_writes 1 # number of misc regfile writes
600system.cpu.toL2Bus.throughput 698991407 # Throughput (bytes/s)
601system.cpu.toL2Bus.trans_dist::ReadReq 1901821 # Transaction distribution
602system.cpu.toL2Bus.trans_dist::ReadResp 1901820 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::Writeback 2330756 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution
608system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 146337 # Packet count per connected master and slave (bytes)
609system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7664164 # Packet count per connected master and slave (bytes)
610system.cpu.toL2Bus.pkt_count::total 7810501 # Packet count per connected master and slave (bytes)
611system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 435712 # Cumulative packet size per connected master and slave (bytes)
612system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311349248 # Cumulative packet size per connected master and slave (bytes)
613system.cpu.toL2Bus.tot_pkt_size::total 311784960 # Cumulative packet size per connected master and slave (bytes)
614system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes)
615system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes)
616system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks)
617system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
618system.cpu.toL2Bus.respLayer0.occupancy 209959241 # Layer occupancy (ticks)
619system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
620system.cpu.toL2Bus.respLayer1.occupancy 3959772656 # Layer occupancy (ticks)
621system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
622system.cpu.icache.tags.replacements 5293 # number of replacements
623system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use
624system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks.
625system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks.
626system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks.
627system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
628system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor
629system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy
630system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy
631system.cpu.icache.ReadReq_hits::cpu.inst 161845824 # number of ReadReq hits
632system.cpu.icache.ReadReq_hits::total 161845824 # number of ReadReq hits
633system.cpu.icache.demand_hits::cpu.inst 161845824 # number of demand (read+write) hits
634system.cpu.icache.demand_hits::total 161845824 # number of demand (read+write) hits
635system.cpu.icache.overall_hits::cpu.inst 161845824 # number of overall hits
636system.cpu.icache.overall_hits::total 161845824 # number of overall hits
637system.cpu.icache.ReadReq_misses::cpu.inst 141483 # number of ReadReq misses
638system.cpu.icache.ReadReq_misses::total 141483 # number of ReadReq misses
639system.cpu.icache.demand_misses::cpu.inst 141483 # number of demand (read+write) misses
640system.cpu.icache.demand_misses::total 141483 # number of demand (read+write) misses
641system.cpu.icache.overall_misses::cpu.inst 141483 # number of overall misses
642system.cpu.icache.overall_misses::total 141483 # number of overall misses
643system.cpu.icache.ReadReq_miss_latency::cpu.inst 929611982 # number of ReadReq miss cycles
644system.cpu.icache.ReadReq_miss_latency::total 929611982 # number of ReadReq miss cycles
645system.cpu.icache.demand_miss_latency::cpu.inst 929611982 # number of demand (read+write) miss cycles
646system.cpu.icache.demand_miss_latency::total 929611982 # number of demand (read+write) miss cycles
647system.cpu.icache.overall_miss_latency::cpu.inst 929611982 # number of overall miss cycles
648system.cpu.icache.overall_miss_latency::total 929611982 # number of overall miss cycles
649system.cpu.icache.ReadReq_accesses::cpu.inst 161987307 # number of ReadReq accesses(hits+misses)
650system.cpu.icache.ReadReq_accesses::total 161987307 # number of ReadReq accesses(hits+misses)
651system.cpu.icache.demand_accesses::cpu.inst 161987307 # number of demand (read+write) accesses
652system.cpu.icache.demand_accesses::total 161987307 # number of demand (read+write) accesses
653system.cpu.icache.overall_accesses::cpu.inst 161987307 # number of overall (read+write) accesses
654system.cpu.icache.overall_accesses::total 161987307 # number of overall (read+write) accesses
655system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000873 # miss rate for ReadReq accesses
656system.cpu.icache.ReadReq_miss_rate::total 0.000873 # miss rate for ReadReq accesses
657system.cpu.icache.demand_miss_rate::cpu.inst 0.000873 # miss rate for demand accesses
658system.cpu.icache.demand_miss_rate::total 0.000873 # miss rate for demand accesses
659system.cpu.icache.overall_miss_rate::cpu.inst 0.000873 # miss rate for overall accesses
660system.cpu.icache.overall_miss_rate::total 0.000873 # miss rate for overall accesses
661system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6570.485373 # average ReadReq miss latency
662system.cpu.icache.ReadReq_avg_miss_latency::total 6570.485373 # average ReadReq miss latency
663system.cpu.icache.demand_avg_miss_latency::cpu.inst 6570.485373 # average overall miss latency
664system.cpu.icache.demand_avg_miss_latency::total 6570.485373 # average overall miss latency
665system.cpu.icache.overall_avg_miss_latency::cpu.inst 6570.485373 # average overall miss latency
666system.cpu.icache.overall_avg_miss_latency::total 6570.485373 # average overall miss latency
667system.cpu.icache.blocked_cycles::no_mshrs 297 # number of cycles access was blocked
668system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
669system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
670system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
671system.cpu.icache.avg_blocked_cycles::no_mshrs 49.500000 # average number of cycles each access was blocked
672system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
673system.cpu.icache.fast_writes 0 # number of fast writes performed
674system.cpu.icache.cache_copies 0 # number of cache copies performed
675system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1954 # number of ReadReq MSHR hits
676system.cpu.icache.ReadReq_mshr_hits::total 1954 # number of ReadReq MSHR hits
677system.cpu.icache.demand_mshr_hits::cpu.inst 1954 # number of demand (read+write) MSHR hits
678system.cpu.icache.demand_mshr_hits::total 1954 # number of demand (read+write) MSHR hits
679system.cpu.icache.overall_mshr_hits::cpu.inst 1954 # number of overall MSHR hits
680system.cpu.icache.overall_mshr_hits::total 1954 # number of overall MSHR hits
681system.cpu.icache.ReadReq_mshr_misses::cpu.inst 139529 # number of ReadReq MSHR misses
682system.cpu.icache.ReadReq_mshr_misses::total 139529 # number of ReadReq MSHR misses
683system.cpu.icache.demand_mshr_misses::cpu.inst 139529 # number of demand (read+write) MSHR misses
684system.cpu.icache.demand_mshr_misses::total 139529 # number of demand (read+write) MSHR misses
685system.cpu.icache.overall_mshr_misses::cpu.inst 139529 # number of overall MSHR misses
686system.cpu.icache.overall_mshr_misses::total 139529 # number of overall MSHR misses
687system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 557299259 # number of ReadReq MSHR miss cycles
688system.cpu.icache.ReadReq_mshr_miss_latency::total 557299259 # number of ReadReq MSHR miss cycles
689system.cpu.icache.demand_mshr_miss_latency::cpu.inst 557299259 # number of demand (read+write) MSHR miss cycles
690system.cpu.icache.demand_mshr_miss_latency::total 557299259 # number of demand (read+write) MSHR miss cycles
691system.cpu.icache.overall_mshr_miss_latency::cpu.inst 557299259 # number of overall MSHR miss cycles
692system.cpu.icache.overall_mshr_miss_latency::total 557299259 # number of overall MSHR miss cycles
693system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000861 # mshr miss rate for ReadReq accesses
694system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000861 # mshr miss rate for ReadReq accesses
695system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000861 # mshr miss rate for demand accesses
696system.cpu.icache.demand_mshr_miss_rate::total 0.000861 # mshr miss rate for demand accesses
697system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000861 # mshr miss rate for overall accesses
698system.cpu.icache.overall_mshr_miss_rate::total 0.000861 # mshr miss rate for overall accesses
699system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3994.146443 # average ReadReq mshr miss latency
700system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3994.146443 # average ReadReq mshr miss latency
701system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3994.146443 # average overall mshr miss latency
702system.cpu.icache.demand_avg_mshr_miss_latency::total 3994.146443 # average overall mshr miss latency
703system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3994.146443 # average overall mshr miss latency
704system.cpu.icache.overall_avg_mshr_miss_latency::total 3994.146443 # average overall mshr miss latency
705system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
706system.cpu.l2cache.tags.replacements 352905 # number of replacements
707system.cpu.l2cache.tags.tagsinuse 29673.331814 # Cycle average of tags in use
708system.cpu.l2cache.tags.total_refs 3696859 # Total number of references to valid blocks.
709system.cpu.l2cache.tags.sampled_refs 385269 # Sample count of references to valid blocks.
710system.cpu.l2cache.tags.avg_refs 9.595527 # Average number of references to valid blocks.
711system.cpu.l2cache.tags.warmup_cycle 199076310000 # Cycle when the warmup percentage was hit.
712system.cpu.l2cache.tags.occ_blocks::writebacks 21119.362848 # Average occupied blocks per requestor
713system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.841801 # Average occupied blocks per requestor
714system.cpu.l2cache.tags.occ_blocks::cpu.data 8330.127165 # Average occupied blocks per requestor
715system.cpu.l2cache.tags.occ_percent::writebacks 0.644512 # Average percentage of cache occupancy
716system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006831 # Average percentage of cache occupancy
717system.cpu.l2cache.tags.occ_percent::cpu.data 0.254215 # Average percentage of cache occupancy
718system.cpu.l2cache.tags.occ_percent::total 0.905558 # Average percentage of cache occupancy
719system.cpu.l2cache.ReadReq_hits::cpu.inst 3661 # number of ReadReq hits
720system.cpu.l2cache.ReadReq_hits::cpu.data 1586701 # number of ReadReq hits
721system.cpu.l2cache.ReadReq_hits::total 1590362 # number of ReadReq hits
722system.cpu.l2cache.Writeback_hits::writebacks 2330756 # number of Writeback hits
723system.cpu.l2cache.Writeback_hits::total 2330756 # number of Writeback hits
724system.cpu.l2cache.UpgradeReq_hits::cpu.data 1409 # number of UpgradeReq hits
725system.cpu.l2cache.UpgradeReq_hits::total 1409 # number of UpgradeReq hits
726system.cpu.l2cache.ReadExReq_hits::cpu.data 564916 # number of ReadExReq hits
727system.cpu.l2cache.ReadExReq_hits::total 564916 # number of ReadExReq hits
728system.cpu.l2cache.demand_hits::cpu.inst 3661 # number of demand (read+write) hits
729system.cpu.l2cache.demand_hits::cpu.data 2151617 # number of demand (read+write) hits
730system.cpu.l2cache.demand_hits::total 2155278 # number of demand (read+write) hits
731system.cpu.l2cache.overall_hits::cpu.inst 3661 # number of overall hits
732system.cpu.l2cache.overall_hits::cpu.data 2151617 # number of overall hits
733system.cpu.l2cache.overall_hits::total 2155278 # number of overall hits
734system.cpu.l2cache.ReadReq_misses::cpu.inst 3148 # number of ReadReq misses
735system.cpu.l2cache.ReadReq_misses::cpu.data 175591 # number of ReadReq misses
736system.cpu.l2cache.ReadReq_misses::total 178739 # number of ReadReq misses
737system.cpu.l2cache.UpgradeReq_misses::cpu.data 131219 # number of UpgradeReq misses
738system.cpu.l2cache.UpgradeReq_misses::total 131219 # number of UpgradeReq misses
739system.cpu.l2cache.ReadExReq_misses::cpu.data 206868 # number of ReadExReq misses
740system.cpu.l2cache.ReadExReq_misses::total 206868 # number of ReadExReq misses
741system.cpu.l2cache.demand_misses::cpu.inst 3148 # number of demand (read+write) misses
742system.cpu.l2cache.demand_misses::cpu.data 382459 # number of demand (read+write) misses
743system.cpu.l2cache.demand_misses::total 385607 # number of demand (read+write) misses
744system.cpu.l2cache.overall_misses::cpu.inst 3148 # number of overall misses
745system.cpu.l2cache.overall_misses::cpu.data 382459 # number of overall misses
746system.cpu.l2cache.overall_misses::total 385607 # number of overall misses
747system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 244818000 # number of ReadReq miss cycles
748system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13237623957 # number of ReadReq miss cycles
749system.cpu.l2cache.ReadReq_miss_latency::total 13482441957 # number of ReadReq miss cycles
750system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6766209 # number of UpgradeReq miss cycles
751system.cpu.l2cache.UpgradeReq_miss_latency::total 6766209 # number of UpgradeReq miss cycles
752system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14252139980 # number of ReadExReq miss cycles
753system.cpu.l2cache.ReadExReq_miss_latency::total 14252139980 # number of ReadExReq miss cycles
754system.cpu.l2cache.demand_miss_latency::cpu.inst 244818000 # number of demand (read+write) miss cycles
755system.cpu.l2cache.demand_miss_latency::cpu.data 27489763937 # number of demand (read+write) miss cycles
756system.cpu.l2cache.demand_miss_latency::total 27734581937 # number of demand (read+write) miss cycles
757system.cpu.l2cache.overall_miss_latency::cpu.inst 244818000 # number of overall miss cycles
758system.cpu.l2cache.overall_miss_latency::cpu.data 27489763937 # number of overall miss cycles
759system.cpu.l2cache.overall_miss_latency::total 27734581937 # number of overall miss cycles
760system.cpu.l2cache.ReadReq_accesses::cpu.inst 6809 # number of ReadReq accesses(hits+misses)
761system.cpu.l2cache.ReadReq_accesses::cpu.data 1762292 # number of ReadReq accesses(hits+misses)
762system.cpu.l2cache.ReadReq_accesses::total 1769101 # number of ReadReq accesses(hits+misses)
763system.cpu.l2cache.Writeback_accesses::writebacks 2330756 # number of Writeback accesses(hits+misses)
764system.cpu.l2cache.Writeback_accesses::total 2330756 # number of Writeback accesses(hits+misses)
765system.cpu.l2cache.UpgradeReq_accesses::cpu.data 132628 # number of UpgradeReq accesses(hits+misses)
766system.cpu.l2cache.UpgradeReq_accesses::total 132628 # number of UpgradeReq accesses(hits+misses)
767system.cpu.l2cache.ReadExReq_accesses::cpu.data 771784 # number of ReadExReq accesses(hits+misses)
768system.cpu.l2cache.ReadExReq_accesses::total 771784 # number of ReadExReq accesses(hits+misses)
769system.cpu.l2cache.demand_accesses::cpu.inst 6809 # number of demand (read+write) accesses
770system.cpu.l2cache.demand_accesses::cpu.data 2534076 # number of demand (read+write) accesses
771system.cpu.l2cache.demand_accesses::total 2540885 # number of demand (read+write) accesses
772system.cpu.l2cache.overall_accesses::cpu.inst 6809 # number of overall (read+write) accesses
773system.cpu.l2cache.overall_accesses::cpu.data 2534076 # number of overall (read+write) accesses
774system.cpu.l2cache.overall_accesses::total 2540885 # number of overall (read+write) accesses
775system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462329 # miss rate for ReadReq accesses
776system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099638 # miss rate for ReadReq accesses
777system.cpu.l2cache.ReadReq_miss_rate::total 0.101034 # miss rate for ReadReq accesses
778system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989376 # miss rate for UpgradeReq accesses
779system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989376 # miss rate for UpgradeReq accesses
780system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268039 # miss rate for ReadExReq accesses
781system.cpu.l2cache.ReadExReq_miss_rate::total 0.268039 # miss rate for ReadExReq accesses
782system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462329 # miss rate for demand accesses
783system.cpu.l2cache.demand_miss_rate::cpu.data 0.150926 # miss rate for demand accesses
784system.cpu.l2cache.demand_miss_rate::total 0.151761 # miss rate for demand accesses
785system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462329 # miss rate for overall accesses
786system.cpu.l2cache.overall_miss_rate::cpu.data 0.150926 # miss rate for overall accesses
787system.cpu.l2cache.overall_miss_rate::total 0.151761 # miss rate for overall accesses
788system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77769.377382 # average ReadReq miss latency
789system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75388.966160 # average ReadReq miss latency
790system.cpu.l2cache.ReadReq_avg_miss_latency::total 75430.890611 # average ReadReq miss latency
791system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51.564248 # average UpgradeReq miss latency
792system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51.564248 # average UpgradeReq miss latency
793system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68894.850726 # average ReadExReq miss latency
794system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68894.850726 # average ReadExReq miss latency
795system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77769.377382 # average overall miss latency
796system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71876.368283 # average overall miss latency
797system.cpu.l2cache.demand_avg_miss_latency::total 71924.477349 # average overall miss latency
798system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77769.377382 # average overall miss latency
799system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71876.368283 # average overall miss latency
800system.cpu.l2cache.overall_avg_miss_latency::total 71924.477349 # average overall miss latency
801system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
802system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
803system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
804system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
805system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
806system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
807system.cpu.l2cache.fast_writes 0 # number of fast writes performed
808system.cpu.l2cache.cache_copies 0 # number of cache copies performed
809system.cpu.l2cache.writebacks::writebacks 293576 # number of writebacks
810system.cpu.l2cache.writebacks::total 293576 # number of writebacks
811system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3148 # number of ReadReq MSHR misses
812system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175591 # number of ReadReq MSHR misses
813system.cpu.l2cache.ReadReq_mshr_misses::total 178739 # number of ReadReq MSHR misses
814system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 131219 # number of UpgradeReq MSHR misses
815system.cpu.l2cache.UpgradeReq_mshr_misses::total 131219 # number of UpgradeReq MSHR misses
816system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206868 # number of ReadExReq MSHR misses
817system.cpu.l2cache.ReadExReq_mshr_misses::total 206868 # number of ReadExReq MSHR misses
818system.cpu.l2cache.demand_mshr_misses::cpu.inst 3148 # number of demand (read+write) MSHR misses
819system.cpu.l2cache.demand_mshr_misses::cpu.data 382459 # number of demand (read+write) MSHR misses
820system.cpu.l2cache.demand_mshr_misses::total 385607 # number of demand (read+write) MSHR misses
821system.cpu.l2cache.overall_mshr_misses::cpu.inst 3148 # number of overall MSHR misses
822system.cpu.l2cache.overall_mshr_misses::cpu.data 382459 # number of overall MSHR misses
823system.cpu.l2cache.overall_mshr_misses::total 385607 # number of overall MSHR misses
824system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205059000 # number of ReadReq MSHR miss cycles
825system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10984214957 # number of ReadReq MSHR miss cycles
826system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11189273957 # number of ReadReq MSHR miss cycles
827system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1316213142 # number of UpgradeReq MSHR miss cycles
828system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1316213142 # number of UpgradeReq MSHR miss cycles
829system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11623719520 # number of ReadExReq MSHR miss cycles
830system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11623719520 # number of ReadExReq MSHR miss cycles
831system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205059000 # number of demand (read+write) MSHR miss cycles
832system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22607934477 # number of demand (read+write) MSHR miss cycles
833system.cpu.l2cache.demand_mshr_miss_latency::total 22812993477 # number of demand (read+write) MSHR miss cycles
834system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205059000 # number of overall MSHR miss cycles
835system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22607934477 # number of overall MSHR miss cycles
836system.cpu.l2cache.overall_mshr_miss_latency::total 22812993477 # number of overall MSHR miss cycles
837system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for ReadReq accesses
838system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099638 # mshr miss rate for ReadReq accesses
839system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101034 # mshr miss rate for ReadReq accesses
840system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989376 # mshr miss rate for UpgradeReq accesses
841system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989376 # mshr miss rate for UpgradeReq accesses
842system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268039 # mshr miss rate for ReadExReq accesses
843system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268039 # mshr miss rate for ReadExReq accesses
844system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for demand accesses
845system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for demand accesses
846system.cpu.l2cache.demand_mshr_miss_rate::total 0.151761 # mshr miss rate for demand accesses
847system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for overall accesses
848system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for overall accesses
849system.cpu.l2cache.overall_mshr_miss_rate::total 0.151761 # mshr miss rate for overall accesses
850system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65139.453621 # average ReadReq mshr miss latency
851system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62555.683133 # average ReadReq mshr miss latency
852system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62601.189203 # average ReadReq mshr miss latency
853system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.659752 # average UpgradeReq mshr miss latency
854system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.659752 # average UpgradeReq mshr miss latency
855system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56189.065104 # average ReadExReq mshr miss latency
856system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56189.065104 # average ReadExReq mshr miss latency
857system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65139.453621 # average overall mshr miss latency
858system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency
859system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency
860system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65139.453621 # average overall mshr miss latency
861system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency
862system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency
863system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
864system.cpu.dcache.tags.replacements 2529980 # number of replacements
865system.cpu.dcache.tags.tagsinuse 4088.352551 # Cycle average of tags in use
866system.cpu.dcache.tags.total_refs 396070659 # Total number of references to valid blocks.
867system.cpu.dcache.tags.sampled_refs 2534076 # Sample count of references to valid blocks.
868system.cpu.dcache.tags.avg_refs 156.297861 # Average number of references to valid blocks.
869system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit.
870system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor
871system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy
872system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy
873system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits
874system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits
875system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits
876system.cpu.dcache.WriteReq_hits::total 148239061 # number of WriteReq hits
877system.cpu.dcache.demand_hits::cpu.data 395579138 # number of demand (read+write) hits
878system.cpu.dcache.demand_hits::total 395579138 # number of demand (read+write) hits
879system.cpu.dcache.overall_hits::cpu.data 395579138 # number of overall hits
880system.cpu.dcache.overall_hits::total 395579138 # number of overall hits
881system.cpu.dcache.ReadReq_misses::cpu.data 2863342 # number of ReadReq misses
882system.cpu.dcache.ReadReq_misses::total 2863342 # number of ReadReq misses
883system.cpu.dcache.WriteReq_misses::cpu.data 921141 # number of WriteReq misses
884system.cpu.dcache.WriteReq_misses::total 921141 # number of WriteReq misses
885system.cpu.dcache.demand_misses::cpu.data 3784483 # number of demand (read+write) misses
886system.cpu.dcache.demand_misses::total 3784483 # number of demand (read+write) misses
887system.cpu.dcache.overall_misses::cpu.data 3784483 # number of overall misses
888system.cpu.dcache.overall_misses::total 3784483 # number of overall misses
889system.cpu.dcache.ReadReq_miss_latency::cpu.data 57420164907 # number of ReadReq miss cycles
890system.cpu.dcache.ReadReq_miss_latency::total 57420164907 # number of ReadReq miss cycles
891system.cpu.dcache.WriteReq_miss_latency::cpu.data 25863644657 # number of WriteReq miss cycles
892system.cpu.dcache.WriteReq_miss_latency::total 25863644657 # number of WriteReq miss cycles
893system.cpu.dcache.demand_miss_latency::cpu.data 83283809564 # number of demand (read+write) miss cycles
894system.cpu.dcache.demand_miss_latency::total 83283809564 # number of demand (read+write) miss cycles
895system.cpu.dcache.overall_miss_latency::cpu.data 83283809564 # number of overall miss cycles
896system.cpu.dcache.overall_miss_latency::total 83283809564 # number of overall miss cycles
897system.cpu.dcache.ReadReq_accesses::cpu.data 250203419 # number of ReadReq accesses(hits+misses)
898system.cpu.dcache.ReadReq_accesses::total 250203419 # number of ReadReq accesses(hits+misses)
899system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
900system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
901system.cpu.dcache.demand_accesses::cpu.data 399363621 # number of demand (read+write) accesses
902system.cpu.dcache.demand_accesses::total 399363621 # number of demand (read+write) accesses
903system.cpu.dcache.overall_accesses::cpu.data 399363621 # number of overall (read+write) accesses
904system.cpu.dcache.overall_accesses::total 399363621 # number of overall (read+write) accesses
905system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses
906system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses
907system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006176 # miss rate for WriteReq accesses
908system.cpu.dcache.WriteReq_miss_rate::total 0.006176 # miss rate for WriteReq accesses
909system.cpu.dcache.demand_miss_rate::cpu.data 0.009476 # miss rate for demand accesses
910system.cpu.dcache.demand_miss_rate::total 0.009476 # miss rate for demand accesses
911system.cpu.dcache.overall_miss_rate::cpu.data 0.009476 # miss rate for overall accesses
912system.cpu.dcache.overall_miss_rate::total 0.009476 # miss rate for overall accesses
913system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.547535 # average ReadReq miss latency
914system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.547535 # average ReadReq miss latency
915system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28077.834617 # average WriteReq miss latency
916system.cpu.dcache.WriteReq_avg_miss_latency::total 28077.834617 # average WriteReq miss latency
917system.cpu.dcache.demand_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency
918system.cpu.dcache.demand_avg_miss_latency::total 22006.654427 # average overall miss latency
919system.cpu.dcache.overall_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency
920system.cpu.dcache.overall_avg_miss_latency::total 22006.654427 # average overall miss latency
921system.cpu.dcache.blocked_cycles::no_mshrs 7199 # number of cycles access was blocked
922system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
923system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked
924system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
925system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.571219 # average number of cycles each access was blocked
926system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
927system.cpu.dcache.fast_writes 0 # number of fast writes performed
928system.cpu.dcache.cache_copies 0 # number of cache copies performed
929system.cpu.dcache.writebacks::writebacks 2330756 # number of writebacks
930system.cpu.dcache.writebacks::total 2330756 # number of writebacks
931system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100793 # number of ReadReq MSHR hits
932system.cpu.dcache.ReadReq_mshr_hits::total 1100793 # number of ReadReq MSHR hits
933system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16986 # number of WriteReq MSHR hits
934system.cpu.dcache.WriteReq_mshr_hits::total 16986 # number of WriteReq MSHR hits
935system.cpu.dcache.demand_mshr_hits::cpu.data 1117779 # number of demand (read+write) MSHR hits
936system.cpu.dcache.demand_mshr_hits::total 1117779 # number of demand (read+write) MSHR hits
937system.cpu.dcache.overall_mshr_hits::cpu.data 1117779 # number of overall MSHR hits
938system.cpu.dcache.overall_mshr_hits::total 1117779 # number of overall MSHR hits
939system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762549 # number of ReadReq MSHR misses
940system.cpu.dcache.ReadReq_mshr_misses::total 1762549 # number of ReadReq MSHR misses
941system.cpu.dcache.WriteReq_mshr_misses::cpu.data 904155 # number of WriteReq MSHR misses
942system.cpu.dcache.WriteReq_mshr_misses::total 904155 # number of WriteReq MSHR misses
943system.cpu.dcache.demand_mshr_misses::cpu.data 2666704 # number of demand (read+write) MSHR misses
944system.cpu.dcache.demand_mshr_misses::total 2666704 # number of demand (read+write) MSHR misses
945system.cpu.dcache.overall_mshr_misses::cpu.data 2666704 # number of overall MSHR misses
946system.cpu.dcache.overall_mshr_misses::total 2666704 # number of overall MSHR misses
947system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30902624251 # number of ReadReq MSHR miss cycles
948system.cpu.dcache.ReadReq_mshr_miss_latency::total 30902624251 # number of ReadReq MSHR miss cycles
949system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23743181593 # number of WriteReq MSHR miss cycles
950system.cpu.dcache.WriteReq_mshr_miss_latency::total 23743181593 # number of WriteReq MSHR miss cycles
951system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54645805844 # number of demand (read+write) MSHR miss cycles
952system.cpu.dcache.demand_mshr_miss_latency::total 54645805844 # number of demand (read+write) MSHR miss cycles
953system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54645805844 # number of overall MSHR miss cycles
954system.cpu.dcache.overall_mshr_miss_latency::total 54645805844 # number of overall MSHR miss cycles
955system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses
956system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses
957system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006062 # mshr miss rate for WriteReq accesses
958system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006062 # mshr miss rate for WriteReq accesses
959system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for demand accesses
960system.cpu.dcache.demand_mshr_miss_rate::total 0.006677 # mshr miss rate for demand accesses
961system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for overall accesses
962system.cpu.dcache.overall_mshr_miss_rate::total 0.006677 # mshr miss rate for overall accesses
963system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17532.916390 # average ReadReq mshr miss latency
964system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17532.916390 # average ReadReq mshr miss latency
965system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26260.078850 # average WriteReq mshr miss latency
966system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26260.078850 # average WriteReq mshr miss latency
967system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency
968system.cpu.dcache.demand_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency
969system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency
970system.cpu.dcache.overall_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency
971system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
972
973---------- End Simulation Statistics ----------