1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.459938 # Number of seconds simulated
4sim_ticks 459937575500 # Number of ticks simulated
5final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 75971 # Simulator instruction rate (inst/s)
8host_op_rate 140479 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42257715 # Simulator tick rate (ticks/s)
10host_mem_usage 287264 # Number of bytes of host memory used
11host_seconds 10884.11 # Real time elapsed on the host
12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 37483008 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 26316864 # Number of bytes written to this memory
17system.physmem.num_reads 585672 # Number of read requests responded to by this memory
18system.physmem.num_writes 411201 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.workload.num_syscalls 551 # Number of system calls
25system.cpu.numCycles 919875152 # number of cpu cycles simulated
26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
28system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups
29system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted
30system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect
31system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups
--- 286 unchanged lines hidden (view full) ---
318system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles
319system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses)
321system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses
322system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses
323system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses
324system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses
325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
326system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
327system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency
329system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
330system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
337system.cpu.icache.fast_writes 0 # number of fast writes performed
338system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 13 unchanged lines hidden (view full) ---
352system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses
353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles
354system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles
355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles
356system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles
357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles
358system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles
359system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses
360system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses
361system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses
362system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency
363system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
364system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
365system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
366system.cpu.dcache.replacements 2527239 # number of replacements
367system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use
368system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks.
369system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks.
370system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks.
371system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit.
372system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
400system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses)
401system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
402system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
403system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses
404system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses
405system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses
406system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses
407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses
408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses
409system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses
410system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses
411system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency
412system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency
413system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
414system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
421system.cpu.dcache.fast_writes 0 # number of fast writes performed
422system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 19 unchanged lines hidden (view full) ---
442system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles
443system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles
444system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles
445system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles
446system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles
447system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles
448system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles
449system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses
450system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses
451system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
452system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency
454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency
455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.l2cache.replacements 574865 # number of replacements
459system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use
460system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks.
461system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks.
462system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks.
463system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit.
464system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor
--- 56 unchanged lines hidden (view full) ---
521system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses
522system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses
523system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses
524system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses
525system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses
526system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
527system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses
528system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses
529system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses
530system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses
531system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses
532system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses
533system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses
534system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses
535system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency
536system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency
537system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency
538system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency
539system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
540system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
541system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
543system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
544system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
545system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
546system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
547system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
548system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
549system.cpu.l2cache.fast_writes 0 # number of fast writes performed
550system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 22 unchanged lines hidden (view full) ---
573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles
575system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles
579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses
580system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses
581system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses
582system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses
587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency
589system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596
597---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.459938 # Number of seconds simulated
4sim_ticks 459937575500 # Number of ticks simulated
5final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 75971 # Simulator instruction rate (inst/s)
8host_op_rate 140479 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42257715 # Simulator tick rate (ticks/s)
10host_mem_usage 287264 # Number of bytes of host memory used
11host_seconds 10884.11 # Real time elapsed on the host
12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 37483008 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 26316864 # Number of bytes written to this memory
17system.physmem.num_reads 585672 # Number of read requests responded to by this memory
18system.physmem.num_writes 411201 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.workload.num_syscalls 551 # Number of system calls
25system.cpu.numCycles 919875152 # number of cpu cycles simulated
26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
28system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups
29system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted
30system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect
31system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups
--- 286 unchanged lines hidden (view full) ---
318system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles
319system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses)
321system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses
322system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses
323system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses
324system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses
325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
326system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
327system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency
329system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
330system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
337system.cpu.icache.fast_writes 0 # number of fast writes performed
338system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 13 unchanged lines hidden (view full) ---
352system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses
353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles
354system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles
355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles
356system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles
357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles
358system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles
359system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses
360system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses
361system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses
362system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency
363system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
364system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
365system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
366system.cpu.dcache.replacements 2527239 # number of replacements
367system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use
368system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks.
369system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks.
370system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks.
371system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit.
372system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
400system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses)
401system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
402system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
403system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses
404system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses
405system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses
406system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses
407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses
408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses
409system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses
410system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses
411system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency
412system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency
413system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
414system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
421system.cpu.dcache.fast_writes 0 # number of fast writes performed
422system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 19 unchanged lines hidden (view full) ---
442system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles
443system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles
444system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles
445system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles
446system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles
447system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles
448system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles
449system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses
450system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses
451system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
452system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency
454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency
455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.l2cache.replacements 574865 # number of replacements
459system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use
460system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks.
461system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks.
462system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks.
463system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit.
464system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor
--- 56 unchanged lines hidden (view full) ---
521system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses
522system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses
523system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses
524system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses
525system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses
526system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
527system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses
528system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses
529system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses
530system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses
531system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses
532system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses
533system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses
534system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses
535system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency
536system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency
537system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency
538system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency
539system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
540system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
541system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
543system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
544system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
545system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
546system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
547system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
548system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
549system.cpu.l2cache.fast_writes 0 # number of fast writes performed
550system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 22 unchanged lines hidden (view full) ---
573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles
575system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles
579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses
580system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses
581system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses
582system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses
587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency
589system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596
597---------- End Simulation Statistics ----------