1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.487015 # Number of seconds simulated
4sim_ticks 487015166000 # Number of ticks simulated
5final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 149671 # Simulator instruction rate (inst/s)
8host_op_rate 276966 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 88156571 # Simulator tick rate (ticks/s)
10host_mem_usage 323840 # Number of bytes of host memory used
11host_seconds 5524.43 # Real time elapsed on the host
12sim_insts 826847303 # Number of instructions simulated
13sim_ops 1530082520 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 154176 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 24645952 # Number of bytes read from this memory
19system.physmem.bytes_read::total 24800128 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 154176 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 154176 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 18907840 # Number of bytes written to this memory
23system.physmem.bytes_written::total 18907840 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 2409 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 385093 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 387502 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 295435 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 295435 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 316573 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 50606128 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 50922702 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 316573 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 316573 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 38823924 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 38823924 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 38823924 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 316573 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 50606128 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 89746626 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.readReqs 387502 # Number of read requests accepted
41system.physmem.writeReqs 295435 # Number of write requests accepted
42system.physmem.readBursts 387502 # Number of DRAM read bursts, including those serviced by the write queue
43system.physmem.writeBursts 295435 # Number of DRAM write bursts, including those merged in the write queue
44system.physmem.bytesReadDRAM 24780416 # Total number of bytes read from DRAM
45system.physmem.bytesReadWrQ 19712 # Total number of bytes read from write queue
46system.physmem.bytesWritten 18906304 # Total number of bytes written to DRAM
47system.physmem.bytesReadSys 24800128 # Total read bytes from the system interface side
48system.physmem.bytesWrittenSys 18907840 # Total written bytes from the system interface side
49system.physmem.servicedByWrQ 308 # Number of DRAM read bursts serviced by the write queue
50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
52system.physmem.perBankRdBursts::0 24677 # Per bank write bursts
53system.physmem.perBankRdBursts::1 26454 # Per bank write bursts
54system.physmem.perBankRdBursts::2 24704 # Per bank write bursts
55system.physmem.perBankRdBursts::3 24551 # Per bank write bursts
56system.physmem.perBankRdBursts::4 23256 # Per bank write bursts
57system.physmem.perBankRdBursts::5 23627 # Per bank write bursts
58system.physmem.perBankRdBursts::6 24680 # Per bank write bursts
59system.physmem.perBankRdBursts::7 24455 # Per bank write bursts
60system.physmem.perBankRdBursts::8 23806 # Per bank write bursts
61system.physmem.perBankRdBursts::9 23529 # Per bank write bursts
62system.physmem.perBankRdBursts::10 24814 # Per bank write bursts
63system.physmem.perBankRdBursts::11 23994 # Per bank write bursts
64system.physmem.perBankRdBursts::12 23307 # Per bank write bursts
65system.physmem.perBankRdBursts::13 23001 # Per bank write bursts
66system.physmem.perBankRdBursts::14 24016 # Per bank write bursts
67system.physmem.perBankRdBursts::15 24323 # Per bank write bursts
68system.physmem.perBankWrBursts::0 19004 # Per bank write bursts
69system.physmem.perBankWrBursts::1 19961 # Per bank write bursts
70system.physmem.perBankWrBursts::2 19032 # Per bank write bursts
71system.physmem.perBankWrBursts::3 19001 # Per bank write bursts
72system.physmem.perBankWrBursts::4 18129 # Per bank write bursts
73system.physmem.perBankWrBursts::5 18443 # Per bank write bursts
74system.physmem.perBankWrBursts::6 19167 # Per bank write bursts
75system.physmem.perBankWrBursts::7 19127 # Per bank write bursts
76system.physmem.perBankWrBursts::8 18708 # Per bank write bursts
77system.physmem.perBankWrBursts::9 17947 # Per bank write bursts
78system.physmem.perBankWrBursts::10 18897 # Per bank write bursts
79system.physmem.perBankWrBursts::11 17782 # Per bank write bursts
80system.physmem.perBankWrBursts::12 17420 # Per bank write bursts
81system.physmem.perBankWrBursts::13 16998 # Per bank write bursts
82system.physmem.perBankWrBursts::14 17822 # Per bank write bursts
83system.physmem.perBankWrBursts::15 17973 # Per bank write bursts
84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
86system.physmem.totGap 487015078500 # Total gap between requests
87system.physmem.readPktSize::0 0 # Read request sizes (log2)
88system.physmem.readPktSize::1 0 # Read request sizes (log2)
89system.physmem.readPktSize::2 0 # Read request sizes (log2)
90system.physmem.readPktSize::3 0 # Read request sizes (log2)
91system.physmem.readPktSize::4 0 # Read request sizes (log2)
92system.physmem.readPktSize::5 0 # Read request sizes (log2)
93system.physmem.readPktSize::6 387502 # Read request sizes (log2)
94system.physmem.writePktSize::0 0 # Write request sizes (log2)
95system.physmem.writePktSize::1 0 # Write request sizes (log2)
96system.physmem.writePktSize::2 0 # Write request sizes (log2)
97system.physmem.writePktSize::3 0 # Write request sizes (log2)
98system.physmem.writePktSize::4 0 # Write request sizes (log2)
99system.physmem.writePktSize::5 0 # Write request sizes (log2)
100system.physmem.writePktSize::6 295435 # Write request sizes (log2)
101system.physmem.rdQLenPdf::0 381038 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 5759 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

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140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::15 6008 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::16 6294 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::17 17484 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::18 17673 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::20 17693 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::21 17697 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::22 17692 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::23 17694 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::24 17700 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::25 17696 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::26 17699 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::27 17704 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::28 17708 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::30 17805 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::31 17713 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::32 17722 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see

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189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
197system.physmem.bytesPerActivate::samples 146349 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::mean 298.501363 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::gmean 176.437841 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::stdev 325.145824 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::0-127 53058 36.25% 36.25% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::128-255 40951 27.98% 64.24% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::256-383 13535 9.25% 73.48% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::384-511 7606 5.20% 78.68% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::512-639 5054 3.45% 82.14% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::640-767 3741 2.56% 84.69% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::768-895 2872 1.96% 86.65% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::896-1023 2862 1.96% 88.61% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::1024-1151 16670 11.39% 100.00% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::total 146349 # Bytes accessed per row activation
211system.physmem.rdPerTurnAround::samples 17683 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::mean 21.896002 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::gmean 18.141977 # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::stdev 216.215491 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::0-1023 17677 99.97% 99.97% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 17683 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 17683 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 16.705932 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 16.678736 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 0.966667 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16 11382 64.37% 64.37% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::17 280 1.58% 65.95% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::18 5890 33.31% 99.26% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::19 116 0.66% 99.92% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::20 11 0.06% 99.98% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::21 2 0.01% 99.99% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::total 17683 # Writes before turning the bus around for reads
235system.physmem.totQLat 9773520500 # Total ticks spent queuing
236system.physmem.totMemAccLat 17033408000 # Total ticks spent from burst creation until serviced by the DRAM
237system.physmem.totBusLat 1935970000 # Total ticks spent in databus transfers
238system.physmem.avgQLat 25241.92 # Average queueing delay per DRAM burst
239system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
240system.physmem.avgMemAccLat 43991.92 # Average memory access latency per DRAM burst
241system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s
242system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s
243system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s
244system.physmem.avgWrBWSys 38.82 # Average system write bandwidth in MiByte/s
245system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
246system.physmem.busUtil 0.70 # Data bus utilization in percentage
247system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads
248system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes
249system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
250system.physmem.avgWrQLen 20.86 # Average write queue length when enqueuing
251system.physmem.readRowHits 316194 # Number of row buffer hits during reads
252system.physmem.writeRowHits 220049 # Number of row buffer hits during writes
253system.physmem.readRowHitRate 81.66 # Row buffer hit rate for reads
254system.physmem.writeRowHitRate 74.48 # Row buffer hit rate for writes
255system.physmem.avgGap 713118.60 # Average gap between requests
256system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined
257system.physmem_0.actEnergy 536506740 # Energy for activate commands per rank (pJ)
258system.physmem_0.preEnergy 285137325 # Energy for precharge commands per rank (pJ)
259system.physmem_0.readEnergy 1402324560 # Energy for read commands per rank (pJ)
260system.physmem_0.writeEnergy 792730080 # Energy for write commands per rank (pJ)
261system.physmem_0.refreshEnergy 13527611760.000004 # Energy for refresh commands per rank (pJ)
262system.physmem_0.actBackEnergy 8827375680 # Energy for active background per rank (pJ)
263system.physmem_0.preBackEnergy 730358400 # Energy for precharge background per rank (pJ)
264system.physmem_0.actPowerDownEnergy 36195677160 # Energy for active power-down per rank (pJ)
265system.physmem_0.prePowerDownEnergy 16995876480 # Energy for precharge power-down per rank (pJ)
266system.physmem_0.selfRefreshEnergy 84126324885 # Energy for self refresh per rank (pJ)
267system.physmem_0.totalEnergy 163425034830 # Total energy per rank (pJ)
268system.physmem_0.averagePower 335.564568 # Core power per rank (mW)
269system.physmem_0.totalIdleTime 465742918500 # Total Idle time Per DRAM Rank
270system.physmem_0.memoryStateTime::IDLE 1151920500 # Time in different power states
271system.physmem_0.memoryStateTime::REF 5744978000 # Time in different power states
272system.physmem_0.memoryStateTime::SREF 342106910750 # Time in different power states
273system.physmem_0.memoryStateTime::PRE_PDN 44260034250 # Time in different power states
274system.physmem_0.memoryStateTime::ACT 14374729750 # Time in different power states
275system.physmem_0.memoryStateTime::ACT_PDN 79376592750 # Time in different power states
276system.physmem_1.actEnergy 508517940 # Energy for activate commands per rank (pJ)
277system.physmem_1.preEnergy 270257130 # Energy for precharge commands per rank (pJ)
278system.physmem_1.readEnergy 1362240600 # Energy for read commands per rank (pJ)
279system.physmem_1.writeEnergy 749315340 # Energy for write commands per rank (pJ)
280system.physmem_1.refreshEnergy 13073392800.000004 # Energy for refresh commands per rank (pJ)
281system.physmem_1.actBackEnergy 8818641570 # Energy for active background per rank (pJ)
282system.physmem_1.preBackEnergy 720149760 # Energy for precharge background per rank (pJ)
283system.physmem_1.actPowerDownEnergy 34369694130 # Energy for active power-down per rank (pJ)
284system.physmem_1.prePowerDownEnergy 16456043520 # Energy for precharge power-down per rank (pJ)
285system.physmem_1.selfRefreshEnergy 85412982225 # Energy for self refresh per rank (pJ)
286system.physmem_1.totalEnergy 161745926205 # Total energy per rank (pJ)
287system.physmem_1.averagePower 332.116816 # Core power per rank (mW)
288system.physmem_1.totalIdleTime 465789870750 # Total Idle time Per DRAM Rank
289system.physmem_1.memoryStateTime::IDLE 1150076250 # Time in different power states
290system.physmem_1.memoryStateTime::REF 5552712000 # Time in different power states
291system.physmem_1.memoryStateTime::SREF 347563722250 # Time in different power states
292system.physmem_1.memoryStateTime::PRE_PDN 42854288750 # Time in different power states
293system.physmem_1.memoryStateTime::ACT 14522378750 # Time in different power states
294system.physmem_1.memoryStateTime::ACT_PDN 75371988000 # Time in different power states
295system.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
296system.cpu.branchPred.lookups 298029097 # Number of BP lookups
297system.cpu.branchPred.condPredicted 298029097 # Number of conditional branches predicted
298system.cpu.branchPred.condIncorrect 23616389 # Number of conditional branches incorrect
299system.cpu.branchPred.BTBLookups 229942542 # Number of BTB lookups
300system.cpu.branchPred.BTBHits 0 # Number of BTB hits
301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
302system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
303system.cpu.branchPred.usedRAS 40333391 # Number of times the RAS was used to get a target.
304system.cpu.branchPred.RASInCorrect 4390674 # Number of incorrect RAS predictions.
305system.cpu.branchPred.indirectLookups 229942542 # Number of indirect predictor lookups.
306system.cpu.branchPred.indirectHits 119860888 # Number of indirect target hits.
307system.cpu.branchPred.indirectMisses 110081654 # Number of indirect misses.
308system.cpu.branchPredindirectMispredicted 11613915 # Number of mispredicted indirect branches.
309system.cpu_clk_domain.clock 500 # Clock period in ticks
310system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
311system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
312system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
313system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
314system.cpu.workload.num_syscalls 551 # Number of system calls
315system.cpu.pwrStateResidencyTicks::ON 487015166000 # Cumulative time (in ticks) in various power states
316system.cpu.numCycles 974030333 # number of cpu cycles simulated
317system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
318system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
319system.cpu.fetch.icacheStallCycles 229618225 # Number of cycles fetch is stalled on an Icache miss
320system.cpu.fetch.Insts 1587637398 # Number of instructions fetch has processed
321system.cpu.fetch.Branches 298029097 # Number of branches that fetch encountered
322system.cpu.fetch.predictedBranches 160194279 # Number of branches that fetch has predicted taken
323system.cpu.fetch.Cycles 719695482 # Number of cycles fetch has run and was not squashing or blocked
324system.cpu.fetch.SquashCycles 48136797 # Number of cycles fetch has spent squashing
325system.cpu.fetch.TlbCycles 1337 # Number of cycles fetch has spent waiting for tlb
326system.cpu.fetch.MiscStallCycles 32063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
327system.cpu.fetch.PendingTrapStallCycles 398708 # Number of stall cycles due to pending traps
328system.cpu.fetch.PendingQuiesceStallCycles 8912 # Number of stall cycles due to pending quiesce instructions
329system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR
330system.cpu.fetch.CacheLines 216378015 # Number of cache lines fetched
331system.cpu.fetch.IcacheSquashes 6307023 # Number of outstanding Icache misses that were squashed
332system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed
333system.cpu.fetch.rateDist::samples 973823159 # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.rateDist::mean 3.052791 # Number of instructions fetched each cycle (Total)
335system.cpu.fetch.rateDist::stdev 3.491297 # Number of instructions fetched each cycle (Total)
336system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::0 482221410 49.52% 49.52% # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::1 36458558 3.74% 53.26% # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::2 36184065 3.72% 56.98% # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::3 33102262 3.40% 60.38% # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::4 28599787 2.94% 63.31% # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::5 29969705 3.08% 66.39% # Number of instructions fetched each cycle (Total)
343system.cpu.fetch.rateDist::6 40168402 4.12% 70.52% # Number of instructions fetched each cycle (Total)
344system.cpu.fetch.rateDist::7 37465076 3.85% 74.36% # Number of instructions fetched each cycle (Total)
345system.cpu.fetch.rateDist::8 249653894 25.64% 100.00% # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
349system.cpu.fetch.rateDist::total 973823159 # Number of instructions fetched each cycle (Total)
350system.cpu.fetch.branchRate 0.305975 # Number of branch fetches per cycle
351system.cpu.fetch.rate 1.629967 # Number of inst fetches per cycle
352system.cpu.decode.IdleCycles 165565722 # Number of cycles decode is idle
353system.cpu.decode.BlockedCycles 390830119 # Number of cycles decode is blocked
354system.cpu.decode.RunCycles 312240973 # Number of cycles decode is running
355system.cpu.decode.UnblockCycles 81117947 # Number of cycles decode is unblocking
356system.cpu.decode.SquashCycles 24068398 # Number of cycles decode is squashing
357system.cpu.decode.DecodedInsts 2744223716 # Number of instructions handled by decode
358system.cpu.rename.SquashCycles 24068398 # Number of cycles rename is squashing
359system.cpu.rename.IdleCycles 201650614 # Number of cycles rename is idle
360system.cpu.rename.BlockCycles 200101577 # Number of cycles rename is blocking
361system.cpu.rename.serializeStallCycles 12340 # count of cycles rename stalled for serializing inst
362system.cpu.rename.RunCycles 351328141 # Number of cycles rename is running
363system.cpu.rename.UnblockCycles 196662089 # Number of cycles rename is unblocking
364system.cpu.rename.RenamedInsts 2626762649 # Number of instructions processed by rename
365system.cpu.rename.ROBFullEvents 653926 # Number of times rename has blocked due to ROB full
366system.cpu.rename.IQFullEvents 121379246 # Number of times rename has blocked due to IQ full
367system.cpu.rename.LQFullEvents 22369281 # Number of times rename has blocked due to LQ full
368system.cpu.rename.SQFullEvents 44360312 # Number of times rename has blocked due to SQ full
369system.cpu.rename.RenamedOperands 2707190257 # Number of destination operands rename has renamed
370system.cpu.rename.RenameLookups 6592545635 # Number of register rename lookups that rename has made
371system.cpu.rename.int_rename_lookups 4207329612 # Number of integer rename lookups
372system.cpu.rename.fp_rename_lookups 2546306 # Number of floating rename lookups
373system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed
374system.cpu.rename.UndoneMaps 1090228685 # Number of HB maps that are undone due to squashing
375system.cpu.rename.serializingInsts 1055 # count of serializing insts renamed
376system.cpu.rename.tempSerializingInsts 956 # count of temporary serializing insts renamed
377system.cpu.rename.skidInsts 369291247 # count of insts added to the skid buffer
378system.cpu.memDep0.insertedLoads 608349007 # Number of loads inserted to the mem dependence unit.
379system.cpu.memDep0.insertedStores 244126939 # Number of stores inserted to the mem dependence unit.
380system.cpu.memDep0.conflictingLoads 253380233 # Number of conflicting loads.
381system.cpu.memDep0.conflictingStores 76614927 # Number of conflicting stores.
382system.cpu.iq.iqInstsAdded 2419683470 # Number of instructions added to the IQ (excludes non-spec)
383system.cpu.iq.iqNonSpecInstsAdded 114601 # Number of non-speculative instructions added to the IQ
384system.cpu.iq.iqInstsIssued 1999301644 # Number of instructions issued
385system.cpu.iq.iqSquashedInstsIssued 3644555 # Number of squashed instructions issued
386system.cpu.iq.iqSquashedInstsExamined 889715551 # Number of squashed instructions iterated over during squash; mainly for profiling
387system.cpu.iq.iqSquashedOperandsExamined 1510079207 # Number of squashed operands that are examined and possibly removed from graph
388system.cpu.iq.iqSquashedNonSpecRemoved 114049 # Number of squashed non-spec instructions that were removed
389system.cpu.iq.issued_per_cycle::samples 973823159 # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::mean 2.053044 # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::stdev 2.105688 # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::0 345234545 35.45% 35.45% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::1 135418864 13.91% 49.36% # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::2 129821558 13.33% 62.69% # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::3 119307207 12.25% 74.94% # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::4 97554322 10.02% 84.96% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::5 67238440 6.90% 91.86% # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::6 45741413 4.70% 96.56% # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::7 22594403 2.32% 98.88% # Number of insts issued each cycle
401system.cpu.iq.issued_per_cycle::8 10912407 1.12% 100.00% # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle
406system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
407system.cpu.iq.fu_full::IntAlu 11212757 43.19% 43.19% # attempts to use FU when none available
408system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available
409system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available
410system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available
411system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.19% # attempts to use FU when none available
412system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.19% # attempts to use FU when none available
413system.cpu.iq.fu_full::FloatMult 0 0.00% 43.19% # attempts to use FU when none available
414system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available
415system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.19% # attempts to use FU when none available

--- 14 unchanged lines hidden (view full) ---

430system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.19% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.19% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.19% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.19% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available
438system.cpu.iq.fu_full::MemRead 11924633 45.93% 89.11% # attempts to use FU when none available
439system.cpu.iq.fu_full::MemWrite 2727831 10.51% 99.62% # attempts to use FU when none available
440system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.62% # attempts to use FU when none available
441system.cpu.iq.fu_full::FloatMemWrite 98893 0.38% 100.00% # attempts to use FU when none available
442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
444system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued
445system.cpu.iq.FU_type_0::IntAlu 1333663160 66.71% 66.85% # Type of FU issued
446system.cpu.iq.FU_type_0::IntMult 357468 0.02% 66.87% # Type of FU issued
447system.cpu.iq.FU_type_0::IntDiv 4798486 0.24% 67.11% # Type of FU issued
448system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Type of FU issued
449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued
450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued
451system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued
452system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued
454system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued
455system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued

--- 6 unchanged lines hidden (view full) ---

468system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued
476system.cpu.iq.FU_type_0::MemRead 471201643 23.57% 90.68% # Type of FU issued
477system.cpu.iq.FU_type_0::MemWrite 185912277 9.30% 99.98% # Type of FU issued
478system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued
479system.cpu.iq.FU_type_0::FloatMemWrite 453578 0.02% 100.00% # Type of FU issued
480system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
481system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
482system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued
483system.cpu.iq.rate 2.052607 # Inst issue rate
484system.cpu.iq.fu_busy_cnt 25964114 # FU busy when requested
485system.cpu.iq.fu_busy_rate 0.012987 # FU busy rate (busy events/executed inst)
486system.cpu.iq.int_inst_queue_reads 5000734134 # Number of integer instruction queue reads
487system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes
488system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses
489system.cpu.iq.fp_inst_queue_reads 1300982 # Number of floating instruction queue reads
490system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes
491system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses
492system.cpu.iq.int_alu_accesses 2021798255 # Number of integer alu accesses
493system.cpu.iq.fp_alu_accesses 552483 # Number of floating point alu accesses
494system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores
495system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
496system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed
497system.cpu.iew.lsq.thread0.ignoredResponses 337750 # Number of memory responses ignored because the instruction is squashed
498system.cpu.iew.lsq.thread0.memOrderViolation 639215 # Number of memory ordering violations
499system.cpu.iew.lsq.thread0.squashedStores 94968744 # Number of stores squashed
500system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
501system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
502system.cpu.iew.lsq.thread0.rescheduledLoads 31938 # Number of loads that were rescheduled
503system.cpu.iew.lsq.thread0.cacheBlocked 869 # Number of times an access to memory failed due to the cache being blocked
504system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
505system.cpu.iew.iewSquashCycles 24068398 # Number of cycles IEW is squashing
506system.cpu.iew.iewBlockCycles 149571445 # Number of cycles IEW is blocking
507system.cpu.iew.iewUnblockCycles 6693651 # Number of cycles IEW is unblocking
508system.cpu.iew.iewDispatchedInsts 2419798071 # Number of instructions dispatched to IQ
509system.cpu.iew.iewDispSquashedInsts 1305719 # Number of squashed instructions skipped by dispatch
510system.cpu.iew.iewDispLoadInsts 608349109 # Number of dispatched load instructions
511system.cpu.iew.iewDispStoreInsts 244126939 # Number of dispatched store instructions
512system.cpu.iew.iewDispNonSpecInsts 39730 # Number of dispatched non-speculative instructions
513system.cpu.iew.iewIQFullEvents 1462244 # Number of times the IQ has become full, causing a stall
514system.cpu.iew.iewLSQFullEvents 4395107 # Number of times the LSQ has become full, causing a stall
515system.cpu.iew.memOrderViolationEvents 639215 # Number of memory order violations
516system.cpu.iew.predictedTakenIncorrect 8704418 # Number of branches that were predicted taken incorrectly
517system.cpu.iew.predictedNotTakenIncorrect 20695714 # Number of branches that were predicted not taken incorrectly
518system.cpu.iew.branchMispredicts 29400132 # Number of branch mispredicts detected at execute
519system.cpu.iew.iewExecutedInsts 1945833568 # Number of executed instructions
520system.cpu.iew.iewExecLoadInsts 456792637 # Number of load instructions executed
521system.cpu.iew.iewExecSquashedInsts 53468076 # Number of squashed instructions skipped in execute
522system.cpu.iew.exec_swp 0 # number of swp insts executed
523system.cpu.iew.exec_nop 0 # number of nop insts executed
524system.cpu.iew.exec_refs 635592905 # number of memory reference insts executed
525system.cpu.iew.exec_branches 185215439 # Number of branches executed
526system.cpu.iew.exec_stores 178800268 # Number of stores executed
527system.cpu.iew.exec_rate 1.997714 # Inst execution rate
528system.cpu.iew.wb_sent 1934717341 # cumulative count of insts sent to commit
529system.cpu.iew.wb_count 1924191844 # cumulative count of insts written-back
530system.cpu.iew.wb_producers 1457208218 # num instructions producing a value
531system.cpu.iew.wb_consumers 2204046368 # num instructions consuming a value
532system.cpu.iew.wb_rate 1.975495 # insts written-back per cycle
533system.cpu.iew.wb_fanout 0.661151 # average fanout of values written-back
534system.cpu.commit.commitSquashedInsts 889791004 # The number of squashed insts skipped by commit
535system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
536system.cpu.commit.branchMispredicts 23647177 # The number of times a branch was mispredicted
537system.cpu.commit.committed_per_cycle::samples 841074000 # Number of insts commited each cycle
538system.cpu.commit.committed_per_cycle::mean 1.819201 # Number of insts commited each cycle
539system.cpu.commit.committed_per_cycle::stdev 2.458814 # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::0 361210845 42.95% 42.95% # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::1 184795052 21.97% 64.92% # Number of insts commited each cycle
543system.cpu.commit.committed_per_cycle::2 57840397 6.88% 71.79% # Number of insts commited each cycle
544system.cpu.commit.committed_per_cycle::3 87376864 10.39% 82.18% # Number of insts commited each cycle
545system.cpu.commit.committed_per_cycle::4 30415751 3.62% 85.80% # Number of insts commited each cycle
546system.cpu.commit.committed_per_cycle::5 26609914 3.16% 88.96% # Number of insts commited each cycle
547system.cpu.commit.committed_per_cycle::6 10385763 1.23% 90.20% # Number of insts commited each cycle
548system.cpu.commit.committed_per_cycle::7 9066382 1.08% 91.28% # Number of insts commited each cycle
549system.cpu.commit.committed_per_cycle::8 73373032 8.72% 100.00% # Number of insts commited each cycle
550system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
551system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
552system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
553system.cpu.commit.committed_per_cycle::total 841074000 # Number of insts commited each cycle
554system.cpu.commit.committedInsts 826847303 # Number of instructions committed
555system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed
556system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
557system.cpu.commit.refs 533241508 # Number of memory references committed
558system.cpu.commit.loads 384083313 # Number of loads committed
559system.cpu.commit.membars 0 # Number of memory barriers committed
560system.cpu.commit.branches 149981740 # Number of branches committed
561system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.

--- 33 unchanged lines hidden (view full) ---

595system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction
596system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction
597system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction
598system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
599system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
600system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
601system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
602system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction
603system.cpu.commit.bw_lim_events 73373032 # number cycles where commit BW limit reached
604system.cpu.rob.rob_reads 3187574492 # The number of ROB reads
605system.cpu.rob.rob_writes 4974168269 # The number of ROB writes
606system.cpu.timesIdled 2040 # Number of times that the entire CPU went into an idle state and unscheduled itself
607system.cpu.idleCycles 207174 # Total number of cycles that the CPU has spent unscheduled due to idling
608system.cpu.committedInsts 826847303 # Number of Instructions Simulated
609system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated
610system.cpu.cpi 1.178005 # CPI: Cycles Per Instruction
611system.cpu.cpi_total 1.178005 # CPI: Total CPI of All Threads
612system.cpu.ipc 0.848893 # IPC: Instructions Per Cycle
613system.cpu.ipc_total 0.848893 # IPC: Total IPC of All Threads
614system.cpu.int_regfile_reads 2928663805 # number of integer regfile reads
615system.cpu.int_regfile_writes 1576907134 # number of integer regfile writes
616system.cpu.fp_regfile_reads 239166 # number of floating regfile reads
617system.cpu.fp_regfile_writes 5 # number of floating regfile writes
618system.cpu.cc_regfile_reads 617952960 # number of cc regfile reads
619system.cpu.cc_regfile_writes 419967877 # number of cc regfile writes
620system.cpu.misc_regfile_reads 1064297744 # number of misc regfile reads
621system.cpu.misc_regfile_writes 1 # number of misc regfile writes
622system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
623system.cpu.dcache.tags.replacements 2546002 # number of replacements
624system.cpu.dcache.tags.tagsinuse 4087.987212 # Cycle average of tags in use
625system.cpu.dcache.tags.total_refs 420920584 # Total number of references to valid blocks.
626system.cpu.dcache.tags.sampled_refs 2550098 # Sample count of references to valid blocks.
627system.cpu.dcache.tags.avg_refs 165.060552 # Average number of references to valid blocks.
628system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit.
629system.cpu.dcache.tags.occ_blocks::cpu.data 4087.987212 # Average occupied blocks per requestor
630system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy
631system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy
632system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
633system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
634system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
635system.cpu.dcache.tags.age_task_id_blocks_1024::2 600 # Occupied blocks per task id
636system.cpu.dcache.tags.age_task_id_blocks_1024::3 3453 # Occupied blocks per task id
637system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
638system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
639system.cpu.dcache.tags.tag_accesses 851091222 # Number of tag accesses
640system.cpu.dcache.tags.data_accesses 851091222 # Number of data accesses
641system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
642system.cpu.dcache.ReadReq_hits::cpu.data 272551011 # number of ReadReq hits
643system.cpu.dcache.ReadReq_hits::total 272551011 # number of ReadReq hits
644system.cpu.dcache.WriteReq_hits::cpu.data 148366737 # number of WriteReq hits
645system.cpu.dcache.WriteReq_hits::total 148366737 # number of WriteReq hits
646system.cpu.dcache.demand_hits::cpu.data 420917748 # number of demand (read+write) hits
647system.cpu.dcache.demand_hits::total 420917748 # number of demand (read+write) hits
648system.cpu.dcache.overall_hits::cpu.data 420917748 # number of overall hits
649system.cpu.dcache.overall_hits::total 420917748 # number of overall hits
650system.cpu.dcache.ReadReq_misses::cpu.data 2561340 # number of ReadReq misses
651system.cpu.dcache.ReadReq_misses::total 2561340 # number of ReadReq misses
652system.cpu.dcache.WriteReq_misses::cpu.data 791474 # number of WriteReq misses
653system.cpu.dcache.WriteReq_misses::total 791474 # number of WriteReq misses
654system.cpu.dcache.demand_misses::cpu.data 3352814 # number of demand (read+write) misses
655system.cpu.dcache.demand_misses::total 3352814 # number of demand (read+write) misses
656system.cpu.dcache.overall_misses::cpu.data 3352814 # number of overall misses
657system.cpu.dcache.overall_misses::total 3352814 # number of overall misses
658system.cpu.dcache.ReadReq_miss_latency::cpu.data 63063270500 # number of ReadReq miss cycles
659system.cpu.dcache.ReadReq_miss_latency::total 63063270500 # number of ReadReq miss cycles
660system.cpu.dcache.WriteReq_miss_latency::cpu.data 26380612500 # number of WriteReq miss cycles
661system.cpu.dcache.WriteReq_miss_latency::total 26380612500 # number of WriteReq miss cycles
662system.cpu.dcache.demand_miss_latency::cpu.data 89443883000 # number of demand (read+write) miss cycles
663system.cpu.dcache.demand_miss_latency::total 89443883000 # number of demand (read+write) miss cycles
664system.cpu.dcache.overall_miss_latency::cpu.data 89443883000 # number of overall miss cycles
665system.cpu.dcache.overall_miss_latency::total 89443883000 # number of overall miss cycles
666system.cpu.dcache.ReadReq_accesses::cpu.data 275112351 # number of ReadReq accesses(hits+misses)
667system.cpu.dcache.ReadReq_accesses::total 275112351 # number of ReadReq accesses(hits+misses)
668system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
669system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
670system.cpu.dcache.demand_accesses::cpu.data 424270562 # number of demand (read+write) accesses
671system.cpu.dcache.demand_accesses::total 424270562 # number of demand (read+write) accesses
672system.cpu.dcache.overall_accesses::cpu.data 424270562 # number of overall (read+write) accesses
673system.cpu.dcache.overall_accesses::total 424270562 # number of overall (read+write) accesses
674system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses
675system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses
676system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses
677system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses
678system.cpu.dcache.demand_miss_rate::cpu.data 0.007903 # miss rate for demand accesses
679system.cpu.dcache.demand_miss_rate::total 0.007903 # miss rate for demand accesses
680system.cpu.dcache.overall_miss_rate::cpu.data 0.007903 # miss rate for overall accesses
681system.cpu.dcache.overall_miss_rate::total 0.007903 # miss rate for overall accesses
682system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24621.202378 # average ReadReq miss latency
683system.cpu.dcache.ReadReq_avg_miss_latency::total 24621.202378 # average ReadReq miss latency
684system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33330.990658 # average WriteReq miss latency
685system.cpu.dcache.WriteReq_avg_miss_latency::total 33330.990658 # average WriteReq miss latency
686system.cpu.dcache.demand_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency
687system.cpu.dcache.demand_avg_miss_latency::total 26677.257671 # average overall miss latency
688system.cpu.dcache.overall_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency
689system.cpu.dcache.overall_avg_miss_latency::total 26677.257671 # average overall miss latency
690system.cpu.dcache.blocked_cycles::no_mshrs 10639 # number of cycles access was blocked
691system.cpu.dcache.blocked_cycles::no_targets 11942 # number of cycles access was blocked
692system.cpu.dcache.blocked::no_mshrs 928 # number of cycles access was blocked
693system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
694system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.464440 # average number of cycles each access was blocked
695system.cpu.dcache.avg_blocked_cycles::no_targets 918.615385 # average number of cycles each access was blocked
696system.cpu.dcache.writebacks::writebacks 2338096 # number of writebacks
697system.cpu.dcache.writebacks::total 2338096 # number of writebacks
698system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794970 # number of ReadReq MSHR hits
699system.cpu.dcache.ReadReq_mshr_hits::total 794970 # number of ReadReq MSHR hits
700system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5921 # number of WriteReq MSHR hits
701system.cpu.dcache.WriteReq_mshr_hits::total 5921 # number of WriteReq MSHR hits
702system.cpu.dcache.demand_mshr_hits::cpu.data 800891 # number of demand (read+write) MSHR hits
703system.cpu.dcache.demand_mshr_hits::total 800891 # number of demand (read+write) MSHR hits
704system.cpu.dcache.overall_mshr_hits::cpu.data 800891 # number of overall MSHR hits
705system.cpu.dcache.overall_mshr_hits::total 800891 # number of overall MSHR hits
706system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766370 # number of ReadReq MSHR misses
707system.cpu.dcache.ReadReq_mshr_misses::total 1766370 # number of ReadReq MSHR misses
708system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785553 # number of WriteReq MSHR misses
709system.cpu.dcache.WriteReq_mshr_misses::total 785553 # number of WriteReq MSHR misses
710system.cpu.dcache.demand_mshr_misses::cpu.data 2551923 # number of demand (read+write) MSHR misses
711system.cpu.dcache.demand_mshr_misses::total 2551923 # number of demand (read+write) MSHR misses
712system.cpu.dcache.overall_mshr_misses::cpu.data 2551923 # number of overall MSHR misses
713system.cpu.dcache.overall_mshr_misses::total 2551923 # number of overall MSHR misses
714system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37596158000 # number of ReadReq MSHR miss cycles
715system.cpu.dcache.ReadReq_mshr_miss_latency::total 37596158000 # number of ReadReq MSHR miss cycles
716system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25486712000 # number of WriteReq MSHR miss cycles
717system.cpu.dcache.WriteReq_mshr_miss_latency::total 25486712000 # number of WriteReq MSHR miss cycles
718system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63082870000 # number of demand (read+write) MSHR miss cycles
719system.cpu.dcache.demand_mshr_miss_latency::total 63082870000 # number of demand (read+write) MSHR miss cycles
720system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63082870000 # number of overall MSHR miss cycles
721system.cpu.dcache.overall_mshr_miss_latency::total 63082870000 # number of overall MSHR miss cycles
722system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses
723system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses
724system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses
725system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses
726system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses
727system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses
728system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses
729system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses
730system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21284.418327 # average ReadReq mshr miss latency
731system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21284.418327 # average ReadReq mshr miss latency
732system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32444.293383 # average WriteReq mshr miss latency
733system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32444.293383 # average WriteReq mshr miss latency
734system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency
735system.cpu.dcache.demand_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency
736system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency
737system.cpu.dcache.overall_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency
738system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
739system.cpu.icache.tags.replacements 3937 # number of replacements
740system.cpu.icache.tags.tagsinuse 1075.833508 # Cycle average of tags in use
741system.cpu.icache.tags.total_refs 216367909 # Total number of references to valid blocks.
742system.cpu.icache.tags.sampled_refs 5646 # Sample count of references to valid blocks.
743system.cpu.icache.tags.avg_refs 38322.335990 # Average number of references to valid blocks.
744system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
745system.cpu.icache.tags.occ_blocks::cpu.inst 1075.833508 # Average occupied blocks per requestor
746system.cpu.icache.tags.occ_percent::cpu.inst 0.525309 # Average percentage of cache occupancy
747system.cpu.icache.tags.occ_percent::total 0.525309 # Average percentage of cache occupancy
748system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id
749system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
750system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
751system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
752system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id
753system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id
754system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id
755system.cpu.icache.tags.tag_accesses 432763508 # Number of tag accesses
756system.cpu.icache.tags.data_accesses 432763508 # Number of data accesses
757system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
758system.cpu.icache.ReadReq_hits::cpu.inst 216368192 # number of ReadReq hits
759system.cpu.icache.ReadReq_hits::total 216368192 # number of ReadReq hits
760system.cpu.icache.demand_hits::cpu.inst 216368192 # number of demand (read+write) hits
761system.cpu.icache.demand_hits::total 216368192 # number of demand (read+write) hits
762system.cpu.icache.overall_hits::cpu.inst 216368192 # number of overall hits
763system.cpu.icache.overall_hits::total 216368192 # number of overall hits
764system.cpu.icache.ReadReq_misses::cpu.inst 9822 # number of ReadReq misses
765system.cpu.icache.ReadReq_misses::total 9822 # number of ReadReq misses
766system.cpu.icache.demand_misses::cpu.inst 9822 # number of demand (read+write) misses
767system.cpu.icache.demand_misses::total 9822 # number of demand (read+write) misses
768system.cpu.icache.overall_misses::cpu.inst 9822 # number of overall misses
769system.cpu.icache.overall_misses::total 9822 # number of overall misses
770system.cpu.icache.ReadReq_miss_latency::cpu.inst 562018500 # number of ReadReq miss cycles
771system.cpu.icache.ReadReq_miss_latency::total 562018500 # number of ReadReq miss cycles
772system.cpu.icache.demand_miss_latency::cpu.inst 562018500 # number of demand (read+write) miss cycles
773system.cpu.icache.demand_miss_latency::total 562018500 # number of demand (read+write) miss cycles
774system.cpu.icache.overall_miss_latency::cpu.inst 562018500 # number of overall miss cycles
775system.cpu.icache.overall_miss_latency::total 562018500 # number of overall miss cycles
776system.cpu.icache.ReadReq_accesses::cpu.inst 216378014 # number of ReadReq accesses(hits+misses)
777system.cpu.icache.ReadReq_accesses::total 216378014 # number of ReadReq accesses(hits+misses)
778system.cpu.icache.demand_accesses::cpu.inst 216378014 # number of demand (read+write) accesses
779system.cpu.icache.demand_accesses::total 216378014 # number of demand (read+write) accesses
780system.cpu.icache.overall_accesses::cpu.inst 216378014 # number of overall (read+write) accesses
781system.cpu.icache.overall_accesses::total 216378014 # number of overall (read+write) accesses
782system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
783system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
784system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
785system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
786system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
787system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
788system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57220.372633 # average ReadReq miss latency
789system.cpu.icache.ReadReq_avg_miss_latency::total 57220.372633 # average ReadReq miss latency
790system.cpu.icache.demand_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency
791system.cpu.icache.demand_avg_miss_latency::total 57220.372633 # average overall miss latency
792system.cpu.icache.overall_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency
793system.cpu.icache.overall_avg_miss_latency::total 57220.372633 # average overall miss latency
794system.cpu.icache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
795system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
796system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
797system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
798system.cpu.icache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked
799system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
800system.cpu.icache.writebacks::writebacks 3937 # number of writebacks
801system.cpu.icache.writebacks::total 3937 # number of writebacks
802system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2342 # number of ReadReq MSHR hits
803system.cpu.icache.ReadReq_mshr_hits::total 2342 # number of ReadReq MSHR hits
804system.cpu.icache.demand_mshr_hits::cpu.inst 2342 # number of demand (read+write) MSHR hits
805system.cpu.icache.demand_mshr_hits::total 2342 # number of demand (read+write) MSHR hits
806system.cpu.icache.overall_mshr_hits::cpu.inst 2342 # number of overall MSHR hits
807system.cpu.icache.overall_mshr_hits::total 2342 # number of overall MSHR hits
808system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7480 # number of ReadReq MSHR misses
809system.cpu.icache.ReadReq_mshr_misses::total 7480 # number of ReadReq MSHR misses
810system.cpu.icache.demand_mshr_misses::cpu.inst 7480 # number of demand (read+write) MSHR misses
811system.cpu.icache.demand_mshr_misses::total 7480 # number of demand (read+write) MSHR misses
812system.cpu.icache.overall_mshr_misses::cpu.inst 7480 # number of overall MSHR misses
813system.cpu.icache.overall_mshr_misses::total 7480 # number of overall MSHR misses
814system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 378895000 # number of ReadReq MSHR miss cycles
815system.cpu.icache.ReadReq_mshr_miss_latency::total 378895000 # number of ReadReq MSHR miss cycles
816system.cpu.icache.demand_mshr_miss_latency::cpu.inst 378895000 # number of demand (read+write) MSHR miss cycles
817system.cpu.icache.demand_mshr_miss_latency::total 378895000 # number of demand (read+write) MSHR miss cycles
818system.cpu.icache.overall_mshr_miss_latency::cpu.inst 378895000 # number of overall MSHR miss cycles
819system.cpu.icache.overall_mshr_miss_latency::total 378895000 # number of overall MSHR miss cycles
820system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for ReadReq accesses
821system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000035 # mshr miss rate for ReadReq accesses
822system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for demand accesses
823system.cpu.icache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
824system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for overall accesses
825system.cpu.icache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
826system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50654.411765 # average ReadReq mshr miss latency
827system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50654.411765 # average ReadReq mshr miss latency
828system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency
829system.cpu.icache.demand_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency
830system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency
831system.cpu.icache.overall_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency
832system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
833system.cpu.l2cache.tags.replacements 355911 # number of replacements
834system.cpu.l2cache.tags.tagsinuse 30630.560827 # Cycle average of tags in use
835system.cpu.l2cache.tags.total_refs 4712762 # Total number of references to valid blocks.
836system.cpu.l2cache.tags.sampled_refs 388679 # Sample count of references to valid blocks.
837system.cpu.l2cache.tags.avg_refs 12.125075 # Average number of references to valid blocks.
838system.cpu.l2cache.tags.warmup_cycle 82947046000 # Cycle when the warmup percentage was hit.
839system.cpu.l2cache.tags.occ_blocks::writebacks 71.927824 # Average occupied blocks per requestor
840system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.909939 # Average occupied blocks per requestor
841system.cpu.l2cache.tags.occ_blocks::cpu.data 30366.723064 # Average occupied blocks per requestor
842system.cpu.l2cache.tags.occ_percent::writebacks 0.002195 # Average percentage of cache occupancy
843system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005857 # Average percentage of cache occupancy
844system.cpu.l2cache.tags.occ_percent::cpu.data 0.926719 # Average percentage of cache occupancy
845system.cpu.l2cache.tags.occ_percent::total 0.934771 # Average percentage of cache occupancy
846system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
847system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
848system.cpu.l2cache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id
849system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1402 # Occupied blocks per task id
850system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31132 # Occupied blocks per task id
851system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
852system.cpu.l2cache.tags.tag_accesses 41200319 # Number of tag accesses
853system.cpu.l2cache.tags.data_accesses 41200319 # Number of data accesses
854system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
855system.cpu.l2cache.WritebackDirty_hits::writebacks 2338096 # number of WritebackDirty hits
856system.cpu.l2cache.WritebackDirty_hits::total 2338096 # number of WritebackDirty hits
857system.cpu.l2cache.WritebackClean_hits::writebacks 3847 # number of WritebackClean hits
858system.cpu.l2cache.WritebackClean_hits::total 3847 # number of WritebackClean hits
859system.cpu.l2cache.UpgradeReq_hits::cpu.data 1820 # number of UpgradeReq hits
860system.cpu.l2cache.UpgradeReq_hits::total 1820 # number of UpgradeReq hits
861system.cpu.l2cache.ReadExReq_hits::cpu.data 577163 # number of ReadExReq hits
862system.cpu.l2cache.ReadExReq_hits::total 577163 # number of ReadExReq hits
863system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3171 # number of ReadCleanReq hits
864system.cpu.l2cache.ReadCleanReq_hits::total 3171 # number of ReadCleanReq hits
865system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587839 # number of ReadSharedReq hits
866system.cpu.l2cache.ReadSharedReq_hits::total 1587839 # number of ReadSharedReq hits
867system.cpu.l2cache.demand_hits::cpu.inst 3171 # number of demand (read+write) hits
868system.cpu.l2cache.demand_hits::cpu.data 2165002 # number of demand (read+write) hits
869system.cpu.l2cache.demand_hits::total 2168173 # number of demand (read+write) hits
870system.cpu.l2cache.overall_hits::cpu.inst 3171 # number of overall hits
871system.cpu.l2cache.overall_hits::cpu.data 2165002 # number of overall hits
872system.cpu.l2cache.overall_hits::total 2168173 # number of overall hits
873system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
874system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
875system.cpu.l2cache.ReadExReq_misses::cpu.data 206795 # number of ReadExReq misses
876system.cpu.l2cache.ReadExReq_misses::total 206795 # number of ReadExReq misses
877system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2409 # number of ReadCleanReq misses
878system.cpu.l2cache.ReadCleanReq_misses::total 2409 # number of ReadCleanReq misses
879system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178301 # number of ReadSharedReq misses
880system.cpu.l2cache.ReadSharedReq_misses::total 178301 # number of ReadSharedReq misses
881system.cpu.l2cache.demand_misses::cpu.inst 2409 # number of demand (read+write) misses
882system.cpu.l2cache.demand_misses::cpu.data 385096 # number of demand (read+write) misses
883system.cpu.l2cache.demand_misses::total 387505 # number of demand (read+write) misses
884system.cpu.l2cache.overall_misses::cpu.inst 2409 # number of overall misses
885system.cpu.l2cache.overall_misses::cpu.data 385096 # number of overall misses
886system.cpu.l2cache.overall_misses::total 387505 # number of overall misses
887system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 # number of UpgradeReq miss cycles
888system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 # number of UpgradeReq miss cycles
889system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18229359500 # number of ReadExReq miss cycles
890system.cpu.l2cache.ReadExReq_miss_latency::total 18229359500 # number of ReadExReq miss cycles
891system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 331268000 # number of ReadCleanReq miss cycles
892system.cpu.l2cache.ReadCleanReq_miss_latency::total 331268000 # number of ReadCleanReq miss cycles
893system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18228771500 # number of ReadSharedReq miss cycles
894system.cpu.l2cache.ReadSharedReq_miss_latency::total 18228771500 # number of ReadSharedReq miss cycles
895system.cpu.l2cache.demand_miss_latency::cpu.inst 331268000 # number of demand (read+write) miss cycles
896system.cpu.l2cache.demand_miss_latency::cpu.data 36458131000 # number of demand (read+write) miss cycles
897system.cpu.l2cache.demand_miss_latency::total 36789399000 # number of demand (read+write) miss cycles
898system.cpu.l2cache.overall_miss_latency::cpu.inst 331268000 # number of overall miss cycles
899system.cpu.l2cache.overall_miss_latency::cpu.data 36458131000 # number of overall miss cycles
900system.cpu.l2cache.overall_miss_latency::total 36789399000 # number of overall miss cycles
901system.cpu.l2cache.WritebackDirty_accesses::writebacks 2338096 # number of WritebackDirty accesses(hits+misses)
902system.cpu.l2cache.WritebackDirty_accesses::total 2338096 # number of WritebackDirty accesses(hits+misses)
903system.cpu.l2cache.WritebackClean_accesses::writebacks 3847 # number of WritebackClean accesses(hits+misses)
904system.cpu.l2cache.WritebackClean_accesses::total 3847 # number of WritebackClean accesses(hits+misses)
905system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
906system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
907system.cpu.l2cache.ReadExReq_accesses::cpu.data 783958 # number of ReadExReq accesses(hits+misses)
908system.cpu.l2cache.ReadExReq_accesses::total 783958 # number of ReadExReq accesses(hits+misses)
909system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5580 # number of ReadCleanReq accesses(hits+misses)
910system.cpu.l2cache.ReadCleanReq_accesses::total 5580 # number of ReadCleanReq accesses(hits+misses)
911system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766140 # number of ReadSharedReq accesses(hits+misses)
912system.cpu.l2cache.ReadSharedReq_accesses::total 1766140 # number of ReadSharedReq accesses(hits+misses)
913system.cpu.l2cache.demand_accesses::cpu.inst 5580 # number of demand (read+write) accesses
914system.cpu.l2cache.demand_accesses::cpu.data 2550098 # number of demand (read+write) accesses
915system.cpu.l2cache.demand_accesses::total 2555678 # number of demand (read+write) accesses
916system.cpu.l2cache.overall_accesses::cpu.inst 5580 # number of overall (read+write) accesses
917system.cpu.l2cache.overall_accesses::cpu.data 2550098 # number of overall (read+write) accesses
918system.cpu.l2cache.overall_accesses::total 2555678 # number of overall (read+write) accesses
919system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002740 # miss rate for UpgradeReq accesses
920system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002740 # miss rate for UpgradeReq accesses
921system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263783 # miss rate for ReadExReq accesses
922system.cpu.l2cache.ReadExReq_miss_rate::total 0.263783 # miss rate for ReadExReq accesses
923system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.431720 # miss rate for ReadCleanReq accesses
924system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.431720 # miss rate for ReadCleanReq accesses
925system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100955 # miss rate for ReadSharedReq accesses
926system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100955 # miss rate for ReadSharedReq accesses
927system.cpu.l2cache.demand_miss_rate::cpu.inst 0.431720 # miss rate for demand accesses
928system.cpu.l2cache.demand_miss_rate::cpu.data 0.151012 # miss rate for demand accesses
929system.cpu.l2cache.demand_miss_rate::total 0.151625 # miss rate for demand accesses
930system.cpu.l2cache.overall_miss_rate::cpu.inst 0.431720 # miss rate for overall accesses
931system.cpu.l2cache.overall_miss_rate::cpu.data 0.151012 # miss rate for overall accesses
932system.cpu.l2cache.overall_miss_rate::total 0.151625 # miss rate for overall accesses
933system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6100 # average UpgradeReq miss latency
934system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6100 # average UpgradeReq miss latency
935system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88151.838778 # average ReadExReq miss latency
936system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88151.838778 # average ReadExReq miss latency
937system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 137512.660855 # average ReadCleanReq miss latency
938system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 137512.660855 # average ReadCleanReq miss latency
939system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102235.946517 # average ReadSharedReq miss latency
940system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102235.946517 # average ReadSharedReq miss latency
941system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 137512.660855 # average overall miss latency
942system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94672.837422 # average overall miss latency
943system.cpu.l2cache.demand_avg_miss_latency::total 94939.159495 # average overall miss latency
944system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 137512.660855 # average overall miss latency
945system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94672.837422 # average overall miss latency
946system.cpu.l2cache.overall_avg_miss_latency::total 94939.159495 # average overall miss latency
947system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
948system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
949system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
950system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
951system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
952system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
953system.cpu.l2cache.writebacks::writebacks 295435 # number of writebacks
954system.cpu.l2cache.writebacks::total 295435 # number of writebacks
955system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
956system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
957system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
958system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
959system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206795 # number of ReadExReq MSHR misses
960system.cpu.l2cache.ReadExReq_mshr_misses::total 206795 # number of ReadExReq MSHR misses
961system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2409 # number of ReadCleanReq MSHR misses
962system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2409 # number of ReadCleanReq MSHR misses
963system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178301 # number of ReadSharedReq MSHR misses
964system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178301 # number of ReadSharedReq MSHR misses
965system.cpu.l2cache.demand_mshr_misses::cpu.inst 2409 # number of demand (read+write) MSHR misses
966system.cpu.l2cache.demand_mshr_misses::cpu.data 385096 # number of demand (read+write) MSHR misses
967system.cpu.l2cache.demand_mshr_misses::total 387505 # number of demand (read+write) MSHR misses
968system.cpu.l2cache.overall_mshr_misses::cpu.inst 2409 # number of overall MSHR misses
969system.cpu.l2cache.overall_mshr_misses::cpu.data 385096 # number of overall MSHR misses
970system.cpu.l2cache.overall_mshr_misses::total 387505 # number of overall MSHR misses
971system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles
972system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles
973system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16161409500 # number of ReadExReq MSHR miss cycles
974system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16161409500 # number of ReadExReq MSHR miss cycles
975system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307178000 # number of ReadCleanReq MSHR miss cycles
976system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307178000 # number of ReadCleanReq MSHR miss cycles
977system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16445761500 # number of ReadSharedReq MSHR miss cycles
978system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16445761500 # number of ReadSharedReq MSHR miss cycles
979system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307178000 # number of demand (read+write) MSHR miss cycles
980system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32607171000 # number of demand (read+write) MSHR miss cycles
981system.cpu.l2cache.demand_mshr_miss_latency::total 32914349000 # number of demand (read+write) MSHR miss cycles
982system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307178000 # number of overall MSHR miss cycles
983system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32607171000 # number of overall MSHR miss cycles
984system.cpu.l2cache.overall_mshr_miss_latency::total 32914349000 # number of overall MSHR miss cycles
985system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
986system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
987system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002740 # mshr miss rate for UpgradeReq accesses
988system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002740 # mshr miss rate for UpgradeReq accesses
989system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263783 # mshr miss rate for ReadExReq accesses
990system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263783 # mshr miss rate for ReadExReq accesses
991system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for ReadCleanReq accesses
992system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.431720 # mshr miss rate for ReadCleanReq accesses
993system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100955 # mshr miss rate for ReadSharedReq accesses
994system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100955 # mshr miss rate for ReadSharedReq accesses
995system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for demand accesses
996system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for demand accesses
997system.cpu.l2cache.demand_mshr_miss_rate::total 0.151625 # mshr miss rate for demand accesses
998system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for overall accesses
999system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for overall accesses
1000system.cpu.l2cache.overall_mshr_miss_rate::total 0.151625 # mshr miss rate for overall accesses
1001system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency
1002system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency
1003system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78151.838778 # average ReadExReq mshr miss latency
1004system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78151.838778 # average ReadExReq mshr miss latency
1005system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 127512.660855 # average ReadCleanReq mshr miss latency
1006system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 127512.660855 # average ReadCleanReq mshr miss latency
1007system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517 # average ReadSharedReq mshr miss latency
1008system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517 # average ReadSharedReq mshr miss latency
1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency
1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency
1011system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency
1012system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency
1013system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency
1014system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency
1015system.cpu.toL2Bus.snoop_filter.tot_requests 5109342 # Total number of requests made to the snoop filter.
1016system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551824 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1017system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1018system.cpu.toL2Bus.snoop_filter.tot_snoops 2956 # Total number of snoops made to the snoop filter.
1019system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2953 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1020system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1021system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
1022system.cpu.toL2Bus.trans_dist::ReadResp 1773620 # Transaction distribution
1023system.cpu.toL2Bus.trans_dist::WritebackDirty 2633531 # Transaction distribution
1024system.cpu.toL2Bus.trans_dist::WritebackClean 3937 # Transaction distribution
1025system.cpu.toL2Bus.trans_dist::CleanEvict 268382 # Transaction distribution
1026system.cpu.toL2Bus.trans_dist::UpgradeReq 1825 # Transaction distribution
1027system.cpu.toL2Bus.trans_dist::UpgradeResp 1825 # Transaction distribution
1028system.cpu.toL2Bus.trans_dist::ReadExReq 783958 # Transaction distribution
1029system.cpu.toL2Bus.trans_dist::ReadExResp 783958 # Transaction distribution
1030system.cpu.toL2Bus.trans_dist::ReadCleanReq 7480 # Transaction distribution
1031system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766140 # Transaction distribution
1032system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16997 # Packet count per connected master and slave (bytes)
1033system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649848 # Packet count per connected master and slave (bytes)
1034system.cpu.toL2Bus.pkt_count::total 7666845 # Packet count per connected master and slave (bytes)
1035system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609088 # Cumulative packet size per connected master and slave (bytes)
1036system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312844416 # Cumulative packet size per connected master and slave (bytes)
1037system.cpu.toL2Bus.pkt_size::total 313453504 # Cumulative packet size per connected master and slave (bytes)
1038system.cpu.toL2Bus.snoops 357811 # Total snoops (count)
1039system.cpu.toL2Bus.snoopTraffic 19029440 # Total snoop traffic (bytes)
1040system.cpu.toL2Bus.snoop_fanout::samples 2915314 # Request fanout histogram
1041system.cpu.toL2Bus.snoop_fanout::mean 0.004397 # Request fanout histogram
1042system.cpu.toL2Bus.snoop_fanout::stdev 0.066180 # Request fanout histogram
1043system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1044system.cpu.toL2Bus.snoop_fanout::0 2902498 99.56% 99.56% # Request fanout histogram
1045system.cpu.toL2Bus.snoop_fanout::1 12813 0.44% 100.00% # Request fanout histogram
1046system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
1047system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1048system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1049system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1050system.cpu.toL2Bus.snoop_fanout::total 2915314 # Request fanout histogram
1051system.cpu.toL2Bus.reqLayer0.occupancy 4896765876 # Layer occupancy (ticks)
1052system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
1053system.cpu.toL2Bus.respLayer0.occupancy 11220998 # Layer occupancy (ticks)
1054system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1055system.cpu.toL2Bus.respLayer1.occupancy 3826059624 # Layer occupancy (ticks)
1056system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
1057system.membus.snoop_filter.tot_requests 740486 # Total number of requests made to the snoop filter.
1058system.membus.snoop_filter.hit_single_requests 353479 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1059system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1060system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1061system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1062system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1063system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states
1064system.membus.trans_dist::ReadResp 180710 # Transaction distribution
1065system.membus.trans_dist::WritebackDirty 295435 # Transaction distribution
1066system.membus.trans_dist::CleanEvict 57541 # Transaction distribution
1067system.membus.trans_dist::UpgradeReq 8 # Transaction distribution
1068system.membus.trans_dist::ReadExReq 206792 # Transaction distribution
1069system.membus.trans_dist::ReadExResp 206792 # Transaction distribution
1070system.membus.trans_dist::ReadSharedReq 180710 # Transaction distribution
1071system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127988 # Packet count per connected master and slave (bytes)
1072system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127988 # Packet count per connected master and slave (bytes)
1073system.membus.pkt_count::total 1127988 # Packet count per connected master and slave (bytes)
1074system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43707968 # Cumulative packet size per connected master and slave (bytes)
1075system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43707968 # Cumulative packet size per connected master and slave (bytes)
1076system.membus.pkt_size::total 43707968 # Cumulative packet size per connected master and slave (bytes)
1077system.membus.snoops 0 # Total snoops (count)
1078system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1079system.membus.snoop_fanout::samples 387510 # Request fanout histogram
1080system.membus.snoop_fanout::mean 0 # Request fanout histogram
1081system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1082system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1083system.membus.snoop_fanout::0 387510 100.00% 100.00% # Request fanout histogram
1084system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1085system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1086system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1087system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1088system.membus.snoop_fanout::total 387510 # Request fanout histogram
1089system.membus.reqLayer0.occupancy 1995365000 # Layer occupancy (ticks)
1090system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
1091system.membus.respLayer1.occupancy 2050434250 # Layer occupancy (ticks)
1092system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
1093
1094---------- End Simulation Statistics ----------