1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.458346 # Number of seconds simulated
4sim_ticks 458345683000 # Number of ticks simulated
5final_tick 458345683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 77949 # Simulator instruction rate (inst/s)
8host_op_rate 144137 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 43207948 # Simulator tick rate (ticks/s)
10host_mem_usage 382980 # Number of bytes of host memory used
11host_seconds 10607.90 # Real time elapsed on the host
12sim_insts 826877109 # Number of instructions simulated
13sim_ops 1528988701 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 201344 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24476224 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24677568 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 201344 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 201344 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 18790080 # Number of bytes written to this memory
22system.physmem.bytes_written::total 18790080 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 3146 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 382441 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 385587 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 293595 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 293595 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 439284 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 53401232 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 53840516 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 439284 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 439284 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 40995434 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 40995434 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 40995434 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 439284 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 53401232 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 94835949 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 385587 # Number of read requests accepted
40system.physmem.writeReqs 293595 # Number of write requests accepted
41system.physmem.readBursts 385587 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 293595 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 24655680 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue
45system.physmem.bytesWritten 18787904 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 24677568 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 18790080 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 137451 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 23999 # Per bank write bursts
52system.physmem.perBankRdBursts::1 26321 # Per bank write bursts
53system.physmem.perBankRdBursts::2 24635 # Per bank write bursts
54system.physmem.perBankRdBursts::3 24488 # Per bank write bursts
55system.physmem.perBankRdBursts::4 23208 # Per bank write bursts
56system.physmem.perBankRdBursts::5 23662 # Per bank write bursts
57system.physmem.perBankRdBursts::6 24431 # Per bank write bursts
58system.physmem.perBankRdBursts::7 24245 # Per bank write bursts
59system.physmem.perBankRdBursts::8 23683 # Per bank write bursts
60system.physmem.perBankRdBursts::9 23822 # Per bank write bursts
61system.physmem.perBankRdBursts::10 24823 # Per bank write bursts
62system.physmem.perBankRdBursts::11 24044 # Per bank write bursts
63system.physmem.perBankRdBursts::12 23228 # Per bank write bursts
64system.physmem.perBankRdBursts::13 22920 # Per bank write bursts
65system.physmem.perBankRdBursts::14 23793 # Per bank write bursts
66system.physmem.perBankRdBursts::15 23943 # Per bank write bursts
67system.physmem.perBankWrBursts::0 18539 # Per bank write bursts
68system.physmem.perBankWrBursts::1 19811 # Per bank write bursts
69system.physmem.perBankWrBursts::2 18919 # Per bank write bursts
70system.physmem.perBankWrBursts::3 18907 # Per bank write bursts
71system.physmem.perBankWrBursts::4 18016 # Per bank write bursts
72system.physmem.perBankWrBursts::5 18404 # Per bank write bursts
73system.physmem.perBankWrBursts::6 18977 # Per bank write bursts
74system.physmem.perBankWrBursts::7 18938 # Per bank write bursts
75system.physmem.perBankWrBursts::8 18573 # Per bank write bursts
76system.physmem.perBankWrBursts::9 18106 # Per bank write bursts
77system.physmem.perBankWrBursts::10 18839 # Per bank write bursts
78system.physmem.perBankWrBursts::11 17716 # Per bank write bursts
79system.physmem.perBankWrBursts::12 17343 # Per bank write bursts
80system.physmem.perBankWrBursts::13 16932 # Per bank write bursts
81system.physmem.perBankWrBursts::14 17725 # Per bank write bursts
82system.physmem.perBankWrBursts::15 17816 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 458345657000 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 385587 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 293595 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 380584 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 4329 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see

--- 25 unchanged lines hidden (view full) ---

139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 6249 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 6906 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 15790 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 16374 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 16588 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 16668 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 16965 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 16912 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 16903 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 21550 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 17962 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 17787 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 22491 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 17603 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 17344 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 17191 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 16827 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 1360 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 517 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 374 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 342 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 329 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 344 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 311 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 306 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 273 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 282 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 272 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 274 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 257 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 96485 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 354.073856 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 206.339683 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 360.153261 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 30862 31.99% 31.99% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 25245 26.16% 58.15% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 9104 9.44% 67.59% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 4981 5.16% 72.75% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 3508 3.64% 76.38% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 2549 2.64% 79.03% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 1904 1.97% 81.00% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 1721 1.78% 82.78% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 16611 17.22% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 96485 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 16638 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 23.153564 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 214.001392 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 16625 99.92% 99.92% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::total 16638 # Reads before turning the bus around for writes
219system.physmem.wrPerTurnAround::samples 16638 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::mean 17.644008 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::gmean 17.412925 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::stdev 3.984420 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::16-19 15809 95.02% 95.02% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::20-23 568 3.41% 98.43% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::24-27 13 0.08% 98.51% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::28-31 7 0.04% 98.55% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::32-35 5 0.03% 98.58% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::36-39 61 0.37% 98.95% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::40-43 106 0.64% 99.59% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::44-47 27 0.16% 99.75% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::48-51 20 0.12% 99.87% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::52-55 3 0.02% 99.89% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::56-59 1 0.01% 99.89% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::60-63 6 0.04% 99.93% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::64-67 1 0.01% 99.93% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::76-79 1 0.01% 99.94% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::80-83 1 0.01% 99.95% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::88-91 2 0.01% 99.96% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::96-99 1 0.01% 99.96% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::100-103 2 0.01% 99.98% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::128-131 1 0.01% 100.00% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::total 16638 # Writes before turning the bus around for reads
245system.physmem.totQLat 2817376000 # Total ticks spent queuing
246system.physmem.totMemAccLat 11128592250 # Total ticks spent from burst creation until serviced by the DRAM
247system.physmem.totBusLat 1926225000 # Total ticks spent in databus transfers
248system.physmem.totBankLat 6384991250 # Total ticks spent accessing banks
249system.physmem.avgQLat 7313.21 # Average queueing delay per DRAM burst
250system.physmem.avgBankLat 16573.85 # Average bank access latency per DRAM burst
251system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
252system.physmem.avgMemAccLat 28887.05 # Average memory access latency per DRAM burst
253system.physmem.avgRdBW 53.79 # Average DRAM read bandwidth in MiByte/s
254system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MiByte/s
255system.physmem.avgRdBWSys 53.84 # Average system read bandwidth in MiByte/s
256system.physmem.avgWrBWSys 41.00 # Average system write bandwidth in MiByte/s
257system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
258system.physmem.busUtil 0.74 # Data bus utilization in percentage
259system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
260system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
261system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
262system.physmem.avgWrQLen 22.28 # Average write queue length when enqueuing
263system.physmem.readRowHits 317177 # Number of row buffer hits during reads
264system.physmem.writeRowHits 216322 # Number of row buffer hits during writes
265system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
266system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes
267system.physmem.avgGap 674849.54 # Average gap between requests
268system.physmem.pageHitRate 78.59 # Row buffer hit rate, read and write combined
269system.physmem.prechargeAllPercent 5.94 # Percentage of time for which DRAM has all the banks in precharge state
270system.membus.throughput 94835949 # Throughput (bytes/s)
271system.membus.trans_dist::ReadReq 178789 # Transaction distribution
272system.membus.trans_dist::ReadResp 178789 # Transaction distribution
273system.membus.trans_dist::Writeback 293595 # Transaction distribution
274system.membus.trans_dist::UpgradeReq 137451 # Transaction distribution
275system.membus.trans_dist::UpgradeResp 137451 # Transaction distribution
276system.membus.trans_dist::ReadExReq 206798 # Transaction distribution
277system.membus.trans_dist::ReadExResp 206798 # Transaction distribution
278system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1339671 # Packet count per connected master and slave (bytes)
279system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1339671 # Packet count per connected master and slave (bytes)
280system.membus.pkt_count::total 1339671 # Packet count per connected master and slave (bytes)
281system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43467648 # Cumulative packet size per connected master and slave (bytes)
282system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43467648 # Cumulative packet size per connected master and slave (bytes)
283system.membus.tot_pkt_size::total 43467648 # Cumulative packet size per connected master and slave (bytes)
284system.membus.data_through_bus 43467648 # Total data (bytes)
285system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
286system.membus.reqLayer0.occupancy 3393086500 # Layer occupancy (ticks)
287system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
288system.membus.respLayer1.occupancy 3901807065 # Layer occupancy (ticks)
289system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
290system.cpu_clk_domain.clock 500 # Clock period in ticks
291system.cpu.branchPred.lookups 205603387 # Number of BP lookups
292system.cpu.branchPred.condPredicted 205603387 # Number of conditional branches predicted
293system.cpu.branchPred.condIncorrect 9902113 # Number of conditional branches incorrect
294system.cpu.branchPred.BTBLookups 117080162 # Number of BTB lookups
295system.cpu.branchPred.BTBHits 114702381 # Number of BTB hits
296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
297system.cpu.branchPred.BTBHitPct 97.969100 # BTB Hit Percentage
298system.cpu.branchPred.usedRAS 25060949 # Number of times the RAS was used to get a target.
299system.cpu.branchPred.RASInCorrect 1802781 # Number of incorrect RAS predictions.
300system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
301system.cpu.workload.num_syscalls 551 # Number of system calls
302system.cpu.numCycles 916852867 # number of cpu cycles simulated
303system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
304system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
305system.cpu.fetch.icacheStallCycles 167425421 # Number of cycles fetch is stalled on an Icache miss
306system.cpu.fetch.Insts 1131697501 # Number of instructions fetch has processed
307system.cpu.fetch.Branches 205603387 # Number of branches that fetch encountered
308system.cpu.fetch.predictedBranches 139763330 # Number of branches that fetch has predicted taken
309system.cpu.fetch.Cycles 352285469 # Number of cycles fetch has run and was not squashing or blocked
310system.cpu.fetch.SquashCycles 71105811 # Number of cycles fetch has spent squashing
311system.cpu.fetch.BlockedCycles 304521969 # Number of cycles fetch has spent blocked
312system.cpu.fetch.MiscStallCycles 48109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
313system.cpu.fetch.PendingTrapStallCycles 252946 # Number of stall cycles due to pending traps
314system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR
315system.cpu.fetch.CacheLines 162022121 # Number of cache lines fetched
316system.cpu.fetch.IcacheSquashes 2522560 # Number of outstanding Icache misses that were squashed
317system.cpu.fetch.rateDist::samples 885484431 # Number of instructions fetched each cycle (Total)
318system.cpu.fetch.rateDist::mean 2.378017 # Number of instructions fetched each cycle (Total)
319system.cpu.fetch.rateDist::stdev 3.324314 # Number of instructions fetched each cycle (Total)
320system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
321system.cpu.fetch.rateDist::0 537271116 60.68% 60.68% # Number of instructions fetched each cycle (Total)
322system.cpu.fetch.rateDist::1 23397088 2.64% 63.32% # Number of instructions fetched each cycle (Total)
323system.cpu.fetch.rateDist::2 25262126 2.85% 66.17% # Number of instructions fetched each cycle (Total)
324system.cpu.fetch.rateDist::3 27864383 3.15% 69.32% # Number of instructions fetched each cycle (Total)
325system.cpu.fetch.rateDist::4 17763945 2.01% 71.32% # Number of instructions fetched each cycle (Total)
326system.cpu.fetch.rateDist::5 22926561 2.59% 73.91% # Number of instructions fetched each cycle (Total)
327system.cpu.fetch.rateDist::6 29429676 3.32% 77.24% # Number of instructions fetched each cycle (Total)
328system.cpu.fetch.rateDist::7 26640012 3.01% 80.24% # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::8 174929524 19.76% 100.00% # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
333system.cpu.fetch.rateDist::total 885484431 # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.branchRate 0.224249 # Number of branch fetches per cycle
335system.cpu.fetch.rate 1.234328 # Number of inst fetches per cycle
336system.cpu.decode.IdleCycles 222585266 # Number of cycles decode is idle
337system.cpu.decode.BlockedCycles 259638923 # Number of cycles decode is blocked
338system.cpu.decode.RunCycles 295357907 # Number of cycles decode is running
339system.cpu.decode.UnblockCycles 46951879 # Number of cycles decode is unblocking
340system.cpu.decode.SquashCycles 60950456 # Number of cycles decode is squashing
341system.cpu.decode.DecodedInsts 2071410922 # Number of instructions handled by decode
342system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
343system.cpu.rename.SquashCycles 60950456 # Number of cycles rename is squashing
344system.cpu.rename.IdleCycles 256114538 # Number of cycles rename is idle
345system.cpu.rename.BlockCycles 114960463 # Number of cycles rename is blocking
346system.cpu.rename.serializeStallCycles 17780 # count of cycles rename stalled for serializing inst
347system.cpu.rename.RunCycles 306643544 # Number of cycles rename is running
348system.cpu.rename.UnblockCycles 146797650 # Number of cycles rename is unblocking
349system.cpu.rename.RenamedInsts 2035254884 # Number of instructions processed by rename
350system.cpu.rename.ROBFullEvents 19108 # Number of times rename has blocked due to ROB full
351system.cpu.rename.IQFullEvents 24985336 # Number of times rename has blocked due to IQ full
352system.cpu.rename.LSQFullEvents 106570240 # Number of times rename has blocked due to LSQ full
353system.cpu.rename.RenamedOperands 2138126742 # Number of destination operands rename has renamed
354system.cpu.rename.RenameLookups 5150804980 # Number of register rename lookups that rename has made
355system.cpu.rename.int_rename_lookups 3273565222 # Number of integer rename lookups
356system.cpu.rename.fp_rename_lookups 40421 # Number of floating rename lookups
357system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
358system.cpu.rename.UndoneMaps 524085888 # Number of HB maps that are undone due to squashing
359system.cpu.rename.serializingInsts 1238 # count of serializing insts renamed
360system.cpu.rename.tempSerializingInsts 1169 # count of temporary serializing insts renamed
361system.cpu.rename.skidInsts 346813798 # count of insts added to the skid buffer
362system.cpu.memDep0.insertedLoads 495843290 # Number of loads inserted to the mem dependence unit.
363system.cpu.memDep0.insertedStores 194454992 # Number of stores inserted to the mem dependence unit.
364system.cpu.memDep0.conflictingLoads 195400842 # Number of conflicting loads.
365system.cpu.memDep0.conflictingStores 54863800 # Number of conflicting stores.
366system.cpu.iq.iqInstsAdded 1975546158 # Number of instructions added to the IQ (excludes non-spec)
367system.cpu.iq.iqNonSpecInstsAdded 13200 # Number of non-speculative instructions added to the IQ
368system.cpu.iq.iqInstsIssued 1772179882 # Number of instructions issued
369system.cpu.iq.iqSquashedInstsIssued 484148 # Number of squashed instructions issued
370system.cpu.iq.iqSquashedInstsExamined 441719386 # Number of squashed instructions iterated over during squash; mainly for profiling
371system.cpu.iq.iqSquashedOperandsExamined 735183548 # Number of squashed operands that are examined and possibly removed from graph
372system.cpu.iq.iqSquashedNonSpecRemoved 12648 # Number of squashed non-spec instructions that were removed
373system.cpu.iq.issued_per_cycle::samples 885484431 # Number of insts issued each cycle
374system.cpu.iq.issued_per_cycle::mean 2.001368 # Number of insts issued each cycle
375system.cpu.iq.issued_per_cycle::stdev 1.882860 # Number of insts issued each cycle
376system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
377system.cpu.iq.issued_per_cycle::0 268514596 30.32% 30.32% # Number of insts issued each cycle
378system.cpu.iq.issued_per_cycle::1 152316057 17.20% 47.53% # Number of insts issued each cycle
379system.cpu.iq.issued_per_cycle::2 137257157 15.50% 63.03% # Number of insts issued each cycle
380system.cpu.iq.issued_per_cycle::3 131678995 14.87% 77.90% # Number of insts issued each cycle
381system.cpu.iq.issued_per_cycle::4 91673992 10.35% 88.25% # Number of insts issued each cycle
382system.cpu.iq.issued_per_cycle::5 56016548 6.33% 94.58% # Number of insts issued each cycle
383system.cpu.iq.issued_per_cycle::6 34412328 3.89% 98.46% # Number of insts issued each cycle
384system.cpu.iq.issued_per_cycle::7 11858214 1.34% 99.80% # Number of insts issued each cycle
385system.cpu.iq.issued_per_cycle::8 1756544 0.20% 100.00% # Number of insts issued each cycle
386system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
387system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
388system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
389system.cpu.iq.issued_per_cycle::total 885484431 # Number of insts issued each cycle
390system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
391system.cpu.iq.fu_full::IntAlu 4914226 32.32% 32.32% # attempts to use FU when none available
392system.cpu.iq.fu_full::IntMult 0 0.00% 32.32% # attempts to use FU when none available
393system.cpu.iq.fu_full::IntDiv 0 0.00% 32.32% # attempts to use FU when none available
394system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.32% # attempts to use FU when none available
395system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.32% # attempts to use FU when none available
396system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.32% # attempts to use FU when none available
397system.cpu.iq.fu_full::FloatMult 0 0.00% 32.32% # attempts to use FU when none available
398system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.32% # attempts to use FU when none available
399system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.32% # attempts to use FU when none available
400system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.32% # attempts to use FU when none available
401system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.32% # attempts to use FU when none available
402system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.32% # attempts to use FU when none available
403system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.32% # attempts to use FU when none available
404system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.32% # attempts to use FU when none available
405system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.32% # attempts to use FU when none available
406system.cpu.iq.fu_full::SimdMult 0 0.00% 32.32% # attempts to use FU when none available
407system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.32% # attempts to use FU when none available
408system.cpu.iq.fu_full::SimdShift 0 0.00% 32.32% # attempts to use FU when none available
409system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.32% # attempts to use FU when none available
410system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.32% # attempts to use FU when none available
411system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.32% # attempts to use FU when none available
412system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.32% # attempts to use FU when none available
413system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.32% # attempts to use FU when none available
414system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.32% # attempts to use FU when none available
415system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.32% # attempts to use FU when none available
416system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.32% # attempts to use FU when none available
417system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.32% # attempts to use FU when none available
418system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.32% # attempts to use FU when none available
419system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.32% # attempts to use FU when none available
420system.cpu.iq.fu_full::MemRead 7684512 50.55% 82.87% # attempts to use FU when none available
421system.cpu.iq.fu_full::MemWrite 2604414 17.13% 100.00% # attempts to use FU when none available
422system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
423system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
424system.cpu.iq.FU_type_0::No_OpClass 2627261 0.15% 0.15% # Type of FU issued
425system.cpu.iq.FU_type_0::IntAlu 1165804408 65.78% 65.93% # Type of FU issued
426system.cpu.iq.FU_type_0::IntMult 352994 0.02% 65.95% # Type of FU issued
427system.cpu.iq.FU_type_0::IntDiv 3880826 0.22% 66.17% # Type of FU issued
428system.cpu.iq.FU_type_0::FloatAdd 67 0.00% 66.17% # Type of FU issued
429system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
430system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
431system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
432system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
433system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
434system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
435system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
436system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued

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446system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
447system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
448system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
449system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
450system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
451system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
452system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
453system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
454system.cpu.iq.FU_type_0::MemRead 429279214 24.22% 90.39% # Type of FU issued
455system.cpu.iq.FU_type_0::MemWrite 170235112 9.61% 100.00% # Type of FU issued
456system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
457system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
458system.cpu.iq.FU_type_0::total 1772179882 # Type of FU issued
459system.cpu.iq.rate 1.932895 # Inst issue rate
460system.cpu.iq.fu_busy_cnt 15203152 # FU busy when requested
461system.cpu.iq.fu_busy_rate 0.008579 # FU busy rate (busy events/executed inst)
462system.cpu.iq.int_inst_queue_reads 4445517936 # Number of integer instruction queue reads
463system.cpu.iq.int_inst_queue_writes 2417485915 # Number of integer instruction queue writes
464system.cpu.iq.int_inst_queue_wakeup_accesses 1744947174 # Number of integer instruction queue wakeup accesses
465system.cpu.iq.fp_inst_queue_reads 13559 # Number of floating instruction queue reads
466system.cpu.iq.fp_inst_queue_writes 50440 # Number of floating instruction queue writes
467system.cpu.iq.fp_inst_queue_wakeup_accesses 3261 # Number of floating instruction queue wakeup accesses
468system.cpu.iq.int_alu_accesses 1784749273 # Number of integer alu accesses
469system.cpu.iq.fp_alu_accesses 6500 # Number of floating point alu accesses
470system.cpu.iew.lsq.thread0.forwLoads 172700004 # Number of loads that had data forwarded from stores
471system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
472system.cpu.iew.lsq.thread0.squashedLoads 111742246 # Number of loads squashed
473system.cpu.iew.lsq.thread0.ignoredResponses 386565 # Number of memory responses ignored because the instruction is squashed
474system.cpu.iew.lsq.thread0.memOrderViolation 329489 # Number of memory ordering violations
475system.cpu.iew.lsq.thread0.squashedStores 45294806 # Number of stores squashed
476system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
477system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
478system.cpu.iew.lsq.thread0.rescheduledLoads 14850 # Number of loads that were rescheduled
479system.cpu.iew.lsq.thread0.cacheBlocked 595 # Number of times an access to memory failed due to the cache being blocked
480system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
481system.cpu.iew.iewSquashCycles 60950456 # Number of cycles IEW is squashing
482system.cpu.iew.iewBlockCycles 66921774 # Number of cycles IEW is blocking
483system.cpu.iew.iewUnblockCycles 7152270 # Number of cycles IEW is unblocking
484system.cpu.iew.iewDispatchedInsts 1975559358 # Number of instructions dispatched to IQ
485system.cpu.iew.iewDispSquashedInsts 792714 # Number of squashed instructions skipped by dispatch
486system.cpu.iew.iewDispLoadInsts 495844403 # Number of dispatched load instructions
487system.cpu.iew.iewDispStoreInsts 194454992 # Number of dispatched store instructions
488system.cpu.iew.iewDispNonSpecInsts 3102 # Number of dispatched non-speculative instructions
489system.cpu.iew.iewIQFullEvents 4466928 # Number of times the IQ has become full, causing a stall
490system.cpu.iew.iewLSQFullEvents 83631 # Number of times the LSQ has become full, causing a stall
491system.cpu.iew.memOrderViolationEvents 329489 # Number of memory order violations
492system.cpu.iew.predictedTakenIncorrect 5907148 # Number of branches that were predicted taken incorrectly
493system.cpu.iew.predictedNotTakenIncorrect 4425214 # Number of branches that were predicted not taken incorrectly
494system.cpu.iew.branchMispredicts 10332362 # Number of branch mispredicts detected at execute
495system.cpu.iew.iewExecutedInsts 1753055321 # Number of executed instructions
496system.cpu.iew.iewExecLoadInsts 424140880 # Number of load instructions executed
497system.cpu.iew.iewExecSquashedInsts 19124561 # Number of squashed instructions skipped in execute
498system.cpu.iew.exec_swp 0 # number of swp insts executed
499system.cpu.iew.exec_nop 0 # number of nop insts executed
500system.cpu.iew.exec_refs 590933103 # number of memory reference insts executed
501system.cpu.iew.exec_branches 167483673 # Number of branches executed
502system.cpu.iew.exec_stores 166792223 # Number of stores executed
503system.cpu.iew.exec_rate 1.912036 # Inst execution rate
504system.cpu.iew.wb_sent 1749807321 # cumulative count of insts sent to commit
505system.cpu.iew.wb_count 1744950435 # cumulative count of insts written-back
506system.cpu.iew.wb_producers 1324909698 # num instructions producing a value
507system.cpu.iew.wb_consumers 1945755632 # num instructions consuming a value
508system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
509system.cpu.iew.wb_rate 1.903196 # insts written-back per cycle
510system.cpu.iew.wb_fanout 0.680923 # average fanout of values written-back
511system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
512system.cpu.commit.commitSquashedInsts 446599399 # The number of squashed insts skipped by commit
513system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
514system.cpu.commit.branchMispredicts 9930890 # The number of times a branch was mispredicted
515system.cpu.commit.committed_per_cycle::samples 824533975 # Number of insts commited each cycle
516system.cpu.commit.committed_per_cycle::mean 1.854367 # Number of insts commited each cycle
517system.cpu.commit.committed_per_cycle::stdev 2.435928 # Number of insts commited each cycle
518system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
519system.cpu.commit.committed_per_cycle::0 332362619 40.31% 40.31% # Number of insts commited each cycle
520system.cpu.commit.committed_per_cycle::1 193345604 23.45% 63.76% # Number of insts commited each cycle
521system.cpu.commit.committed_per_cycle::2 63386723 7.69% 71.45% # Number of insts commited each cycle
522system.cpu.commit.committed_per_cycle::3 92493757 11.22% 82.66% # Number of insts commited each cycle
523system.cpu.commit.committed_per_cycle::4 24926721 3.02% 85.69% # Number of insts commited each cycle
524system.cpu.commit.committed_per_cycle::5 27481357 3.33% 89.02% # Number of insts commited each cycle
525system.cpu.commit.committed_per_cycle::6 9323499 1.13% 90.15% # Number of insts commited each cycle
526system.cpu.commit.committed_per_cycle::7 11375843 1.38% 91.53% # Number of insts commited each cycle
527system.cpu.commit.committed_per_cycle::8 69837852 8.47% 100.00% # Number of insts commited each cycle
528system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
529system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
530system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
531system.cpu.commit.committed_per_cycle::total 824533975 # Number of insts commited each cycle
532system.cpu.commit.committedInsts 826877109 # Number of instructions committed
533system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
534system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
535system.cpu.commit.refs 533262343 # Number of memory references committed
536system.cpu.commit.loads 384102157 # Number of loads committed
537system.cpu.commit.membars 0 # Number of memory barriers committed
538system.cpu.commit.branches 149758583 # Number of branches committed
539system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
540system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
541system.cpu.commit.function_calls 17673145 # Number of function calls committed.
542system.cpu.commit.bw_lim_events 69837852 # number cycles where commit BW limit reached
543system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
544system.cpu.rob.rob_reads 2730284223 # The number of ROB reads
545system.cpu.rob.rob_writes 4012285085 # The number of ROB writes
546system.cpu.timesIdled 3361589 # Number of times that the entire CPU went into an idle state and unscheduled itself
547system.cpu.idleCycles 31368436 # Total number of cycles that the CPU has spent unscheduled due to idling
548system.cpu.committedInsts 826877109 # Number of Instructions Simulated
549system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
550system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
551system.cpu.cpi 1.108814 # CPI: Cycles Per Instruction
552system.cpu.cpi_total 1.108814 # CPI: Total CPI of All Threads
553system.cpu.ipc 0.901865 # IPC: Instructions Per Cycle
554system.cpu.ipc_total 0.901865 # IPC: Total IPC of All Threads
555system.cpu.int_regfile_reads 2716343034 # number of integer regfile reads
556system.cpu.int_regfile_writes 1420512883 # number of integer regfile writes
557system.cpu.fp_regfile_reads 3304 # number of floating regfile reads
558system.cpu.fp_regfile_writes 92 # number of floating regfile writes
559system.cpu.cc_regfile_reads 597249207 # number of cc regfile reads
560system.cpu.cc_regfile_writes 405429285 # number of cc regfile writes
561system.cpu.misc_regfile_reads 964722506 # number of misc regfile reads
562system.cpu.misc_regfile_writes 1 # number of misc regfile writes
563system.cpu.toL2Bus.throughput 699635153 # Throughput (bytes/s)
564system.cpu.toL2Bus.trans_dist::ReadReq 1908088 # Transaction distribution
565system.cpu.toL2Bus.trans_dist::ReadResp 1908087 # Transaction distribution
566system.cpu.toL2Bus.trans_dist::Writeback 2330726 # Transaction distribution
567system.cpu.toL2Bus.trans_dist::UpgradeReq 138856 # Transaction distribution
568system.cpu.toL2Bus.trans_dist::UpgradeResp 138856 # Transaction distribution
569system.cpu.toL2Bus.trans_dist::ReadExReq 771730 # Transaction distribution
570system.cpu.toL2Bus.trans_dist::ReadExResp 771730 # Transaction distribution
571system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152619 # Packet count per connected master and slave (bytes)
572system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7676496 # Packet count per connected master and slave (bytes)
573system.cpu.toL2Bus.pkt_count::total 7829115 # Packet count per connected master and slave (bytes)
574system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437120 # Cumulative packet size per connected master and slave (bytes)
575system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311344320 # Cumulative packet size per connected master and slave (bytes)
576system.cpu.toL2Bus.tot_pkt_size::total 311781440 # Cumulative packet size per connected master and slave (bytes)
577system.cpu.toL2Bus.data_through_bus 311781440 # Total data (bytes)
578system.cpu.toL2Bus.snoop_data_through_bus 8893312 # Total snoop data (bytes)
579system.cpu.toL2Bus.reqLayer0.occupancy 4908984370 # Layer occupancy (ticks)
580system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
581system.cpu.toL2Bus.respLayer0.occupancy 219136241 # Layer occupancy (ticks)
582system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
583system.cpu.toL2Bus.respLayer1.occupancy 3952027365 # Layer occupancy (ticks)
584system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
585system.cpu.icache.tags.replacements 5320 # number of replacements
586system.cpu.icache.tags.tagsinuse 1037.745275 # Cycle average of tags in use
587system.cpu.icache.tags.total_refs 161872406 # Total number of references to valid blocks.
588system.cpu.icache.tags.sampled_refs 6896 # Sample count of references to valid blocks.
589system.cpu.icache.tags.avg_refs 23473.376740 # Average number of references to valid blocks.
590system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
591system.cpu.icache.tags.occ_blocks::cpu.inst 1037.745275 # Average occupied blocks per requestor
592system.cpu.icache.tags.occ_percent::cpu.inst 0.506712 # Average percentage of cache occupancy
593system.cpu.icache.tags.occ_percent::total 0.506712 # Average percentage of cache occupancy
594system.cpu.icache.tags.occ_task_id_blocks::1024 1576 # Occupied blocks per task id
595system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
596system.cpu.icache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
597system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
598system.cpu.icache.tags.age_task_id_blocks_1024::3 238 # Occupied blocks per task id
599system.cpu.icache.tags.age_task_id_blocks_1024::4 1228 # Occupied blocks per task id
600system.cpu.icache.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
601system.cpu.icache.tags.tag_accesses 324190030 # Number of tag accesses
602system.cpu.icache.tags.data_accesses 324190030 # Number of data accesses
603system.cpu.icache.ReadReq_hits::cpu.inst 161874355 # number of ReadReq hits
604system.cpu.icache.ReadReq_hits::total 161874355 # number of ReadReq hits
605system.cpu.icache.demand_hits::cpu.inst 161874355 # number of demand (read+write) hits
606system.cpu.icache.demand_hits::total 161874355 # number of demand (read+write) hits
607system.cpu.icache.overall_hits::cpu.inst 161874355 # number of overall hits
608system.cpu.icache.overall_hits::total 161874355 # number of overall hits
609system.cpu.icache.ReadReq_misses::cpu.inst 147766 # number of ReadReq misses
610system.cpu.icache.ReadReq_misses::total 147766 # number of ReadReq misses
611system.cpu.icache.demand_misses::cpu.inst 147766 # number of demand (read+write) misses
612system.cpu.icache.demand_misses::total 147766 # number of demand (read+write) misses
613system.cpu.icache.overall_misses::cpu.inst 147766 # number of overall misses
614system.cpu.icache.overall_misses::total 147766 # number of overall misses
615system.cpu.icache.ReadReq_miss_latency::cpu.inst 941588486 # number of ReadReq miss cycles
616system.cpu.icache.ReadReq_miss_latency::total 941588486 # number of ReadReq miss cycles
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630system.cpu.icache.demand_miss_rate::total 0.000912 # miss rate for demand accesses
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636system.cpu.icache.demand_avg_miss_latency::total 6372.159265 # average overall miss latency
637system.cpu.icache.overall_avg_miss_latency::cpu.inst 6372.159265 # average overall miss latency
638system.cpu.icache.overall_avg_miss_latency::total 6372.159265 # average overall miss latency
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641system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked
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644system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
645system.cpu.icache.fast_writes 0 # number of fast writes performed
646system.cpu.icache.cache_copies 0 # number of cache copies performed
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649system.cpu.icache.demand_mshr_hits::cpu.inst 1977 # number of demand (read+write) MSHR hits
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652system.cpu.icache.overall_mshr_hits::total 1977 # number of overall MSHR hits
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654system.cpu.icache.ReadReq_mshr_misses::total 145789 # number of ReadReq MSHR misses
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657system.cpu.icache.overall_mshr_misses::cpu.inst 145789 # number of overall MSHR misses
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660system.cpu.icache.ReadReq_mshr_miss_latency::total 560897259 # number of ReadReq MSHR miss cycles
661system.cpu.icache.demand_mshr_miss_latency::cpu.inst 560897259 # number of demand (read+write) MSHR miss cycles
662system.cpu.icache.demand_mshr_miss_latency::total 560897259 # number of demand (read+write) MSHR miss cycles
663system.cpu.icache.overall_mshr_miss_latency::cpu.inst 560897259 # number of overall MSHR miss cycles
664system.cpu.icache.overall_mshr_miss_latency::total 560897259 # number of overall MSHR miss cycles
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666system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000900 # mshr miss rate for ReadReq accesses
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668system.cpu.icache.demand_mshr_miss_rate::total 0.000900 # mshr miss rate for demand accesses
669system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000900 # mshr miss rate for overall accesses
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671system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3847.322219 # average ReadReq mshr miss latency
672system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.322219 # average ReadReq mshr miss latency
673system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3847.322219 # average overall mshr miss latency
674system.cpu.icache.demand_avg_mshr_miss_latency::total 3847.322219 # average overall mshr miss latency
675system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3847.322219 # average overall mshr miss latency
676system.cpu.icache.overall_avg_mshr_miss_latency::total 3847.322219 # average overall mshr miss latency
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679system.cpu.l2cache.tags.tagsinuse 29664.192610 # Cycle average of tags in use
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681system.cpu.l2cache.tags.sampled_refs 385281 # Sample count of references to valid blocks.
682system.cpu.l2cache.tags.avg_refs 9.597034 # Average number of references to valid blocks.
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685system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.120798 # Average occupied blocks per requestor
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691system.cpu.l2cache.tags.occ_task_id_blocks::1024 32376 # Occupied blocks per task id
692system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
693system.cpu.l2cache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
694system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11697 # Occupied blocks per task id
695system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20354 # Occupied blocks per task id
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703system.cpu.l2cache.Writeback_hits::total 2330726 # number of Writeback hits
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705system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits
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712system.cpu.l2cache.overall_hits::cpu.data 2151566 # number of overall hits
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718system.cpu.l2cache.UpgradeReq_misses::total 137429 # number of UpgradeReq misses
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739system.cpu.l2cache.overall_miss_latency::total 27616182433 # number of overall miss cycles
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743system.cpu.l2cache.Writeback_accesses::writebacks 2330726 # number of Writeback accesses(hits+misses)
744system.cpu.l2cache.Writeback_accesses::total 2330726 # number of Writeback accesses(hits+misses)
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758system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989723 # miss rate for UpgradeReq accesses
759system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989723 # miss rate for UpgradeReq accesses
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765system.cpu.l2cache.overall_miss_rate::cpu.inst 0.460694 # miss rate for overall accesses
766system.cpu.l2cache.overall_miss_rate::cpu.data 0.150931 # miss rate for overall accesses
767system.cpu.l2cache.overall_miss_rate::total 0.151764 # miss rate for overall accesses
768system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74994.439148 # average ReadReq miss latency
769system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72507.569075 # average ReadReq miss latency
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771system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48.917703 # average UpgradeReq miss latency
772system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48.917703 # average UpgradeReq miss latency
773system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70809.051243 # average ReadExReq miss latency
774system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70809.051243 # average ReadExReq miss latency
775system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74994.439148 # average overall miss latency
776system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71589.081644 # average overall miss latency
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778system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74994.439148 # average overall miss latency
779system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71589.081644 # average overall miss latency
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782system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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784system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
785system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
786system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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788system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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790system.cpu.l2cache.writebacks::total 293595 # number of writebacks
791system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3147 # number of ReadReq MSHR misses
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795system.cpu.l2cache.UpgradeReq_mshr_misses::total 137429 # number of UpgradeReq MSHR misses
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797system.cpu.l2cache.ReadExReq_mshr_misses::total 206820 # number of ReadExReq MSHR misses
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828system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150931 # mshr miss rate for overall accesses
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834system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.021306 # average UpgradeReq mshr miss latency
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840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62497.457896 # average overall mshr miss latency
841system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58882.958553 # average overall mshr miss latency
842system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.456827 # average overall mshr miss latency
843system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
844system.cpu.dcache.tags.replacements 2529933 # number of replacements
845system.cpu.dcache.tags.tagsinuse 4088.224261 # Cycle average of tags in use
846system.cpu.dcache.tags.total_refs 395924693 # Total number of references to valid blocks.
847system.cpu.dcache.tags.sampled_refs 2534029 # Sample count of references to valid blocks.
848system.cpu.dcache.tags.avg_refs 156.243158 # Average number of references to valid blocks.
849system.cpu.dcache.tags.warmup_cycle 1796857250 # Cycle when the warmup percentage was hit.
850system.cpu.dcache.tags.occ_blocks::cpu.data 4088.224261 # Average occupied blocks per requestor
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852system.cpu.dcache.tags.occ_percent::total 0.998102 # Average percentage of cache occupancy
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854system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
855system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
856system.cpu.dcache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id
857system.cpu.dcache.tags.age_task_id_blocks_1024::3 3301 # Occupied blocks per task id
858system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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860system.cpu.dcache.tags.data_accesses 800965525 # Number of data accesses
861system.cpu.dcache.ReadReq_hits::cpu.data 247184750 # number of ReadReq hits
862system.cpu.dcache.ReadReq_hits::total 247184750 # number of ReadReq hits
863system.cpu.dcache.WriteReq_hits::cpu.data 148232864 # number of WriteReq hits
864system.cpu.dcache.WriteReq_hits::total 148232864 # number of WriteReq hits
865system.cpu.dcache.demand_hits::cpu.data 395417614 # number of demand (read+write) hits
866system.cpu.dcache.demand_hits::total 395417614 # number of demand (read+write) hits
867system.cpu.dcache.overall_hits::cpu.data 395417614 # number of overall hits
868system.cpu.dcache.overall_hits::total 395417614 # number of overall hits
869system.cpu.dcache.ReadReq_misses::cpu.data 2870796 # number of ReadReq misses
870system.cpu.dcache.ReadReq_misses::total 2870796 # number of ReadReq misses
871system.cpu.dcache.WriteReq_misses::cpu.data 927338 # number of WriteReq misses
872system.cpu.dcache.WriteReq_misses::total 927338 # number of WriteReq misses
873system.cpu.dcache.demand_misses::cpu.data 3798134 # number of demand (read+write) misses
874system.cpu.dcache.demand_misses::total 3798134 # number of demand (read+write) misses
875system.cpu.dcache.overall_misses::cpu.data 3798134 # number of overall misses
876system.cpu.dcache.overall_misses::total 3798134 # number of overall misses
877system.cpu.dcache.ReadReq_miss_latency::cpu.data 57044971459 # number of ReadReq miss cycles
878system.cpu.dcache.ReadReq_miss_latency::total 57044971459 # number of ReadReq miss cycles
879system.cpu.dcache.WriteReq_miss_latency::cpu.data 26405527365 # number of WriteReq miss cycles
880system.cpu.dcache.WriteReq_miss_latency::total 26405527365 # number of WriteReq miss cycles
881system.cpu.dcache.demand_miss_latency::cpu.data 83450498824 # number of demand (read+write) miss cycles
882system.cpu.dcache.demand_miss_latency::total 83450498824 # number of demand (read+write) miss cycles
883system.cpu.dcache.overall_miss_latency::cpu.data 83450498824 # number of overall miss cycles
884system.cpu.dcache.overall_miss_latency::total 83450498824 # number of overall miss cycles
885system.cpu.dcache.ReadReq_accesses::cpu.data 250055546 # number of ReadReq accesses(hits+misses)
886system.cpu.dcache.ReadReq_accesses::total 250055546 # number of ReadReq accesses(hits+misses)
887system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
888system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
889system.cpu.dcache.demand_accesses::cpu.data 399215748 # number of demand (read+write) accesses
890system.cpu.dcache.demand_accesses::total 399215748 # number of demand (read+write) accesses
891system.cpu.dcache.overall_accesses::cpu.data 399215748 # number of overall (read+write) accesses
892system.cpu.dcache.overall_accesses::total 399215748 # number of overall (read+write) accesses
893system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011481 # miss rate for ReadReq accesses
894system.cpu.dcache.ReadReq_miss_rate::total 0.011481 # miss rate for ReadReq accesses
895system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006217 # miss rate for WriteReq accesses
896system.cpu.dcache.WriteReq_miss_rate::total 0.006217 # miss rate for WriteReq accesses
897system.cpu.dcache.demand_miss_rate::cpu.data 0.009514 # miss rate for demand accesses
898system.cpu.dcache.demand_miss_rate::total 0.009514 # miss rate for demand accesses
899system.cpu.dcache.overall_miss_rate::cpu.data 0.009514 # miss rate for overall accesses
900system.cpu.dcache.overall_miss_rate::total 0.009514 # miss rate for overall accesses
901system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19870.785475 # average ReadReq miss latency
902system.cpu.dcache.ReadReq_avg_miss_latency::total 19870.785475 # average ReadReq miss latency
903system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28474.544734 # average WriteReq miss latency
904system.cpu.dcache.WriteReq_avg_miss_latency::total 28474.544734 # average WriteReq miss latency
905system.cpu.dcache.demand_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency
906system.cpu.dcache.demand_avg_miss_latency::total 21971.446722 # average overall miss latency
907system.cpu.dcache.overall_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency
908system.cpu.dcache.overall_avg_miss_latency::total 21971.446722 # average overall miss latency
909system.cpu.dcache.blocked_cycles::no_mshrs 6569 # number of cycles access was blocked
910system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
911system.cpu.dcache.blocked::no_mshrs 666 # number of cycles access was blocked
912system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
913system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.863363 # average number of cycles each access was blocked
914system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
915system.cpu.dcache.fast_writes 0 # number of fast writes performed
916system.cpu.dcache.cache_copies 0 # number of cache copies performed
917system.cpu.dcache.writebacks::writebacks 2330726 # number of writebacks
918system.cpu.dcache.writebacks::total 2330726 # number of writebacks
919system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1108238 # number of ReadReq MSHR hits
920system.cpu.dcache.ReadReq_mshr_hits::total 1108238 # number of ReadReq MSHR hits
921system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17013 # number of WriteReq MSHR hits
922system.cpu.dcache.WriteReq_mshr_hits::total 17013 # number of WriteReq MSHR hits
923system.cpu.dcache.demand_mshr_hits::cpu.data 1125251 # number of demand (read+write) MSHR hits
924system.cpu.dcache.demand_mshr_hits::total 1125251 # number of demand (read+write) MSHR hits
925system.cpu.dcache.overall_mshr_hits::cpu.data 1125251 # number of overall MSHR hits
926system.cpu.dcache.overall_mshr_hits::total 1125251 # number of overall MSHR hits
927system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762558 # number of ReadReq MSHR misses
928system.cpu.dcache.ReadReq_mshr_misses::total 1762558 # number of ReadReq MSHR misses
929system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910325 # number of WriteReq MSHR misses
930system.cpu.dcache.WriteReq_mshr_misses::total 910325 # number of WriteReq MSHR misses
931system.cpu.dcache.demand_mshr_misses::cpu.data 2672883 # number of demand (read+write) MSHR misses
932system.cpu.dcache.demand_mshr_misses::total 2672883 # number of demand (read+write) MSHR misses
933system.cpu.dcache.overall_mshr_misses::cpu.data 2672883 # number of overall MSHR misses
934system.cpu.dcache.overall_mshr_misses::total 2672883 # number of overall MSHR misses
935system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30399879250 # number of ReadReq MSHR miss cycles
936system.cpu.dcache.ReadReq_mshr_miss_latency::total 30399879250 # number of ReadReq MSHR miss cycles
937system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24280652885 # number of WriteReq MSHR miss cycles
938system.cpu.dcache.WriteReq_mshr_miss_latency::total 24280652885 # number of WriteReq MSHR miss cycles
939system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54680532135 # number of demand (read+write) MSHR miss cycles
940system.cpu.dcache.demand_mshr_miss_latency::total 54680532135 # number of demand (read+write) MSHR miss cycles
941system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54680532135 # number of overall MSHR miss cycles
942system.cpu.dcache.overall_mshr_miss_latency::total 54680532135 # number of overall MSHR miss cycles
943system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007049 # mshr miss rate for ReadReq accesses
944system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007049 # mshr miss rate for ReadReq accesses
945system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006103 # mshr miss rate for WriteReq accesses
946system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006103 # mshr miss rate for WriteReq accesses
947system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for demand accesses
948system.cpu.dcache.demand_mshr_miss_rate::total 0.006695 # mshr miss rate for demand accesses
949system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for overall accesses
950system.cpu.dcache.overall_mshr_miss_rate::total 0.006695 # mshr miss rate for overall accesses
951system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17247.590859 # average ReadReq mshr miss latency
952system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17247.590859 # average ReadReq mshr miss latency
953system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26672.510241 # average WriteReq mshr miss latency
954system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26672.510241 # average WriteReq mshr miss latency
955system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency
956system.cpu.dcache.demand_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency
957system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency
958system.cpu.dcache.overall_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency
959system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
960
961---------- End Simulation Statistics ----------