1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.458276 # Number of seconds simulated
4sim_ticks 458276279000 # Number of ticks simulated
5final_tick 458276279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 81967 # Simulator instruction rate (inst/s)
8host_op_rate 151565 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 45427941 # Simulator tick rate (ticks/s)
10host_mem_usage 343960 # Number of bytes of host memory used
11host_seconds 10087.98 # Real time elapsed on the host
12sim_insts 826877109 # Number of instructions simulated
13sim_ops 1528988701 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 24475520 # Number of bytes read from this memory
16system.physmem.bytes_read::total 24678208 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 18791744 # Number of bytes written to this memory
20system.physmem.bytes_written::total 18791744 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 382430 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 385597 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 293621 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 293621 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 442283 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 53407783 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 53850066 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 442283 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 442283 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 41005273 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 41005273 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 41005273 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 442283 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 53407783 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 94855339 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 385597 # Total number of read requests accepted by DRAM controller
38system.physmem.writeReqs 293621 # Total number of write requests accepted by DRAM controller
39system.physmem.readBursts 385597 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
40system.physmem.writeBursts 293621 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
41system.physmem.bytesRead 24678208 # Total number of bytes read from memory
42system.physmem.bytesWritten 18791744 # Total number of bytes written to memory
43system.physmem.bytesConsumedRd 24678208 # bytesRead derated as per pkt->getSize()
44system.physmem.bytesConsumedWr 18791744 # bytesWritten derated as per pkt->getSize()
45system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by write Q
46system.physmem.neitherReadNorWrite 129454 # Reqs where no action is needed
47system.physmem.perBankRdReqs::0 24004 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::1 26368 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::2 24819 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::3 24535 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::4 23440 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::5 23690 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::6 24438 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::7 24255 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::8 23670 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::9 23840 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::10 24809 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::11 23982 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::12 23151 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::13 22850 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::14 23658 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::15 23921 # Track reads on a per bank basis
63system.physmem.perBankWrReqs::0 18532 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::1 19819 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::2 18953 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::3 18919 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::4 18083 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::5 18410 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::6 18967 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::7 18941 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::8 18561 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::9 18114 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::10 18821 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::11 17718 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::12 17344 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::13 16935 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::14 17686 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::15 17818 # Track writes on a per bank basis
79system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
80system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry
81system.physmem.totGap 458276251500 # Total gap between requests
82system.physmem.readPktSize::0 0 # Categorize read packet sizes
83system.physmem.readPktSize::1 0 # Categorize read packet sizes
84system.physmem.readPktSize::2 0 # Categorize read packet sizes
85system.physmem.readPktSize::3 0 # Categorize read packet sizes
86system.physmem.readPktSize::4 0 # Categorize read packet sizes
87system.physmem.readPktSize::5 0 # Categorize read packet sizes
88system.physmem.readPktSize::6 385597 # Categorize read packet sizes
89system.physmem.writePktSize::0 0 # Categorize write packet sizes
90system.physmem.writePktSize::1 0 # Categorize write packet sizes
91system.physmem.writePktSize::2 0 # Categorize write packet sizes
92system.physmem.writePktSize::3 0 # Categorize write packet sizes
93system.physmem.writePktSize::4 0 # Categorize write packet sizes
94system.physmem.writePktSize::5 0 # Categorize write packet sizes
95system.physmem.writePktSize::6 293621 # Categorize write packet sizes
96system.physmem.rdQLenPdf::0 380795 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 4297 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

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120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128system.physmem.wrQLenPdf::0 12731 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::1 12737 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::2 12740 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::4 12741 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::5 12744 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::6 12749 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::7 12750 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 12753 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 30 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see
160system.physmem.bytesPerActivate::samples 125846 # Bytes accessed per row activation
161system.physmem.bytesPerActivate::mean 345.334329 # Bytes accessed per row activation
162system.physmem.bytesPerActivate::gmean 162.235120 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::stdev 666.634247 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::64-65 53836 42.78% 42.78% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::128-129 23576 18.73% 61.51% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::192-193 10431 8.29% 69.80% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::256-257 6405 5.09% 74.89% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::320-321 4091 3.25% 78.14% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::384-385 2950 2.34% 80.49% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::448-449 2205 1.75% 82.24% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::512-513 1721 1.37% 83.61% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::576-577 1423 1.13% 84.74% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::640-641 1129 0.90% 85.63% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::704-705 1178 0.94% 86.57% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::768-769 1088 0.86% 87.43% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::832-833 719 0.57% 88.01% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::896-897 691 0.55% 88.56% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::960-961 593 0.47% 89.03% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1024-1025 590 0.47% 89.50% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1088-1089 543 0.43% 89.93% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1152-1153 555 0.44% 90.37% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1216-1217 625 0.50% 90.86% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1280-1281 694 0.55% 91.42% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1344-1345 625 0.50% 91.91% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1408-1409 735 0.58% 92.50% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1472-1473 6224 4.95% 97.44% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1536-1537 501 0.40% 97.84% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1600-1601 329 0.26% 98.10% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1664-1665 262 0.21% 98.31% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1728-1729 235 0.19% 98.50% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1792-1793 154 0.12% 98.62% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1856-1857 168 0.13% 98.75% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1920-1921 127 0.10% 98.85% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1984-1985 91 0.07% 98.93% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2048-2049 78 0.06% 98.99% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::2112-2113 63 0.05% 99.04% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::2176-2177 57 0.05% 99.08% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2240-2241 48 0.04% 99.12% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2304-2305 48 0.04% 99.16% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::2368-2369 32 0.03% 99.18% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::2432-2433 31 0.02% 99.21% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.23% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.25% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::2624-2625 34 0.03% 99.28% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::2688-2689 24 0.02% 99.30% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2752-2753 22 0.02% 99.31% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2816-2817 28 0.02% 99.34% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.35% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2944-2945 15 0.01% 99.37% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::3008-3009 11 0.01% 99.37% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::3072-3073 26 0.02% 99.39% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::3136-3137 10 0.01% 99.40% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::3200-3201 12 0.01% 99.41% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::3264-3265 9 0.01% 99.42% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.44% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::3456-3457 11 0.01% 99.45% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::3520-3521 10 0.01% 99.46% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::3648-3649 11 0.01% 99.48% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3776-3777 9 0.01% 99.49% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3840-3841 9 0.01% 99.50% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.51% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::4032-4033 4 0.00% 99.51% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::4096-4097 11 0.01% 99.52% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::4160-4161 3 0.00% 99.53% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.53% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::4288-4289 5 0.00% 99.53% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::4352-4353 10 0.01% 99.54% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::4416-4417 5 0.00% 99.54% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.55% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.55% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4672-4673 4 0.00% 99.56% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::4736-4737 4 0.00% 99.56% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.56% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.57% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::5056-5057 12 0.01% 99.59% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.59% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.60% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::5376-5377 10 0.01% 99.60% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.61% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::5504-5505 9 0.01% 99.61% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::5568-5569 8 0.01% 99.62% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.62% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.62% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.63% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.63% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5888-5889 5 0.00% 99.63% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.64% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.64% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.65% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::6656-6657 4 0.00% 99.66% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.66% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.67% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.67% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.67% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.68% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.68% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.68% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.68% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.69% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.69% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::7616-7617 3 0.00% 99.69% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.69% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::7744-7745 3 0.00% 99.69% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.70% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::8192-8193 376 0.30% 100.00% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::total 125846 # Bytes accessed per row activation
291system.physmem.totQLat 3013395500 # Total cycles spent in queuing delays
292system.physmem.totMemAccLat 11189631750 # Sum of mem lat for all requests
293system.physmem.totBusLat 1927150000 # Total cycles spent in databus access
294system.physmem.totBankLat 6249086250 # Total cycles spent in bank access
295system.physmem.avgQLat 7818.27 # Average queueing delay per request
296system.physmem.avgBankLat 16213.28 # Average bank access latency per request
297system.physmem.avgBusLat 5000.00 # Average bus latency per request
298system.physmem.avgMemAccLat 29031.55 # Average memory access latency
299system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s
300system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s
301system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s
302system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s
303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
304system.physmem.busUtil 0.74 # Data bus utilization in percentage
305system.physmem.avgRdQLen 0.02 # Average read queue length over time
306system.physmem.avgWrQLen 10.13 # Average write queue length over time
307system.physmem.readRowHits 346215 # Number of row buffer hits during reads
308system.physmem.writeRowHits 206987 # Number of row buffer hits during writes
309system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads
310system.physmem.writeRowHitRate 70.49 # Row buffer hit rate for writes
311system.physmem.avgGap 674711.58 # Average gap between requests
312system.membus.throughput 94855339 # Throughput (bytes/s)
313system.membus.trans_dist::ReadReq 178753 # Transaction distribution
314system.membus.trans_dist::ReadResp 178753 # Transaction distribution
315system.membus.trans_dist::Writeback 293621 # Transaction distribution
316system.membus.trans_dist::UpgradeReq 129454 # Transaction distribution
317system.membus.trans_dist::UpgradeResp 129454 # Transaction distribution
318system.membus.trans_dist::ReadExReq 206844 # Transaction distribution
319system.membus.trans_dist::ReadExResp 206844 # Transaction distribution
320system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1323723 # Packet count per connected master and slave (bytes)
321system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1323723 # Packet count per connected master and slave (bytes)
322system.membus.pkt_count::total 1323723 # Packet count per connected master and slave (bytes)
323system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469952 # Cumulative packet size per connected master and slave (bytes)
324system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469952 # Cumulative packet size per connected master and slave (bytes)
325system.membus.tot_pkt_size::total 43469952 # Cumulative packet size per connected master and slave (bytes)
326system.membus.data_through_bus 43469952 # Total data (bytes)
327system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
328system.membus.reqLayer0.occupancy 3387419250 # Layer occupancy (ticks)
329system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
330system.membus.respLayer1.occupancy 3898953053 # Layer occupancy (ticks)
331system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
332system.cpu.branchPred.lookups 205598458 # Number of BP lookups
333system.cpu.branchPred.condPredicted 205598458 # Number of conditional branches predicted
334system.cpu.branchPred.condIncorrect 9896380 # Number of conditional branches incorrect
335system.cpu.branchPred.BTBLookups 117174051 # Number of BTB lookups
336system.cpu.branchPred.BTBHits 114692881 # Number of BTB hits
337system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
338system.cpu.branchPred.BTBHitPct 97.882492 # BTB Hit Percentage
339system.cpu.branchPred.usedRAS 25059076 # Number of times the RAS was used to get a target.
340system.cpu.branchPred.RASInCorrect 1793638 # Number of incorrect RAS predictions.
341system.cpu.workload.num_syscalls 551 # Number of system calls
342system.cpu.numCycles 916711426 # number of cpu cycles simulated
343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
345system.cpu.fetch.icacheStallCycles 167358741 # Number of cycles fetch is stalled on an Icache miss
346system.cpu.fetch.Insts 1131763090 # Number of instructions fetch has processed
347system.cpu.fetch.Branches 205598458 # Number of branches that fetch encountered
348system.cpu.fetch.predictedBranches 139751957 # Number of branches that fetch has predicted taken
349system.cpu.fetch.Cycles 352259726 # Number of cycles fetch has run and was not squashing or blocked
350system.cpu.fetch.SquashCycles 71078928 # Number of cycles fetch has spent squashing
351system.cpu.fetch.BlockedCycles 303625713 # Number of cycles fetch has spent blocked
352system.cpu.fetch.MiscStallCycles 47908 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
353system.cpu.fetch.PendingTrapStallCycles 254198 # Number of stall cycles due to pending traps
354system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR
355system.cpu.fetch.CacheLines 162013852 # Number of cache lines fetched
356system.cpu.fetch.IcacheSquashes 2539166 # Number of outstanding Icache misses that were squashed
357system.cpu.fetch.rateDist::samples 884476430 # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::mean 2.380618 # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::stdev 3.325214 # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::0 536284008 60.63% 60.63% # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.rateDist::1 23384253 2.64% 63.28% # Number of instructions fetched each cycle (Total)
363system.cpu.fetch.rateDist::2 25253496 2.86% 66.13% # Number of instructions fetched each cycle (Total)
364system.cpu.fetch.rateDist::3 27902300 3.15% 69.29% # Number of instructions fetched each cycle (Total)
365system.cpu.fetch.rateDist::4 17749201 2.01% 71.29% # Number of instructions fetched each cycle (Total)
366system.cpu.fetch.rateDist::5 22913352 2.59% 73.88% # Number of instructions fetched each cycle (Total)
367system.cpu.fetch.rateDist::6 29416028 3.33% 77.21% # Number of instructions fetched each cycle (Total)
368system.cpu.fetch.rateDist::7 26647385 3.01% 80.22% # Number of instructions fetched each cycle (Total)
369system.cpu.fetch.rateDist::8 174926407 19.78% 100.00% # Number of instructions fetched each cycle (Total)
370system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
371system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
372system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
373system.cpu.fetch.rateDist::total 884476430 # Number of instructions fetched each cycle (Total)
374system.cpu.fetch.branchRate 0.224278 # Number of branch fetches per cycle
375system.cpu.fetch.rate 1.234590 # Number of inst fetches per cycle
376system.cpu.decode.IdleCycles 222500802 # Number of cycles decode is idle
377system.cpu.decode.BlockedCycles 258763432 # Number of cycles decode is blocked
378system.cpu.decode.RunCycles 295392395 # Number of cycles decode is running
379system.cpu.decode.UnblockCycles 46889742 # Number of cycles decode is unblocking
380system.cpu.decode.SquashCycles 60930059 # Number of cycles decode is squashing
381system.cpu.decode.DecodedInsts 2071354254 # Number of instructions handled by decode
382system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
383system.cpu.rename.SquashCycles 60930059 # Number of cycles rename is squashing
384system.cpu.rename.IdleCycles 255984410 # Number of cycles rename is idle
385system.cpu.rename.BlockCycles 114277740 # Number of cycles rename is blocking
386system.cpu.rename.serializeStallCycles 18348 # count of cycles rename stalled for serializing inst
387system.cpu.rename.RunCycles 306680368 # Number of cycles rename is running
388system.cpu.rename.UnblockCycles 146585505 # Number of cycles rename is unblocking
389system.cpu.rename.RenamedInsts 2035184371 # Number of instructions processed by rename
390system.cpu.rename.ROBFullEvents 17660 # Number of times rename has blocked due to ROB full
391system.cpu.rename.IQFullEvents 24877077 # Number of times rename has blocked due to IQ full
392system.cpu.rename.LSQFullEvents 106438010 # Number of times rename has blocked due to LSQ full
393system.cpu.rename.RenamedOperands 2138008878 # Number of destination operands rename has renamed
394system.cpu.rename.RenameLookups 5150477195 # Number of register rename lookups that rename has made
395system.cpu.rename.int_rename_lookups 3273486109 # Number of integer rename lookups
396system.cpu.rename.fp_rename_lookups 27867 # Number of floating rename lookups
397system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
398system.cpu.rename.UndoneMaps 523968024 # Number of HB maps that are undone due to squashing
399system.cpu.rename.serializingInsts 1260 # count of serializing insts renamed
400system.cpu.rename.tempSerializingInsts 1188 # count of temporary serializing insts renamed
401system.cpu.rename.skidInsts 346256555 # count of insts added to the skid buffer
402system.cpu.memDep0.insertedLoads 495848123 # Number of loads inserted to the mem dependence unit.
403system.cpu.memDep0.insertedStores 194451746 # Number of stores inserted to the mem dependence unit.
404system.cpu.memDep0.conflictingLoads 195373810 # Number of conflicting loads.
405system.cpu.memDep0.conflictingStores 54752041 # Number of conflicting stores.
406system.cpu.iq.iqInstsAdded 1975440933 # Number of instructions added to the IQ (excludes non-spec)
407system.cpu.iq.iqNonSpecInstsAdded 14060 # Number of non-speculative instructions added to the IQ
408system.cpu.iq.iqInstsIssued 1772196947 # Number of instructions issued
409system.cpu.iq.iqSquashedInstsIssued 491373 # Number of squashed instructions issued
410system.cpu.iq.iqSquashedInstsExamined 441593338 # Number of squashed instructions iterated over during squash; mainly for profiling
411system.cpu.iq.iqSquashedOperandsExamined 734714175 # Number of squashed operands that are examined and possibly removed from graph
412system.cpu.iq.iqSquashedNonSpecRemoved 13508 # Number of squashed non-spec instructions that were removed
413system.cpu.iq.issued_per_cycle::samples 884476430 # Number of insts issued each cycle
414system.cpu.iq.issued_per_cycle::mean 2.003668 # Number of insts issued each cycle
415system.cpu.iq.issued_per_cycle::stdev 1.883218 # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::0 267871954 30.29% 30.29% # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::1 151795933 17.16% 47.45% # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::2 137193879 15.51% 62.96% # Number of insts issued each cycle
420system.cpu.iq.issued_per_cycle::3 131984117 14.92% 77.88% # Number of insts issued each cycle
421system.cpu.iq.issued_per_cycle::4 91584837 10.35% 88.24% # Number of insts issued each cycle
422system.cpu.iq.issued_per_cycle::5 55972472 6.33% 94.56% # Number of insts issued each cycle
423system.cpu.iq.issued_per_cycle::6 34407043 3.89% 98.45% # Number of insts issued each cycle
424system.cpu.iq.issued_per_cycle::7 11912621 1.35% 99.80% # Number of insts issued each cycle
425system.cpu.iq.issued_per_cycle::8 1753574 0.20% 100.00% # Number of insts issued each cycle
426system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
427system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
428system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
429system.cpu.iq.issued_per_cycle::total 884476430 # Number of insts issued each cycle
430system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
431system.cpu.iq.fu_full::IntAlu 4900873 32.33% 32.33% # attempts to use FU when none available
432system.cpu.iq.fu_full::IntMult 0 0.00% 32.33% # attempts to use FU when none available
433system.cpu.iq.fu_full::IntDiv 0 0.00% 32.33% # attempts to use FU when none available
434system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.33% # attempts to use FU when none available
435system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.33% # attempts to use FU when none available
436system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.33% # attempts to use FU when none available
437system.cpu.iq.fu_full::FloatMult 0 0.00% 32.33% # attempts to use FU when none available
438system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.33% # attempts to use FU when none available
439system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.33% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.33% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.33% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.33% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.33% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.33% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.33% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdMult 0 0.00% 32.33% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.33% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdShift 0 0.00% 32.33% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.33% # attempts to use FU when none available
450system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.33% # attempts to use FU when none available
451system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.33% # attempts to use FU when none available
452system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.33% # attempts to use FU when none available
453system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.33% # attempts to use FU when none available
454system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.33% # attempts to use FU when none available
455system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.33% # attempts to use FU when none available
456system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.33% # attempts to use FU when none available
457system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.33% # attempts to use FU when none available
458system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.33% # attempts to use FU when none available
459system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.33% # attempts to use FU when none available
460system.cpu.iq.fu_full::MemRead 7664927 50.56% 82.88% # attempts to use FU when none available
461system.cpu.iq.fu_full::MemWrite 2594883 17.12% 100.00% # attempts to use FU when none available
462system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
463system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
464system.cpu.iq.FU_type_0::No_OpClass 2622931 0.15% 0.15% # Type of FU issued
465system.cpu.iq.FU_type_0::IntAlu 1165806661 65.78% 65.93% # Type of FU issued
466system.cpu.iq.FU_type_0::IntMult 353241 0.02% 65.95% # Type of FU issued
467system.cpu.iq.FU_type_0::IntDiv 3880883 0.22% 66.17% # Type of FU issued
468system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued
469system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
470system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
471system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
472system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
473system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued

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486system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
487system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
488system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
489system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
490system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
491system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
492system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
493system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
494system.cpu.iq.FU_type_0::MemRead 429278261 24.22% 90.39% # Type of FU issued
495system.cpu.iq.FU_type_0::MemWrite 170254965 9.61% 100.00% # Type of FU issued
496system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
497system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
498system.cpu.iq.FU_type_0::total 1772196947 # Type of FU issued
499system.cpu.iq.rate 1.933211 # Inst issue rate
500system.cpu.iq.fu_busy_cnt 15160683 # FU busy when requested
501system.cpu.iq.fu_busy_rate 0.008555 # FU busy rate (busy events/executed inst)
502system.cpu.iq.int_inst_queue_reads 4444507102 # Number of integer instruction queue reads
503system.cpu.iq.int_inst_queue_writes 2417272272 # Number of integer instruction queue writes
504system.cpu.iq.int_inst_queue_wakeup_accesses 1744936391 # Number of integer instruction queue wakeup accesses
505system.cpu.iq.fp_inst_queue_reads 15278 # Number of floating instruction queue reads
506system.cpu.iq.fp_inst_queue_writes 33048 # Number of floating instruction queue writes
507system.cpu.iq.fp_inst_queue_wakeup_accesses 3640 # Number of floating instruction queue wakeup accesses
508system.cpu.iq.int_alu_accesses 1784727445 # Number of integer alu accesses
509system.cpu.iq.fp_alu_accesses 7254 # Number of floating point alu accesses
510system.cpu.iew.lsq.thread0.forwLoads 172555642 # Number of loads that had data forwarded from stores
511system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
512system.cpu.iew.lsq.thread0.squashedLoads 111746790 # Number of loads squashed
513system.cpu.iew.lsq.thread0.ignoredResponses 385650 # Number of memory responses ignored because the instruction is squashed
514system.cpu.iew.lsq.thread0.memOrderViolation 328822 # Number of memory ordering violations
515system.cpu.iew.lsq.thread0.squashedStores 45291560 # Number of stores squashed
516system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
517system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
518system.cpu.iew.lsq.thread0.rescheduledLoads 15317 # Number of loads that were rescheduled
519system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked
520system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
521system.cpu.iew.iewSquashCycles 60930059 # Number of cycles IEW is squashing
522system.cpu.iew.iewBlockCycles 66792766 # Number of cycles IEW is blocking
523system.cpu.iew.iewUnblockCycles 7181188 # Number of cycles IEW is unblocking
524system.cpu.iew.iewDispatchedInsts 1975454993 # Number of instructions dispatched to IQ
525system.cpu.iew.iewDispSquashedInsts 789344 # Number of squashed instructions skipped by dispatch
526system.cpu.iew.iewDispLoadInsts 495848947 # Number of dispatched load instructions
527system.cpu.iew.iewDispStoreInsts 194451746 # Number of dispatched store instructions
528system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions
529system.cpu.iew.iewIQFullEvents 4469390 # Number of times the IQ has become full, causing a stall
530system.cpu.iew.iewLSQFullEvents 83563 # Number of times the LSQ has become full, causing a stall
531system.cpu.iew.memOrderViolationEvents 328822 # Number of memory order violations
532system.cpu.iew.predictedTakenIncorrect 5897715 # Number of branches that were predicted taken incorrectly
533system.cpu.iew.predictedNotTakenIncorrect 4420728 # Number of branches that were predicted not taken incorrectly
534system.cpu.iew.branchMispredicts 10318443 # Number of branch mispredicts detected at execute
535system.cpu.iew.iewExecutedInsts 1753033326 # Number of executed instructions
536system.cpu.iew.iewExecLoadInsts 424140898 # Number of load instructions executed
537system.cpu.iew.iewExecSquashedInsts 19163621 # Number of squashed instructions skipped in execute
538system.cpu.iew.exec_swp 0 # number of swp insts executed
539system.cpu.iew.exec_nop 0 # number of nop insts executed
540system.cpu.iew.exec_refs 590949993 # number of memory reference insts executed
541system.cpu.iew.exec_branches 167484534 # Number of branches executed
542system.cpu.iew.exec_stores 166809095 # Number of stores executed
543system.cpu.iew.exec_rate 1.912307 # Inst execution rate
544system.cpu.iew.wb_sent 1749784390 # cumulative count of insts sent to commit
545system.cpu.iew.wb_count 1744940031 # cumulative count of insts written-back
546system.cpu.iew.wb_producers 1325078811 # num instructions producing a value
547system.cpu.iew.wb_consumers 1946006295 # num instructions consuming a value
548system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
549system.cpu.iew.wb_rate 1.903478 # insts written-back per cycle
550system.cpu.iew.wb_fanout 0.680922 # average fanout of values written-back
551system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
552system.cpu.commit.commitSquashedInsts 446495753 # The number of squashed insts skipped by commit
553system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
554system.cpu.commit.branchMispredicts 9924967 # The number of times a branch was mispredicted
555system.cpu.commit.committed_per_cycle::samples 823546371 # Number of insts commited each cycle
556system.cpu.commit.committed_per_cycle::mean 1.856591 # Number of insts commited each cycle
557system.cpu.commit.committed_per_cycle::stdev 2.436968 # Number of insts commited each cycle
558system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
559system.cpu.commit.committed_per_cycle::0 331540397 40.26% 40.26% # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::1 193316161 23.47% 63.73% # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::2 63109500 7.66% 71.39% # Number of insts commited each cycle
562system.cpu.commit.committed_per_cycle::3 92579702 11.24% 82.64% # Number of insts commited each cycle
563system.cpu.commit.committed_per_cycle::4 24975285 3.03% 85.67% # Number of insts commited each cycle
564system.cpu.commit.committed_per_cycle::5 27432624 3.33% 89.00% # Number of insts commited each cycle
565system.cpu.commit.committed_per_cycle::6 9320772 1.13% 90.13% # Number of insts commited each cycle
566system.cpu.commit.committed_per_cycle::7 11449898 1.39% 91.52% # Number of insts commited each cycle
567system.cpu.commit.committed_per_cycle::8 69822032 8.48% 100.00% # Number of insts commited each cycle
568system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
569system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
570system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
571system.cpu.commit.committed_per_cycle::total 823546371 # Number of insts commited each cycle
572system.cpu.commit.committedInsts 826877109 # Number of instructions committed
573system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
574system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
575system.cpu.commit.refs 533262343 # Number of memory references committed
576system.cpu.commit.loads 384102157 # Number of loads committed
577system.cpu.commit.membars 0 # Number of memory barriers committed
578system.cpu.commit.branches 149758583 # Number of branches committed
579system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
580system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
581system.cpu.commit.function_calls 17673145 # Number of function calls committed.
582system.cpu.commit.bw_lim_events 69822032 # number cycles where commit BW limit reached
583system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
584system.cpu.rob.rob_reads 2729208793 # The number of ROB reads
585system.cpu.rob.rob_writes 4012058416 # The number of ROB writes
586system.cpu.timesIdled 3349890 # Number of times that the entire CPU went into an idle state and unscheduled itself
587system.cpu.idleCycles 32234996 # Total number of cycles that the CPU has spent unscheduled due to idling
588system.cpu.committedInsts 826877109 # Number of Instructions Simulated
589system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
590system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
591system.cpu.cpi 1.108643 # CPI: Cycles Per Instruction
592system.cpu.cpi_total 1.108643 # CPI: Total CPI of All Threads
593system.cpu.ipc 0.902004 # IPC: Instructions Per Cycle
594system.cpu.ipc_total 0.902004 # IPC: Total IPC of All Threads
595system.cpu.int_regfile_reads 2716444328 # number of integer regfile reads
596system.cpu.int_regfile_writes 1420478428 # number of integer regfile writes
597system.cpu.fp_regfile_reads 3628 # number of floating regfile reads
598system.cpu.fp_regfile_writes 22 # number of floating regfile writes
599system.cpu.cc_regfile_reads 597234249 # number of cc regfile reads
600system.cpu.cc_regfile_writes 405441134 # number of cc regfile writes
601system.cpu.misc_regfile_reads 964696527 # number of misc regfile reads
602system.cpu.misc_regfile_writes 1 # number of misc regfile writes
603system.cpu.toL2Bus.throughput 698612009 # Throughput (bytes/s)
604system.cpu.toL2Bus.trans_dist::ReadReq 1899997 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::ReadResp 1899996 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::Writeback 2330686 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::UpgradeReq 130874 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::UpgradeResp 130874 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadExReq 771776 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::ReadExResp 771776 # Transaction distribution
611system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 144643 # Packet count per connected master and slave (bytes)
612system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7660372 # Packet count per connected master and slave (bytes)
613system.cpu.toL2Bus.pkt_count::total 7805015 # Packet count per connected master and slave (bytes)
614system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437696 # Cumulative packet size per connected master and slave (bytes)
615system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311337920 # Cumulative packet size per connected master and slave (bytes)
616system.cpu.toL2Bus.tot_pkt_size::total 311775616 # Cumulative packet size per connected master and slave (bytes)
617system.cpu.toL2Bus.data_through_bus 311775616 # Total data (bytes)
618system.cpu.toL2Bus.snoop_data_through_bus 8381696 # Total snoop data (bytes)
619system.cpu.toL2Bus.reqLayer0.occupancy 4900939314 # Layer occupancy (ticks)
620system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
621system.cpu.toL2Bus.respLayer0.occupancy 207374491 # Layer occupancy (ticks)
622system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
623system.cpu.toL2Bus.respLayer1.occupancy 3958743651 # Layer occupancy (ticks)
624system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
625system.cpu.icache.tags.replacements 5318 # number of replacements
626system.cpu.icache.tags.tagsinuse 1036.794557 # Cycle average of tags in use
627system.cpu.icache.tags.total_refs 161872030 # Total number of references to valid blocks.
628system.cpu.icache.tags.sampled_refs 6894 # Sample count of references to valid blocks.
629system.cpu.icache.tags.avg_refs 23480.131999 # Average number of references to valid blocks.
630system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
631system.cpu.icache.tags.occ_blocks::cpu.inst 1036.794557 # Average occupied blocks per requestor
632system.cpu.icache.tags.occ_percent::cpu.inst 0.506247 # Average percentage of cache occupancy
633system.cpu.icache.tags.occ_percent::total 0.506247 # Average percentage of cache occupancy
634system.cpu.icache.ReadReq_hits::cpu.inst 161874097 # number of ReadReq hits
635system.cpu.icache.ReadReq_hits::total 161874097 # number of ReadReq hits
636system.cpu.icache.demand_hits::cpu.inst 161874097 # number of demand (read+write) hits
637system.cpu.icache.demand_hits::total 161874097 # number of demand (read+write) hits
638system.cpu.icache.overall_hits::cpu.inst 161874097 # number of overall hits
639system.cpu.icache.overall_hits::total 161874097 # number of overall hits
640system.cpu.icache.ReadReq_misses::cpu.inst 139755 # number of ReadReq misses
641system.cpu.icache.ReadReq_misses::total 139755 # number of ReadReq misses
642system.cpu.icache.demand_misses::cpu.inst 139755 # number of demand (read+write) misses
643system.cpu.icache.demand_misses::total 139755 # number of demand (read+write) misses
644system.cpu.icache.overall_misses::cpu.inst 139755 # number of overall misses
645system.cpu.icache.overall_misses::total 139755 # number of overall misses
646system.cpu.icache.ReadReq_miss_latency::cpu.inst 916174482 # number of ReadReq miss cycles
647system.cpu.icache.ReadReq_miss_latency::total 916174482 # number of ReadReq miss cycles
648system.cpu.icache.demand_miss_latency::cpu.inst 916174482 # number of demand (read+write) miss cycles
649system.cpu.icache.demand_miss_latency::total 916174482 # number of demand (read+write) miss cycles
650system.cpu.icache.overall_miss_latency::cpu.inst 916174482 # number of overall miss cycles
651system.cpu.icache.overall_miss_latency::total 916174482 # number of overall miss cycles
652system.cpu.icache.ReadReq_accesses::cpu.inst 162013852 # number of ReadReq accesses(hits+misses)
653system.cpu.icache.ReadReq_accesses::total 162013852 # number of ReadReq accesses(hits+misses)
654system.cpu.icache.demand_accesses::cpu.inst 162013852 # number of demand (read+write) accesses
655system.cpu.icache.demand_accesses::total 162013852 # number of demand (read+write) accesses
656system.cpu.icache.overall_accesses::cpu.inst 162013852 # number of overall (read+write) accesses
657system.cpu.icache.overall_accesses::total 162013852 # number of overall (read+write) accesses
658system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000863 # miss rate for ReadReq accesses
659system.cpu.icache.ReadReq_miss_rate::total 0.000863 # miss rate for ReadReq accesses
660system.cpu.icache.demand_miss_rate::cpu.inst 0.000863 # miss rate for demand accesses
661system.cpu.icache.demand_miss_rate::total 0.000863 # miss rate for demand accesses
662system.cpu.icache.overall_miss_rate::cpu.inst 0.000863 # miss rate for overall accesses
663system.cpu.icache.overall_miss_rate::total 0.000863 # miss rate for overall accesses
664system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6555.575700 # average ReadReq miss latency
665system.cpu.icache.ReadReq_avg_miss_latency::total 6555.575700 # average ReadReq miss latency
666system.cpu.icache.demand_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency
667system.cpu.icache.demand_avg_miss_latency::total 6555.575700 # average overall miss latency
668system.cpu.icache.overall_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency
669system.cpu.icache.overall_avg_miss_latency::total 6555.575700 # average overall miss latency
670system.cpu.icache.blocked_cycles::no_mshrs 1833 # number of cycles access was blocked
671system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
672system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
673system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
674system.cpu.icache.avg_blocked_cycles::no_mshrs 166.636364 # average number of cycles each access was blocked
675system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
676system.cpu.icache.fast_writes 0 # number of fast writes performed
677system.cpu.icache.cache_copies 0 # number of cache copies performed
678system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1951 # number of ReadReq MSHR hits
679system.cpu.icache.ReadReq_mshr_hits::total 1951 # number of ReadReq MSHR hits
680system.cpu.icache.demand_mshr_hits::cpu.inst 1951 # number of demand (read+write) MSHR hits
681system.cpu.icache.demand_mshr_hits::total 1951 # number of demand (read+write) MSHR hits
682system.cpu.icache.overall_mshr_hits::cpu.inst 1951 # number of overall MSHR hits
683system.cpu.icache.overall_mshr_hits::total 1951 # number of overall MSHR hits
684system.cpu.icache.ReadReq_mshr_misses::cpu.inst 137804 # number of ReadReq MSHR misses
685system.cpu.icache.ReadReq_mshr_misses::total 137804 # number of ReadReq MSHR misses
686system.cpu.icache.demand_mshr_misses::cpu.inst 137804 # number of demand (read+write) MSHR misses
687system.cpu.icache.demand_mshr_misses::total 137804 # number of demand (read+write) MSHR misses
688system.cpu.icache.overall_mshr_misses::cpu.inst 137804 # number of overall MSHR misses
689system.cpu.icache.overall_mshr_misses::total 137804 # number of overall MSHR misses
690system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 553553258 # number of ReadReq MSHR miss cycles
691system.cpu.icache.ReadReq_mshr_miss_latency::total 553553258 # number of ReadReq MSHR miss cycles
692system.cpu.icache.demand_mshr_miss_latency::cpu.inst 553553258 # number of demand (read+write) MSHR miss cycles
693system.cpu.icache.demand_mshr_miss_latency::total 553553258 # number of demand (read+write) MSHR miss cycles
694system.cpu.icache.overall_mshr_miss_latency::cpu.inst 553553258 # number of overall MSHR miss cycles
695system.cpu.icache.overall_mshr_miss_latency::total 553553258 # number of overall MSHR miss cycles
696system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for ReadReq accesses
697system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000851 # mshr miss rate for ReadReq accesses
698system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for demand accesses
699system.cpu.icache.demand_mshr_miss_rate::total 0.000851 # mshr miss rate for demand accesses
700system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for overall accesses
701system.cpu.icache.overall_mshr_miss_rate::total 0.000851 # mshr miss rate for overall accesses
702system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4016.960741 # average ReadReq mshr miss latency
703system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4016.960741 # average ReadReq mshr miss latency
704system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency
705system.cpu.icache.demand_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency
706system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency
707system.cpu.icache.overall_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency
708system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
709system.cpu.l2cache.tags.replacements 352916 # number of replacements
710system.cpu.l2cache.tags.tagsinuse 29674.078168 # Cycle average of tags in use
711system.cpu.l2cache.tags.total_refs 3696976 # Total number of references to valid blocks.
712system.cpu.l2cache.tags.sampled_refs 385280 # Sample count of references to valid blocks.
713system.cpu.l2cache.tags.avg_refs 9.595556 # Average number of references to valid blocks.
714system.cpu.l2cache.tags.warmup_cycle 199035325000 # Cycle when the warmup percentage was hit.
715system.cpu.l2cache.tags.occ_blocks::writebacks 21118.733135 # Average occupied blocks per requestor
716system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.036414 # Average occupied blocks per requestor
717system.cpu.l2cache.tags.occ_blocks::cpu.data 8331.308620 # Average occupied blocks per requestor
718system.cpu.l2cache.tags.occ_percent::writebacks 0.644493 # Average percentage of cache occupancy
719system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006837 # Average percentage of cache occupancy
720system.cpu.l2cache.tags.occ_percent::cpu.data 0.254251 # Average percentage of cache occupancy
721system.cpu.l2cache.tags.occ_percent::total 0.905581 # Average percentage of cache occupancy
722system.cpu.l2cache.ReadReq_hits::cpu.inst 3672 # number of ReadReq hits
723system.cpu.l2cache.ReadReq_hits::cpu.data 1586607 # number of ReadReq hits
724system.cpu.l2cache.ReadReq_hits::total 1590279 # number of ReadReq hits
725system.cpu.l2cache.Writeback_hits::writebacks 2330686 # number of Writeback hits
726system.cpu.l2cache.Writeback_hits::total 2330686 # number of Writeback hits
727system.cpu.l2cache.UpgradeReq_hits::cpu.data 1446 # number of UpgradeReq hits
728system.cpu.l2cache.UpgradeReq_hits::total 1446 # number of UpgradeReq hits
729system.cpu.l2cache.ReadExReq_hits::cpu.data 564906 # number of ReadExReq hits
730system.cpu.l2cache.ReadExReq_hits::total 564906 # number of ReadExReq hits
731system.cpu.l2cache.demand_hits::cpu.inst 3672 # number of demand (read+write) hits
732system.cpu.l2cache.demand_hits::cpu.data 2151513 # number of demand (read+write) hits
733system.cpu.l2cache.demand_hits::total 2155185 # number of demand (read+write) hits
734system.cpu.l2cache.overall_hits::cpu.inst 3672 # number of overall hits
735system.cpu.l2cache.overall_hits::cpu.data 2151513 # number of overall hits
736system.cpu.l2cache.overall_hits::total 2155185 # number of overall hits
737system.cpu.l2cache.ReadReq_misses::cpu.inst 3168 # number of ReadReq misses
738system.cpu.l2cache.ReadReq_misses::cpu.data 175586 # number of ReadReq misses
739system.cpu.l2cache.ReadReq_misses::total 178754 # number of ReadReq misses
740system.cpu.l2cache.UpgradeReq_misses::cpu.data 129428 # number of UpgradeReq misses
741system.cpu.l2cache.UpgradeReq_misses::total 129428 # number of UpgradeReq misses
742system.cpu.l2cache.ReadExReq_misses::cpu.data 206870 # number of ReadExReq misses
743system.cpu.l2cache.ReadExReq_misses::total 206870 # number of ReadExReq misses
744system.cpu.l2cache.demand_misses::cpu.inst 3168 # number of demand (read+write) misses
745system.cpu.l2cache.demand_misses::cpu.data 382456 # number of demand (read+write) misses
746system.cpu.l2cache.demand_misses::total 385624 # number of demand (read+write) misses
747system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses
748system.cpu.l2cache.overall_misses::cpu.data 382456 # number of overall misses
749system.cpu.l2cache.overall_misses::total 385624 # number of overall misses
750system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245961000 # number of ReadReq miss cycles
751system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13200679958 # number of ReadReq miss cycles
752system.cpu.l2cache.ReadReq_miss_latency::total 13446640958 # number of ReadReq miss cycles
753system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6462222 # number of UpgradeReq miss cycles
754system.cpu.l2cache.UpgradeReq_miss_latency::total 6462222 # number of UpgradeReq miss cycles
755system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14256875974 # number of ReadExReq miss cycles
756system.cpu.l2cache.ReadExReq_miss_latency::total 14256875974 # number of ReadExReq miss cycles
757system.cpu.l2cache.demand_miss_latency::cpu.inst 245961000 # number of demand (read+write) miss cycles
758system.cpu.l2cache.demand_miss_latency::cpu.data 27457555932 # number of demand (read+write) miss cycles
759system.cpu.l2cache.demand_miss_latency::total 27703516932 # number of demand (read+write) miss cycles
760system.cpu.l2cache.overall_miss_latency::cpu.inst 245961000 # number of overall miss cycles
761system.cpu.l2cache.overall_miss_latency::cpu.data 27457555932 # number of overall miss cycles
762system.cpu.l2cache.overall_miss_latency::total 27703516932 # number of overall miss cycles
763system.cpu.l2cache.ReadReq_accesses::cpu.inst 6840 # number of ReadReq accesses(hits+misses)
764system.cpu.l2cache.ReadReq_accesses::cpu.data 1762193 # number of ReadReq accesses(hits+misses)
765system.cpu.l2cache.ReadReq_accesses::total 1769033 # number of ReadReq accesses(hits+misses)
766system.cpu.l2cache.Writeback_accesses::writebacks 2330686 # number of Writeback accesses(hits+misses)
767system.cpu.l2cache.Writeback_accesses::total 2330686 # number of Writeback accesses(hits+misses)
768system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130874 # number of UpgradeReq accesses(hits+misses)
769system.cpu.l2cache.UpgradeReq_accesses::total 130874 # number of UpgradeReq accesses(hits+misses)
770system.cpu.l2cache.ReadExReq_accesses::cpu.data 771776 # number of ReadExReq accesses(hits+misses)
771system.cpu.l2cache.ReadExReq_accesses::total 771776 # number of ReadExReq accesses(hits+misses)
772system.cpu.l2cache.demand_accesses::cpu.inst 6840 # number of demand (read+write) accesses
773system.cpu.l2cache.demand_accesses::cpu.data 2533969 # number of demand (read+write) accesses
774system.cpu.l2cache.demand_accesses::total 2540809 # number of demand (read+write) accesses
775system.cpu.l2cache.overall_accesses::cpu.inst 6840 # number of overall (read+write) accesses
776system.cpu.l2cache.overall_accesses::cpu.data 2533969 # number of overall (read+write) accesses
777system.cpu.l2cache.overall_accesses::total 2540809 # number of overall (read+write) accesses
778system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463158 # miss rate for ReadReq accesses
779system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099641 # miss rate for ReadReq accesses
780system.cpu.l2cache.ReadReq_miss_rate::total 0.101046 # miss rate for ReadReq accesses
781system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988951 # miss rate for UpgradeReq accesses
782system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988951 # miss rate for UpgradeReq accesses
783system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268044 # miss rate for ReadExReq accesses
784system.cpu.l2cache.ReadExReq_miss_rate::total 0.268044 # miss rate for ReadExReq accesses
785system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463158 # miss rate for demand accesses
786system.cpu.l2cache.demand_miss_rate::cpu.data 0.150932 # miss rate for demand accesses
787system.cpu.l2cache.demand_miss_rate::total 0.151772 # miss rate for demand accesses
788system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463158 # miss rate for overall accesses
789system.cpu.l2cache.overall_miss_rate::cpu.data 0.150932 # miss rate for overall accesses
790system.cpu.l2cache.overall_miss_rate::total 0.151772 # miss rate for overall accesses
791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77639.204545 # average ReadReq miss latency
792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75180.708929 # average ReadReq miss latency
793system.cpu.l2cache.ReadReq_avg_miss_latency::total 75224.280061 # average ReadReq miss latency
794system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.929088 # average UpgradeReq miss latency
795system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.929088 # average UpgradeReq miss latency
796system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68917.078233 # average ReadExReq miss latency
797system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68917.078233 # average ReadExReq miss latency
798system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency
799system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency
800system.cpu.l2cache.demand_avg_miss_latency::total 71840.748843 # average overall miss latency
801system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency
802system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency
803system.cpu.l2cache.overall_avg_miss_latency::total 71840.748843 # average overall miss latency
804system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
805system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
806system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
807system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
808system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
809system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
810system.cpu.l2cache.fast_writes 0 # number of fast writes performed
811system.cpu.l2cache.cache_copies 0 # number of cache copies performed
812system.cpu.l2cache.writebacks::writebacks 293621 # number of writebacks
813system.cpu.l2cache.writebacks::total 293621 # number of writebacks
814system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3168 # number of ReadReq MSHR misses
815system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175586 # number of ReadReq MSHR misses
816system.cpu.l2cache.ReadReq_mshr_misses::total 178754 # number of ReadReq MSHR misses
817system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 129428 # number of UpgradeReq MSHR misses
818system.cpu.l2cache.UpgradeReq_mshr_misses::total 129428 # number of UpgradeReq MSHR misses
819system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206870 # number of ReadExReq MSHR misses
820system.cpu.l2cache.ReadExReq_mshr_misses::total 206870 # number of ReadExReq MSHR misses
821system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses
822system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses
823system.cpu.l2cache.demand_mshr_misses::total 385624 # number of demand (read+write) MSHR misses
824system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses
825system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses
826system.cpu.l2cache.overall_mshr_misses::total 385624 # number of overall MSHR misses
827system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205953000 # number of ReadReq MSHR miss cycles
828system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10947318958 # number of ReadReq MSHR miss cycles
829system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11153271958 # number of ReadReq MSHR miss cycles
830system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1297954472 # number of UpgradeReq MSHR miss cycles
831system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1297954472 # number of UpgradeReq MSHR miss cycles
832system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11628367526 # number of ReadExReq MSHR miss cycles
833system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11628367526 # number of ReadExReq MSHR miss cycles
834system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205953000 # number of demand (read+write) MSHR miss cycles
835system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22575686484 # number of demand (read+write) MSHR miss cycles
836system.cpu.l2cache.demand_mshr_miss_latency::total 22781639484 # number of demand (read+write) MSHR miss cycles
837system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205953000 # number of overall MSHR miss cycles
838system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22575686484 # number of overall MSHR miss cycles
839system.cpu.l2cache.overall_mshr_miss_latency::total 22781639484 # number of overall MSHR miss cycles
840system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for ReadReq accesses
841system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099641 # mshr miss rate for ReadReq accesses
842system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101046 # mshr miss rate for ReadReq accesses
843system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988951 # mshr miss rate for UpgradeReq accesses
844system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988951 # mshr miss rate for UpgradeReq accesses
845system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268044 # mshr miss rate for ReadExReq accesses
846system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268044 # mshr miss rate for ReadExReq accesses
847system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for demand accesses
848system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for demand accesses
849system.cpu.l2cache.demand_mshr_miss_rate::total 0.151772 # mshr miss rate for demand accesses
850system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for overall accesses
851system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for overall accesses
852system.cpu.l2cache.overall_mshr_miss_rate::total 0.151772 # mshr miss rate for overall accesses
853system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65010.416667 # average ReadReq mshr miss latency
854system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62347.333831 # average ReadReq mshr miss latency
855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62394.530797 # average ReadReq mshr miss latency
856system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10028.390086 # average UpgradeReq mshr miss latency
857system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10028.390086 # average UpgradeReq mshr miss latency
858system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56210.990119 # average ReadExReq mshr miss latency
859system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56210.990119 # average ReadExReq mshr miss latency
860system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency
861system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency
862system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency
863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency
864system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency
865system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency
866system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
867system.cpu.dcache.tags.replacements 2529873 # number of replacements
868system.cpu.dcache.tags.tagsinuse 4088.353795 # Cycle average of tags in use
869system.cpu.dcache.tags.total_refs 396071280 # Total number of references to valid blocks.
870system.cpu.dcache.tags.sampled_refs 2533969 # Sample count of references to valid blocks.
871system.cpu.dcache.tags.avg_refs 156.304706 # Average number of references to valid blocks.
872system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit.
873system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353795 # Average occupied blocks per requestor
874system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy
875system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy
876system.cpu.dcache.ReadReq_hits::cpu.data 247337709 # number of ReadReq hits
877system.cpu.dcache.ReadReq_hits::total 247337709 # number of ReadReq hits
878system.cpu.dcache.WriteReq_hits::cpu.data 148240799 # number of WriteReq hits
879system.cpu.dcache.WriteReq_hits::total 148240799 # number of WriteReq hits
880system.cpu.dcache.demand_hits::cpu.data 395578508 # number of demand (read+write) hits
881system.cpu.dcache.demand_hits::total 395578508 # number of demand (read+write) hits
882system.cpu.dcache.overall_hits::cpu.data 395578508 # number of overall hits
883system.cpu.dcache.overall_hits::total 395578508 # number of overall hits
884system.cpu.dcache.ReadReq_misses::cpu.data 2867309 # number of ReadReq misses
885system.cpu.dcache.ReadReq_misses::total 2867309 # number of ReadReq misses
886system.cpu.dcache.WriteReq_misses::cpu.data 919403 # number of WriteReq misses
887system.cpu.dcache.WriteReq_misses::total 919403 # number of WriteReq misses
888system.cpu.dcache.demand_misses::cpu.data 3786712 # number of demand (read+write) misses
889system.cpu.dcache.demand_misses::total 3786712 # number of demand (read+write) misses
890system.cpu.dcache.overall_misses::cpu.data 3786712 # number of overall misses
891system.cpu.dcache.overall_misses::total 3786712 # number of overall misses
892system.cpu.dcache.ReadReq_miss_latency::cpu.data 57500595434 # number of ReadReq miss cycles
893system.cpu.dcache.ReadReq_miss_latency::total 57500595434 # number of ReadReq miss cycles
894system.cpu.dcache.WriteReq_miss_latency::cpu.data 25821603651 # number of WriteReq miss cycles
895system.cpu.dcache.WriteReq_miss_latency::total 25821603651 # number of WriteReq miss cycles
896system.cpu.dcache.demand_miss_latency::cpu.data 83322199085 # number of demand (read+write) miss cycles
897system.cpu.dcache.demand_miss_latency::total 83322199085 # number of demand (read+write) miss cycles
898system.cpu.dcache.overall_miss_latency::cpu.data 83322199085 # number of overall miss cycles
899system.cpu.dcache.overall_miss_latency::total 83322199085 # number of overall miss cycles
900system.cpu.dcache.ReadReq_accesses::cpu.data 250205018 # number of ReadReq accesses(hits+misses)
901system.cpu.dcache.ReadReq_accesses::total 250205018 # number of ReadReq accesses(hits+misses)
902system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
903system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
904system.cpu.dcache.demand_accesses::cpu.data 399365220 # number of demand (read+write) accesses
905system.cpu.dcache.demand_accesses::total 399365220 # number of demand (read+write) accesses
906system.cpu.dcache.overall_accesses::cpu.data 399365220 # number of overall (read+write) accesses
907system.cpu.dcache.overall_accesses::total 399365220 # number of overall (read+write) accesses
908system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011460 # miss rate for ReadReq accesses
909system.cpu.dcache.ReadReq_miss_rate::total 0.011460 # miss rate for ReadReq accesses
910system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006164 # miss rate for WriteReq accesses
911system.cpu.dcache.WriteReq_miss_rate::total 0.006164 # miss rate for WriteReq accesses
912system.cpu.dcache.demand_miss_rate::cpu.data 0.009482 # miss rate for demand accesses
913system.cpu.dcache.demand_miss_rate::total 0.009482 # miss rate for demand accesses
914system.cpu.dcache.overall_miss_rate::cpu.data 0.009482 # miss rate for overall accesses
915system.cpu.dcache.overall_miss_rate::total 0.009482 # miss rate for overall accesses
916system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.853782 # average ReadReq miss latency
917system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.853782 # average ReadReq miss latency
918system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28085.185333 # average WriteReq miss latency
919system.cpu.dcache.WriteReq_avg_miss_latency::total 28085.185333 # average WriteReq miss latency
920system.cpu.dcache.demand_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency
921system.cpu.dcache.demand_avg_miss_latency::total 22003.838445 # average overall miss latency
922system.cpu.dcache.overall_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency
923system.cpu.dcache.overall_avg_miss_latency::total 22003.838445 # average overall miss latency
924system.cpu.dcache.blocked_cycles::no_mshrs 7384 # number of cycles access was blocked
925system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
926system.cpu.dcache.blocked::no_mshrs 704 # number of cycles access was blocked
927system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
928system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.488636 # average number of cycles each access was blocked
929system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
930system.cpu.dcache.fast_writes 0 # number of fast writes performed
931system.cpu.dcache.cache_copies 0 # number of cache copies performed
932system.cpu.dcache.writebacks::writebacks 2330686 # number of writebacks
933system.cpu.dcache.writebacks::total 2330686 # number of writebacks
934system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1104851 # number of ReadReq MSHR hits
935system.cpu.dcache.ReadReq_mshr_hits::total 1104851 # number of ReadReq MSHR hits
936system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits
937system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits
938system.cpu.dcache.demand_mshr_hits::cpu.data 1121870 # number of demand (read+write) MSHR hits
939system.cpu.dcache.demand_mshr_hits::total 1121870 # number of demand (read+write) MSHR hits
940system.cpu.dcache.overall_mshr_hits::cpu.data 1121870 # number of overall MSHR hits
941system.cpu.dcache.overall_mshr_hits::total 1121870 # number of overall MSHR hits
942system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762458 # number of ReadReq MSHR misses
943system.cpu.dcache.ReadReq_mshr_misses::total 1762458 # number of ReadReq MSHR misses
944system.cpu.dcache.WriteReq_mshr_misses::cpu.data 902384 # number of WriteReq MSHR misses
945system.cpu.dcache.WriteReq_mshr_misses::total 902384 # number of WriteReq MSHR misses
946system.cpu.dcache.demand_mshr_misses::cpu.data 2664842 # number of demand (read+write) MSHR misses
947system.cpu.dcache.demand_mshr_misses::total 2664842 # number of demand (read+write) MSHR misses
948system.cpu.dcache.overall_mshr_misses::cpu.data 2664842 # number of overall MSHR misses
949system.cpu.dcache.overall_mshr_misses::total 2664842 # number of overall MSHR misses
950system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30865724250 # number of ReadReq MSHR miss cycles
951system.cpu.dcache.ReadReq_mshr_miss_latency::total 30865724250 # number of ReadReq MSHR miss cycles
952system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23705880099 # number of WriteReq MSHR miss cycles
953system.cpu.dcache.WriteReq_mshr_miss_latency::total 23705880099 # number of WriteReq MSHR miss cycles
954system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54571604349 # number of demand (read+write) MSHR miss cycles
955system.cpu.dcache.demand_mshr_miss_latency::total 54571604349 # number of demand (read+write) MSHR miss cycles
956system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54571604349 # number of overall MSHR miss cycles
957system.cpu.dcache.overall_mshr_miss_latency::total 54571604349 # number of overall MSHR miss cycles
958system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses
959system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses
960system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006050 # mshr miss rate for WriteReq accesses
961system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006050 # mshr miss rate for WriteReq accesses
962system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for demand accesses
963system.cpu.dcache.demand_mshr_miss_rate::total 0.006673 # mshr miss rate for demand accesses
964system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for overall accesses
965system.cpu.dcache.overall_mshr_miss_rate::total 0.006673 # mshr miss rate for overall accesses
966system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17512.884988 # average ReadReq mshr miss latency
967system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17512.884988 # average ReadReq mshr miss latency
968system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26270.279725 # average WriteReq mshr miss latency
969system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26270.279725 # average WriteReq mshr miss latency
970system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency
971system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency
972system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency
973system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency
974system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
975
976---------- End Simulation Statistics ----------