1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.458513 # Number of seconds simulated
4sim_ticks 458512999500 # Number of ticks simulated
5final_tick 458512999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 75448 # Simulator instruction rate (inst/s)
8host_op_rate 139512 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 41836736 # Simulator tick rate (ticks/s)
10host_mem_usage 384056 # Number of bytes of host memory used
11host_seconds 10959.58 # Real time elapsed on the host
12sim_insts 826877109 # Number of instructions simulated
13sim_ops 1528988701 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 201856 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24474368 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24676224 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 201856 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 201856 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 18792384 # Number of bytes written to this memory
22system.physmem.bytes_written::total 18792384 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 3154 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 382412 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 385566 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 293631 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 293631 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 440241 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 53377697 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 53817938 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 440241 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 440241 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 40985499 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 40985499 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 40985499 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 440241 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 53377697 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 94803436 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 385568 # Number of read requests accepted
40system.physmem.writeReqs 293631 # Number of write requests accepted
41system.physmem.readBursts 385568 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 293631 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 24654400 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue
45system.physmem.bytesWritten 18790528 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 24676352 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 18792384 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 136756 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 24002 # Per bank write bursts
52system.physmem.perBankRdBursts::1 26346 # Per bank write bursts
53system.physmem.perBankRdBursts::2 24809 # Per bank write bursts
54system.physmem.perBankRdBursts::3 24514 # Per bank write bursts
55system.physmem.perBankRdBursts::4 23427 # Per bank write bursts
56system.physmem.perBankRdBursts::5 23679 # Per bank write bursts
57system.physmem.perBankRdBursts::6 24437 # Per bank write bursts
58system.physmem.perBankRdBursts::7 24240 # Per bank write bursts
59system.physmem.perBankRdBursts::8 23642 # Per bank write bursts
60system.physmem.perBankRdBursts::9 23833 # Per bank write bursts
61system.physmem.perBankRdBursts::10 24803 # Per bank write bursts
62system.physmem.perBankRdBursts::11 23968 # Per bank write bursts
63system.physmem.perBankRdBursts::12 23115 # Per bank write bursts
64system.physmem.perBankRdBursts::13 22838 # Per bank write bursts
65system.physmem.perBankRdBursts::14 23649 # Per bank write bursts
66system.physmem.perBankRdBursts::15 23923 # Per bank write bursts
67system.physmem.perBankWrBursts::0 18533 # Per bank write bursts
68system.physmem.perBankWrBursts::1 19811 # Per bank write bursts
69system.physmem.perBankWrBursts::2 18961 # Per bank write bursts
70system.physmem.perBankWrBursts::3 18917 # Per bank write bursts
71system.physmem.perBankWrBursts::4 18087 # Per bank write bursts
72system.physmem.perBankWrBursts::5 18414 # Per bank write bursts
73system.physmem.perBankWrBursts::6 18972 # Per bank write bursts
74system.physmem.perBankWrBursts::7 18944 # Per bank write bursts
75system.physmem.perBankWrBursts::8 18562 # Per bank write bursts
76system.physmem.perBankWrBursts::9 18116 # Per bank write bursts
77system.physmem.perBankWrBursts::10 18832 # Per bank write bursts
78system.physmem.perBankWrBursts::11 17714 # Per bank write bursts
79system.physmem.perBankWrBursts::12 17339 # Per bank write bursts
80system.physmem.perBankWrBursts::13 16924 # Per bank write bursts
81system.physmem.perBankWrBursts::14 17682 # Per bank write bursts
82system.physmem.perBankWrBursts::15 17794 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 458512983000 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 385568 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 293631 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 380696 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 4209 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see

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139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 6409 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 6808 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 16841 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 17378 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 17536 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 17527 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 17556 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 17556 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 17549 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 17549 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 17561 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 17726 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 17619 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 17583 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 17768 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 17495 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 17431 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 9 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 7 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 9 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 8 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 8 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 6 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 146743 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 296.052173 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 174.726027 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 323.657452 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 54056 36.84% 36.84% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 40668 27.71% 64.55% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 13398 9.13% 73.68% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 7234 4.93% 78.61% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 5377 3.66% 82.28% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 3862 2.63% 84.91% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 3026 2.06% 86.97% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 2779 1.89% 88.86% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 16343 11.14% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 146743 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 17400 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 22.138621 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 209.351810 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 17386 99.92% 99.92% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::total 17400 # Reads before turning the bus around for writes
219system.physmem.wrPerTurnAround::samples 17400 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::mean 16.873678 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::gmean 16.805032 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::stdev 2.403017 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::16-19 17211 98.91% 98.91% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::20-23 144 0.83% 99.74% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::24-27 22 0.13% 99.87% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::28-31 3 0.02% 99.89% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::40-43 2 0.01% 99.92% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::52-55 2 0.01% 99.94% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::84-87 2 0.01% 99.98% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::108-111 2 0.01% 99.99% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::total 17400 # Writes before turning the bus around for reads
241system.physmem.totQLat 4188887000 # Total ticks spent queuing
242system.physmem.totMemAccLat 11411855750 # Total ticks spent from burst creation until serviced by the DRAM
243system.physmem.totBusLat 1926125000 # Total ticks spent in databus transfers
244system.physmem.avgQLat 10873.87 # Average queueing delay per DRAM burst
245system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
246system.physmem.avgMemAccLat 29623.87 # Average memory access latency per DRAM burst
247system.physmem.avgRdBW 53.77 # Average DRAM read bandwidth in MiByte/s
248system.physmem.avgWrBW 40.98 # Average achieved write bandwidth in MiByte/s
249system.physmem.avgRdBWSys 53.82 # Average system read bandwidth in MiByte/s
250system.physmem.avgWrBWSys 40.99 # Average system write bandwidth in MiByte/s
251system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
252system.physmem.busUtil 0.74 # Data bus utilization in percentage
253system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
254system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
255system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
256system.physmem.avgWrQLen 21.82 # Average write queue length when enqueuing
257system.physmem.readRowHits 316892 # Number of row buffer hits during reads
258system.physmem.writeRowHits 215180 # Number of row buffer hits during writes
259system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads
260system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes
261system.physmem.avgGap 675079.00 # Average gap between requests
262system.physmem.pageHitRate 78.38 # Row buffer hit rate, read and write combined
263system.physmem.memoryStateTime::IDLE 318092069500 # Time in different power states
264system.physmem.memoryStateTime::REF 15310620000 # Time in different power states
265system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
266system.physmem.memoryStateTime::ACT 125106520750 # Time in different power states
267system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
268system.membus.throughput 94803436 # Throughput (bytes/s)
269system.membus.trans_dist::ReadReq 178732 # Transaction distribution
270system.membus.trans_dist::ReadResp 178730 # Transaction distribution
271system.membus.trans_dist::Writeback 293631 # Transaction distribution
272system.membus.trans_dist::UpgradeReq 136756 # Transaction distribution
273system.membus.trans_dist::UpgradeResp 136756 # Transaction distribution
274system.membus.trans_dist::ReadExReq 206836 # Transaction distribution
275system.membus.trans_dist::ReadExResp 206836 # Transaction distribution
276system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1338277 # Packet count per connected master and slave (bytes)
277system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1338277 # Packet count per connected master and slave (bytes)
278system.membus.pkt_count::total 1338277 # Packet count per connected master and slave (bytes)
279system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43468608 # Cumulative packet size per connected master and slave (bytes)
280system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43468608 # Cumulative packet size per connected master and slave (bytes)
281system.membus.tot_pkt_size::total 43468608 # Cumulative packet size per connected master and slave (bytes)
282system.membus.data_through_bus 43468608 # Total data (bytes)
283system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
284system.membus.reqLayer0.occupancy 3392871500 # Layer occupancy (ticks)
285system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
286system.membus.respLayer1.occupancy 3899245261 # Layer occupancy (ticks)
287system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
288system.cpu_clk_domain.clock 500 # Clock period in ticks
289system.cpu.branchPred.lookups 205578466 # Number of BP lookups
290system.cpu.branchPred.condPredicted 205578466 # Number of conditional branches predicted
291system.cpu.branchPred.condIncorrect 9901534 # Number of conditional branches incorrect
292system.cpu.branchPred.BTBLookups 117029392 # Number of BTB lookups
293system.cpu.branchPred.BTBHits 114680074 # Number of BTB hits
294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
295system.cpu.branchPred.BTBHitPct 97.992540 # BTB Hit Percentage
296system.cpu.branchPred.usedRAS 25067972 # Number of times the RAS was used to get a target.
297system.cpu.branchPred.RASInCorrect 1805738 # Number of incorrect RAS predictions.
298system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
299system.cpu.workload.num_syscalls 551 # Number of system calls
300system.cpu.numCycles 917184655 # number of cpu cycles simulated
301system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
302system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
303system.cpu.fetch.icacheStallCycles 167397549 # Number of cycles fetch is stalled on an Icache miss
304system.cpu.fetch.Insts 1131555944 # Number of instructions fetch has processed
305system.cpu.fetch.Branches 205578466 # Number of branches that fetch encountered
306system.cpu.fetch.predictedBranches 139748046 # Number of branches that fetch has predicted taken
307system.cpu.fetch.Cycles 352223186 # Number of cycles fetch has run and was not squashing or blocked
308system.cpu.fetch.SquashCycles 71069558 # Number of cycles fetch has spent squashing
309system.cpu.fetch.BlockedCycles 304555909 # Number of cycles fetch has spent blocked
310system.cpu.fetch.MiscStallCycles 47998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
311system.cpu.fetch.PendingTrapStallCycles 253720 # Number of stall cycles due to pending traps
312system.cpu.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR
313system.cpu.fetch.CacheLines 161997167 # Number of cache lines fetched
314system.cpu.fetch.IcacheSquashes 2518791 # Number of outstanding Icache misses that were squashed
315system.cpu.fetch.rateDist::samples 885395126 # Number of instructions fetched each cycle (Total)
316system.cpu.fetch.rateDist::mean 2.377906 # Number of instructions fetched each cycle (Total)
317system.cpu.fetch.rateDist::stdev 3.324319 # Number of instructions fetched each cycle (Total)
318system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
319system.cpu.fetch.rateDist::0 537236750 60.68% 60.68% # Number of instructions fetched each cycle (Total)
320system.cpu.fetch.rateDist::1 23398648 2.64% 63.32% # Number of instructions fetched each cycle (Total)
321system.cpu.fetch.rateDist::2 25254202 2.85% 66.17% # Number of instructions fetched each cycle (Total)
322system.cpu.fetch.rateDist::3 27875613 3.15% 69.32% # Number of instructions fetched each cycle (Total)
323system.cpu.fetch.rateDist::4 17735392 2.00% 71.32% # Number of instructions fetched each cycle (Total)
324system.cpu.fetch.rateDist::5 22920767 2.59% 73.91% # Number of instructions fetched each cycle (Total)
325system.cpu.fetch.rateDist::6 29423422 3.32% 77.24% # Number of instructions fetched each cycle (Total)
326system.cpu.fetch.rateDist::7 26636426 3.01% 80.24% # Number of instructions fetched each cycle (Total)
327system.cpu.fetch.rateDist::8 174913906 19.76% 100.00% # Number of instructions fetched each cycle (Total)
328system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::total 885395126 # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.branchRate 0.224141 # Number of branch fetches per cycle
333system.cpu.fetch.rate 1.233728 # Number of inst fetches per cycle
334system.cpu.decode.IdleCycles 222654978 # Number of cycles decode is idle
335system.cpu.decode.BlockedCycles 259567656 # Number of cycles decode is blocked
336system.cpu.decode.RunCycles 295344640 # Number of cycles decode is running
337system.cpu.decode.UnblockCycles 46911146 # Number of cycles decode is unblocking
338system.cpu.decode.SquashCycles 60916706 # Number of cycles decode is squashing
339system.cpu.decode.DecodedInsts 2071122559 # Number of instructions handled by decode
340system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode
341system.cpu.rename.SquashCycles 60916706 # Number of cycles rename is squashing
342system.cpu.rename.IdleCycles 256101136 # Number of cycles rename is idle
343system.cpu.rename.BlockCycles 115302026 # Number of cycles rename is blocking
344system.cpu.rename.serializeStallCycles 17668 # count of cycles rename stalled for serializing inst
345system.cpu.rename.RunCycles 306678759 # Number of cycles rename is running
346system.cpu.rename.UnblockCycles 146378831 # Number of cycles rename is unblocking
347system.cpu.rename.RenamedInsts 2034998452 # Number of instructions processed by rename
348system.cpu.rename.ROBFullEvents 20313 # Number of times rename has blocked due to ROB full
349system.cpu.rename.IQFullEvents 24722090 # Number of times rename has blocked due to IQ full
350system.cpu.rename.LSQFullEvents 106340501 # Number of times rename has blocked due to LSQ full
351system.cpu.rename.RenamedOperands 2137925960 # Number of destination operands rename has renamed
352system.cpu.rename.RenameLookups 5150186774 # Number of register rename lookups that rename has made
353system.cpu.rename.int_rename_lookups 3273147321 # Number of integer rename lookups
354system.cpu.rename.fp_rename_lookups 41991 # Number of floating rename lookups
355system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
356system.cpu.rename.UndoneMaps 523885106 # Number of HB maps that are undone due to squashing
357system.cpu.rename.serializingInsts 1288 # count of serializing insts renamed
358system.cpu.rename.tempSerializingInsts 1219 # count of temporary serializing insts renamed
359system.cpu.rename.skidInsts 345625652 # count of insts added to the skid buffer
360system.cpu.memDep0.insertedLoads 495840221 # Number of loads inserted to the mem dependence unit.
361system.cpu.memDep0.insertedStores 194409464 # Number of stores inserted to the mem dependence unit.
362system.cpu.memDep0.conflictingLoads 195351813 # Number of conflicting loads.
363system.cpu.memDep0.conflictingStores 54649414 # Number of conflicting stores.
364system.cpu.iq.iqInstsAdded 1975275020 # Number of instructions added to the IQ (excludes non-spec)
365system.cpu.iq.iqNonSpecInstsAdded 13975 # Number of non-speculative instructions added to the IQ
366system.cpu.iq.iqInstsIssued 1772033700 # Number of instructions issued
367system.cpu.iq.iqSquashedInstsIssued 489443 # Number of squashed instructions issued
368system.cpu.iq.iqSquashedInstsExamined 441377933 # Number of squashed instructions iterated over during squash; mainly for profiling
369system.cpu.iq.iqSquashedOperandsExamined 734704744 # Number of squashed operands that are examined and possibly removed from graph
370system.cpu.iq.iqSquashedNonSpecRemoved 13423 # Number of squashed non-spec instructions that were removed
371system.cpu.iq.issued_per_cycle::samples 885395126 # Number of insts issued each cycle
372system.cpu.iq.issued_per_cycle::mean 2.001404 # Number of insts issued each cycle
373system.cpu.iq.issued_per_cycle::stdev 1.883479 # Number of insts issued each cycle
374system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
375system.cpu.iq.issued_per_cycle::0 268930520 30.37% 30.37% # Number of insts issued each cycle
376system.cpu.iq.issued_per_cycle::1 151513258 17.11% 47.49% # Number of insts issued each cycle
377system.cpu.iq.issued_per_cycle::2 137639902 15.55% 63.03% # Number of insts issued each cycle
378system.cpu.iq.issued_per_cycle::3 131544541 14.86% 77.89% # Number of insts issued each cycle
379system.cpu.iq.issued_per_cycle::4 91741507 10.36% 88.25% # Number of insts issued each cycle
380system.cpu.iq.issued_per_cycle::5 55934371 6.32% 94.57% # Number of insts issued each cycle
381system.cpu.iq.issued_per_cycle::6 34425935 3.89% 98.46% # Number of insts issued each cycle
382system.cpu.iq.issued_per_cycle::7 11907214 1.34% 99.80% # Number of insts issued each cycle
383system.cpu.iq.issued_per_cycle::8 1757878 0.20% 100.00% # Number of insts issued each cycle
384system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
385system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
386system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
387system.cpu.iq.issued_per_cycle::total 885395126 # Number of insts issued each cycle
388system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
389system.cpu.iq.fu_full::IntAlu 4908226 32.44% 32.44% # attempts to use FU when none available
390system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available
391system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available
392system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available
393system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available
394system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available
395system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available
396system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available
397system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
398system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available
399system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available
400system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available
401system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available
402system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available
403system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available
404system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available
405system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available
406system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available
407system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available
408system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available
409system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available
410system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available
411system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available
412system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available
413system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available
414system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available
415system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available
416system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available
417system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
418system.cpu.iq.fu_full::MemRead 7617033 50.35% 82.79% # attempts to use FU when none available
419system.cpu.iq.fu_full::MemWrite 2603803 17.21% 100.00% # attempts to use FU when none available
420system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
421system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
422system.cpu.iq.FU_type_0::No_OpClass 2622809 0.15% 0.15% # Type of FU issued
423system.cpu.iq.FU_type_0::IntAlu 1165654727 65.78% 65.93% # Type of FU issued
424system.cpu.iq.FU_type_0::IntMult 353604 0.02% 65.95% # Type of FU issued
425system.cpu.iq.FU_type_0::IntDiv 3880790 0.22% 66.17% # Type of FU issued
426system.cpu.iq.FU_type_0::FloatAdd 51 0.00% 66.17% # Type of FU issued
427system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
428system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
429system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
430system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
431system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
434system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued

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444system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
445system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
446system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
447system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
448system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
449system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
450system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
451system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
452system.cpu.iq.FU_type_0::MemRead 429257765 24.22% 90.39% # Type of FU issued
453system.cpu.iq.FU_type_0::MemWrite 170263954 9.61% 100.00% # Type of FU issued
454system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
455system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
456system.cpu.iq.FU_type_0::total 1772033700 # Type of FU issued
457system.cpu.iq.rate 1.932036 # Inst issue rate
458system.cpu.iq.fu_busy_cnt 15129062 # FU busy when requested
459system.cpu.iq.fu_busy_rate 0.008538 # FU busy rate (busy events/executed inst)
460system.cpu.iq.int_inst_queue_reads 4445065609 # Number of integer instruction queue reads
461system.cpu.iq.int_inst_queue_writes 2416869316 # Number of integer instruction queue writes
462system.cpu.iq.int_inst_queue_wakeup_accesses 1744809668 # Number of integer instruction queue wakeup accesses
463system.cpu.iq.fp_inst_queue_reads 15422 # Number of floating instruction queue reads
464system.cpu.iq.fp_inst_queue_writes 52952 # Number of floating instruction queue writes
465system.cpu.iq.fp_inst_queue_wakeup_accesses 3677 # Number of floating instruction queue wakeup accesses
466system.cpu.iq.int_alu_accesses 1784532643 # Number of integer alu accesses
467system.cpu.iq.fp_alu_accesses 7310 # Number of floating point alu accesses
468system.cpu.iew.lsq.thread0.forwLoads 172476568 # Number of loads that had data forwarded from stores
469system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
470system.cpu.iew.lsq.thread0.squashedLoads 111739174 # Number of loads squashed
471system.cpu.iew.lsq.thread0.ignoredResponses 389536 # Number of memory responses ignored because the instruction is squashed
472system.cpu.iew.lsq.thread0.memOrderViolation 327115 # Number of memory ordering violations
473system.cpu.iew.lsq.thread0.squashedStores 45249278 # Number of stores squashed
474system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
475system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
476system.cpu.iew.lsq.thread0.rescheduledLoads 14923 # Number of loads that were rescheduled
477system.cpu.iew.lsq.thread0.cacheBlocked 606 # Number of times an access to memory failed due to the cache being blocked
478system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
479system.cpu.iew.iewSquashCycles 60916706 # Number of cycles IEW is squashing
480system.cpu.iew.iewBlockCycles 67511680 # Number of cycles IEW is blocking
481system.cpu.iew.iewUnblockCycles 7160873 # Number of cycles IEW is unblocking
482system.cpu.iew.iewDispatchedInsts 1975288995 # Number of instructions dispatched to IQ
483system.cpu.iew.iewDispSquashedInsts 782662 # Number of squashed instructions skipped by dispatch
484system.cpu.iew.iewDispLoadInsts 495841331 # Number of dispatched load instructions
485system.cpu.iew.iewDispStoreInsts 194409464 # Number of dispatched store instructions
486system.cpu.iew.iewDispNonSpecInsts 3475 # Number of dispatched non-speculative instructions
487system.cpu.iew.iewIQFullEvents 4447984 # Number of times the IQ has become full, causing a stall
488system.cpu.iew.iewLSQFullEvents 83109 # Number of times the LSQ has become full, causing a stall
489system.cpu.iew.memOrderViolationEvents 327115 # Number of memory order violations
490system.cpu.iew.predictedTakenIncorrect 5905027 # Number of branches that were predicted taken incorrectly
491system.cpu.iew.predictedNotTakenIncorrect 4421064 # Number of branches that were predicted not taken incorrectly
492system.cpu.iew.branchMispredicts 10326091 # Number of branch mispredicts detected at execute
493system.cpu.iew.iewExecutedInsts 1752917365 # Number of executed instructions
494system.cpu.iew.iewExecLoadInsts 424127416 # Number of load instructions executed
495system.cpu.iew.iewExecSquashedInsts 19116335 # Number of squashed instructions skipped in execute
496system.cpu.iew.exec_swp 0 # number of swp insts executed
497system.cpu.iew.exec_nop 0 # number of nop insts executed
498system.cpu.iew.exec_refs 590948442 # number of memory reference insts executed
499system.cpu.iew.exec_branches 167460417 # Number of branches executed
500system.cpu.iew.exec_stores 166821026 # Number of stores executed
501system.cpu.iew.exec_rate 1.911194 # Inst execution rate
502system.cpu.iew.wb_sent 1749660983 # cumulative count of insts sent to commit
503system.cpu.iew.wb_count 1744813345 # cumulative count of insts written-back
504system.cpu.iew.wb_producers 1324821434 # num instructions producing a value
505system.cpu.iew.wb_consumers 1945562364 # num instructions consuming a value
506system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
507system.cpu.iew.wb_rate 1.902358 # insts written-back per cycle
508system.cpu.iew.wb_fanout 0.680945 # average fanout of values written-back
509system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
510system.cpu.commit.commitSquashedInsts 446329306 # The number of squashed insts skipped by commit
511system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
512system.cpu.commit.branchMispredicts 9930052 # The number of times a branch was mispredicted
513system.cpu.commit.committed_per_cycle::samples 824478420 # Number of insts commited each cycle
514system.cpu.commit.committed_per_cycle::mean 1.854492 # Number of insts commited each cycle
515system.cpu.commit.committed_per_cycle::stdev 2.436428 # Number of insts commited each cycle
516system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
517system.cpu.commit.committed_per_cycle::0 332514113 40.33% 40.33% # Number of insts commited each cycle
518system.cpu.commit.committed_per_cycle::1 193200456 23.43% 63.76% # Number of insts commited each cycle
519system.cpu.commit.committed_per_cycle::2 63249703 7.67% 71.43% # Number of insts commited each cycle
520system.cpu.commit.committed_per_cycle::3 92516022 11.22% 82.66% # Number of insts commited each cycle
521system.cpu.commit.committed_per_cycle::4 24944995 3.03% 85.68% # Number of insts commited each cycle
522system.cpu.commit.committed_per_cycle::5 27441019 3.33% 89.01% # Number of insts commited each cycle
523system.cpu.commit.committed_per_cycle::6 9353308 1.13% 90.14% # Number of insts commited each cycle
524system.cpu.commit.committed_per_cycle::7 11434582 1.39% 91.53% # Number of insts commited each cycle
525system.cpu.commit.committed_per_cycle::8 69824222 8.47% 100.00% # Number of insts commited each cycle
526system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
527system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
528system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
529system.cpu.commit.committed_per_cycle::total 824478420 # Number of insts commited each cycle
530system.cpu.commit.committedInsts 826877109 # Number of instructions committed
531system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
532system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
533system.cpu.commit.refs 533262343 # Number of memory references committed
534system.cpu.commit.loads 384102157 # Number of loads committed
535system.cpu.commit.membars 0 # Number of memory barriers committed
536system.cpu.commit.branches 149758583 # Number of branches committed
537system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
538system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
539system.cpu.commit.function_calls 17673145 # Number of function calls committed.
540system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
541system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
542system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
543system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
544system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
545system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
546system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
547system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
548system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
549system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
550system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
551system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
552system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
553system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
554system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
555system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
556system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
557system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
558system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
559system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
560system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
561system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
562system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
563system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
564system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
565system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
566system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
567system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
568system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
569system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
570system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
571system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
572system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
573system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
574system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
575system.cpu.commit.bw_lim_events 69824222 # number cycles where commit BW limit reached
576system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
577system.cpu.rob.rob_reads 2729972205 # The number of ROB reads
578system.cpu.rob.rob_writes 4011712950 # The number of ROB writes
579system.cpu.timesIdled 3360559 # Number of times that the entire CPU went into an idle state and unscheduled itself
580system.cpu.idleCycles 31789529 # Total number of cycles that the CPU has spent unscheduled due to idling
581system.cpu.committedInsts 826877109 # Number of Instructions Simulated
582system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
583system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
584system.cpu.cpi 1.109215 # CPI: Cycles Per Instruction
585system.cpu.cpi_total 1.109215 # CPI: Total CPI of All Threads
586system.cpu.ipc 0.901538 # IPC: Instructions Per Cycle
587system.cpu.ipc_total 0.901538 # IPC: Total IPC of All Threads
588system.cpu.int_regfile_reads 2716307472 # number of integer regfile reads
589system.cpu.int_regfile_writes 1420359444 # number of integer regfile writes
590system.cpu.fp_regfile_reads 3689 # number of floating regfile reads
591system.cpu.fp_regfile_writes 68 # number of floating regfile writes
592system.cpu.cc_regfile_reads 597203936 # number of cc regfile reads
593system.cpu.cc_regfile_writes 405421760 # number of cc regfile writes
594system.cpu.misc_regfile_reads 964666021 # number of misc regfile reads
595system.cpu.misc_regfile_writes 1 # number of misc regfile writes
596system.cpu.toL2Bus.throughput 699262879 # Throughput (bytes/s)
597system.cpu.toL2Bus.trans_dist::ReadReq 1907311 # Transaction distribution
598system.cpu.toL2Bus.trans_dist::ReadResp 1907308 # Transaction distribution
599system.cpu.toL2Bus.trans_dist::Writeback 2330645 # Transaction distribution
600system.cpu.toL2Bus.trans_dist::UpgradeReq 138184 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::UpgradeResp 138184 # Transaction distribution
602system.cpu.toL2Bus.trans_dist::ReadExReq 771752 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::ReadExResp 771752 # Transaction distribution
604system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 151977 # Packet count per connected master and slave (bytes)
605system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7674879 # Packet count per connected master and slave (bytes)
606system.cpu.toL2Bus.pkt_count::total 7826856 # Packet count per connected master and slave (bytes)
607system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 438272 # Cumulative packet size per connected master and slave (bytes)
608system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311332928 # Cumulative packet size per connected master and slave (bytes)
609system.cpu.toL2Bus.tot_pkt_size::total 311771200 # Cumulative packet size per connected master and slave (bytes)
610system.cpu.toL2Bus.data_through_bus 311771200 # Total data (bytes)
611system.cpu.toL2Bus.snoop_data_through_bus 8849920 # Total snoop data (bytes)
612system.cpu.toL2Bus.reqLayer0.occupancy 4908820525 # Layer occupancy (ticks)
613system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
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615system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
616system.cpu.toL2Bus.respLayer1.occupancy 3952575691 # Layer occupancy (ticks)
617system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
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628system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
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630system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
631system.cpu.icache.tags.age_task_id_blocks_1024::3 250 # Occupied blocks per task id
632system.cpu.icache.tags.age_task_id_blocks_1024::4 1221 # Occupied blocks per task id
633system.cpu.icache.tags.occ_task_id_percent::1024 0.770996 # Percentage of cache occupancy per task id
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637system.cpu.icache.ReadReq_hits::total 161850058 # number of ReadReq hits
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643system.cpu.icache.ReadReq_misses::total 147109 # number of ReadReq misses
644system.cpu.icache.demand_misses::cpu.inst 147109 # number of demand (read+write) misses
645system.cpu.icache.demand_misses::total 147109 # number of demand (read+write) misses
646system.cpu.icache.overall_misses::cpu.inst 147109 # number of overall misses
647system.cpu.icache.overall_misses::total 147109 # number of overall misses
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665system.cpu.icache.overall_miss_rate::total 0.000908 # miss rate for overall accesses
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670system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency
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683system.cpu.icache.demand_mshr_hits::total 1980 # number of demand (read+write) MSHR hits
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687system.cpu.icache.ReadReq_mshr_misses::total 145129 # number of ReadReq MSHR misses
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702system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for overall accesses
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705system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.430617 # average ReadReq mshr miss latency
706system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency
707system.cpu.icache.demand_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency
708system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency
709system.cpu.icache.overall_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency
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725system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
726system.cpu.l2cache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id
727system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11715 # Occupied blocks per task id
728system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20331 # Occupied blocks per task id
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736system.cpu.l2cache.Writeback_hits::total 2330645 # number of Writeback hits
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862system.cpu.l2cache.overall_mshr_miss_rate::total 0.151761 # mshr miss rate for overall accesses
863system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61744.453249 # average ReadReq mshr miss latency
864system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60418.236943 # average ReadReq mshr miss latency
865system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60441.647351 # average ReadReq mshr miss latency
866system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.296079 # average UpgradeReq mshr miss latency
867system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.296079 # average UpgradeReq mshr miss latency
868system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58957.920516 # average ReadExReq mshr miss latency
869system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58957.920516 # average ReadExReq mshr miss latency
870system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency
871system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency
872system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency
873system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency
874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency
875system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency
876system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
877system.cpu.dcache.tags.replacements 2529836 # number of replacements
878system.cpu.dcache.tags.tagsinuse 4088.247019 # Cycle average of tags in use
879system.cpu.dcache.tags.total_refs 396128893 # Total number of references to valid blocks.
880system.cpu.dcache.tags.sampled_refs 2533932 # Sample count of references to valid blocks.
881system.cpu.dcache.tags.avg_refs 156.329725 # Average number of references to valid blocks.
882system.cpu.dcache.tags.warmup_cycle 1791176250 # Cycle when the warmup percentage was hit.
883system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247019 # Average occupied blocks per requestor
884system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy
885system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy
886system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
887system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
888system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
889system.cpu.dcache.tags.age_task_id_blocks_1024::2 741 # Occupied blocks per task id
890system.cpu.dcache.tags.age_task_id_blocks_1024::3 3311 # Occupied blocks per task id
891system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
892system.cpu.dcache.tags.tag_accesses 801380064 # Number of tag accesses
893system.cpu.dcache.tags.data_accesses 801380064 # Number of data accesses
894system.cpu.dcache.ReadReq_hits::cpu.data 247376910 # number of ReadReq hits
895system.cpu.dcache.ReadReq_hits::total 247376910 # number of ReadReq hits
896system.cpu.dcache.WriteReq_hits::cpu.data 148233547 # number of WriteReq hits
897system.cpu.dcache.WriteReq_hits::total 148233547 # number of WriteReq hits
898system.cpu.dcache.demand_hits::cpu.data 395610457 # number of demand (read+write) hits
899system.cpu.dcache.demand_hits::total 395610457 # number of demand (read+write) hits
900system.cpu.dcache.overall_hits::cpu.data 395610457 # number of overall hits
901system.cpu.dcache.overall_hits::total 395610457 # number of overall hits
902system.cpu.dcache.ReadReq_misses::cpu.data 2885954 # number of ReadReq misses
903system.cpu.dcache.ReadReq_misses::total 2885954 # number of ReadReq misses
904system.cpu.dcache.WriteReq_misses::cpu.data 926655 # number of WriteReq misses
905system.cpu.dcache.WriteReq_misses::total 926655 # number of WriteReq misses
906system.cpu.dcache.demand_misses::cpu.data 3812609 # number of demand (read+write) misses
907system.cpu.dcache.demand_misses::total 3812609 # number of demand (read+write) misses
908system.cpu.dcache.overall_misses::cpu.data 3812609 # number of overall misses
909system.cpu.dcache.overall_misses::total 3812609 # number of overall misses
910system.cpu.dcache.ReadReq_miss_latency::cpu.data 57615846746 # number of ReadReq miss cycles
911system.cpu.dcache.ReadReq_miss_latency::total 57615846746 # number of ReadReq miss cycles
912system.cpu.dcache.WriteReq_miss_latency::cpu.data 26561972442 # number of WriteReq miss cycles
913system.cpu.dcache.WriteReq_miss_latency::total 26561972442 # number of WriteReq miss cycles
914system.cpu.dcache.demand_miss_latency::cpu.data 84177819188 # number of demand (read+write) miss cycles
915system.cpu.dcache.demand_miss_latency::total 84177819188 # number of demand (read+write) miss cycles
916system.cpu.dcache.overall_miss_latency::cpu.data 84177819188 # number of overall miss cycles
917system.cpu.dcache.overall_miss_latency::total 84177819188 # number of overall miss cycles
918system.cpu.dcache.ReadReq_accesses::cpu.data 250262864 # number of ReadReq accesses(hits+misses)
919system.cpu.dcache.ReadReq_accesses::total 250262864 # number of ReadReq accesses(hits+misses)
920system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
921system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
922system.cpu.dcache.demand_accesses::cpu.data 399423066 # number of demand (read+write) accesses
923system.cpu.dcache.demand_accesses::total 399423066 # number of demand (read+write) accesses
924system.cpu.dcache.overall_accesses::cpu.data 399423066 # number of overall (read+write) accesses
925system.cpu.dcache.overall_accesses::total 399423066 # number of overall (read+write) accesses
926system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011532 # miss rate for ReadReq accesses
927system.cpu.dcache.ReadReq_miss_rate::total 0.011532 # miss rate for ReadReq accesses
928system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006212 # miss rate for WriteReq accesses
929system.cpu.dcache.WriteReq_miss_rate::total 0.006212 # miss rate for WriteReq accesses
930system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses
931system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses
932system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses
933system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses
934system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19964.229072 # average ReadReq miss latency
935system.cpu.dcache.ReadReq_avg_miss_latency::total 19964.229072 # average ReadReq miss latency
936system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28664.359920 # average WriteReq miss latency
937system.cpu.dcache.WriteReq_avg_miss_latency::total 28664.359920 # average WriteReq miss latency
938system.cpu.dcache.demand_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency
939system.cpu.dcache.demand_avg_miss_latency::total 22078.796747 # average overall miss latency
940system.cpu.dcache.overall_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency
941system.cpu.dcache.overall_avg_miss_latency::total 22078.796747 # average overall miss latency
942system.cpu.dcache.blocked_cycles::no_mshrs 6778 # number of cycles access was blocked
943system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
944system.cpu.dcache.blocked::no_mshrs 684 # number of cycles access was blocked
945system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
946system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.909357 # average number of cycles each access was blocked
947system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
948system.cpu.dcache.fast_writes 0 # number of fast writes performed
949system.cpu.dcache.cache_copies 0 # number of cache copies performed
950system.cpu.dcache.writebacks::writebacks 2330645 # number of writebacks
951system.cpu.dcache.writebacks::total 2330645 # number of writebacks
952system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123517 # number of ReadReq MSHR hits
953system.cpu.dcache.ReadReq_mshr_hits::total 1123517 # number of ReadReq MSHR hits
954system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16974 # number of WriteReq MSHR hits
955system.cpu.dcache.WriteReq_mshr_hits::total 16974 # number of WriteReq MSHR hits
956system.cpu.dcache.demand_mshr_hits::cpu.data 1140491 # number of demand (read+write) MSHR hits
957system.cpu.dcache.demand_mshr_hits::total 1140491 # number of demand (read+write) MSHR hits
958system.cpu.dcache.overall_mshr_hits::cpu.data 1140491 # number of overall MSHR hits
959system.cpu.dcache.overall_mshr_hits::total 1140491 # number of overall MSHR hits
960system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762437 # number of ReadReq MSHR misses
961system.cpu.dcache.ReadReq_mshr_misses::total 1762437 # number of ReadReq MSHR misses
962system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909681 # number of WriteReq MSHR misses
963system.cpu.dcache.WriteReq_mshr_misses::total 909681 # number of WriteReq MSHR misses
964system.cpu.dcache.demand_mshr_misses::cpu.data 2672118 # number of demand (read+write) MSHR misses
965system.cpu.dcache.demand_mshr_misses::total 2672118 # number of demand (read+write) MSHR misses
966system.cpu.dcache.overall_mshr_misses::cpu.data 2672118 # number of overall MSHR misses
967system.cpu.dcache.overall_mshr_misses::total 2672118 # number of overall MSHR misses
968system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30508505001 # number of ReadReq MSHR miss cycles
969system.cpu.dcache.ReadReq_mshr_miss_latency::total 30508505001 # number of ReadReq MSHR miss cycles
970system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24438286308 # number of WriteReq MSHR miss cycles
971system.cpu.dcache.WriteReq_mshr_miss_latency::total 24438286308 # number of WriteReq MSHR miss cycles
972system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54946791309 # number of demand (read+write) MSHR miss cycles
973system.cpu.dcache.demand_mshr_miss_latency::total 54946791309 # number of demand (read+write) MSHR miss cycles
974system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54946791309 # number of overall MSHR miss cycles
975system.cpu.dcache.overall_mshr_miss_latency::total 54946791309 # number of overall MSHR miss cycles
976system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007042 # mshr miss rate for ReadReq accesses
977system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007042 # mshr miss rate for ReadReq accesses
978system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses
979system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses
980system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for demand accesses
981system.cpu.dcache.demand_mshr_miss_rate::total 0.006690 # mshr miss rate for demand accesses
982system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for overall accesses
983system.cpu.dcache.overall_mshr_miss_rate::total 0.006690 # mshr miss rate for overall accesses
984system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17310.408827 # average ReadReq mshr miss latency
985system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17310.408827 # average ReadReq mshr miss latency
986system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26864.677077 # average WriteReq mshr miss latency
987system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26864.677077 # average WriteReq mshr miss latency
988system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency
989system.cpu.dcache.demand_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency
990system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency
991system.cpu.dcache.overall_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency
992system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
993
994---------- End Simulation Statistics ----------