1[root] 2type=Root 3children=system
| 1[root] 2type=Root 3children=system
|
| 4eventq_index=0
|
4full_system=false
| 5full_system=false
|
| 6sim_quantum=0
|
5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain
| 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain
|
| 17eventq_index=0
|
15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000
| 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000
|
| 39eventq_index=0
|
36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb
| 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51activity=0 52backComSize=5 53branchPred=system.cpu.branchPred 54cachePorts=200 55checker=Null 56clk_domain=system.cpu_clk_domain 57commitToDecodeDelay=1 58commitToFetchDelay=1 59commitToIEWDelay=1 60commitToRenameDelay=1 61commitWidth=8 62cpu_id=0 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb
|
| 71eventq_index=0 72fetchBufferSize=64
|
67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=true 88numIQEntries=64 89numPhysCCRegs=1280 90numPhysFloatRegs=256 91numPhysIntRegs=256 92numROBEntries=192 93numRobs=1 94numThreads=1 95profile=0 96progress_interval=0 97renameToDecodeDelay=1 98renameToFetchDelay=1 99renameToIEWDelay=2 100renameToROBDelay=1 101renameWidth=8 102simpoint_start_insts= 103smtCommitPolicy=RoundRobin 104smtFetchPolicy=SingleThread 105smtIQPolicy=Partitioned 106smtIQThreshold=100 107smtLSQPolicy=Partitioned 108smtLSQThreshold=100 109smtNumFetchingThreads=1 110smtROBPolicy=Partitioned 111smtROBThreshold=100 112squashWidth=8 113store_set_clear_period=250000 114switched_out=false 115system=system 116tracer=system.cpu.tracer 117trapLatency=13 118wbDepth=1 119wbWidth=8 120workload=system.cpu.workload 121dcache_port=system.cpu.dcache.cpu_side 122icache_port=system.cpu.icache.cpu_side 123 124[system.cpu.apic_clk_domain] 125type=DerivedClockDomain 126clk_divider=16 127clk_domain=system.cpu_clk_domain
| 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 81iewToDecodeDelay=1 82iewToFetchDelay=1 83iewToRenameDelay=1 84interrupts=system.cpu.interrupts 85isa=system.cpu.isa 86issueToExecuteDelay=1 87issueWidth=8 88itb=system.cpu.itb 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=true 94numIQEntries=64 95numPhysCCRegs=1280 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108simpoint_start_insts= 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu.workload 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.apic_clk_domain] 131type=DerivedClockDomain 132clk_divider=16 133clk_domain=system.cpu_clk_domain
|
| 134eventq_index=0
|
128 129[system.cpu.branchPred] 130type=BranchPredictor 131BTBEntries=4096 132BTBTagSize=16 133RASSize=16 134choiceCtrBits=2 135choicePredictorSize=8192
| 135 136[system.cpu.branchPred] 137type=BranchPredictor 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192
|
| 143eventq_index=0
|
136globalCtrBits=2 137globalPredictorSize=8192 138instShiftAmt=2 139localCtrBits=2 140localHistoryTableSize=2048 141localPredictorSize=2048 142numThreads=1 143predType=tournament 144 145[system.cpu.dcache] 146type=BaseCache 147children=tags 148addr_ranges=0:18446744073709551615 149assoc=2 150clk_domain=system.cpu_clk_domain
| 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151predType=tournament 152 153[system.cpu.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain
|
| 159eventq_index=0
|
151forward_snoops=true 152hit_latency=2 153is_top_level=true 154max_miss_count=0 155mshrs=4 156prefetch_on_access=false 157prefetcher=Null 158response_latency=2 159size=262144 160system=system 161tags=system.cpu.dcache.tags 162tgts_per_mshr=20 163two_queue=false 164write_buffers=8 165cpu_side=system.cpu.dcache_port 166mem_side=system.cpu.toL2Bus.slave[1] 167 168[system.cpu.dcache.tags] 169type=LRU 170assoc=2 171block_size=64 172clk_domain=system.cpu_clk_domain
| 160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168size=262144 169system=system 170tags=system.cpu.dcache.tags 171tgts_per_mshr=20 172two_queue=false 173write_buffers=8 174cpu_side=system.cpu.dcache_port 175mem_side=system.cpu.toL2Bus.slave[1] 176 177[system.cpu.dcache.tags] 178type=LRU 179assoc=2 180block_size=64 181clk_domain=system.cpu_clk_domain
|
| 182eventq_index=0
|
173hit_latency=2 174size=262144 175 176[system.cpu.dtb] 177type=X86TLB 178children=walker
| 183hit_latency=2 184size=262144 185 186[system.cpu.dtb] 187type=X86TLB 188children=walker
|
| 189eventq_index=0
|
179size=64 180walker=system.cpu.dtb.walker 181 182[system.cpu.dtb.walker] 183type=X86PagetableWalker 184clk_domain=system.cpu_clk_domain
| 190size=64 191walker=system.cpu.dtb.walker 192 193[system.cpu.dtb.walker] 194type=X86PagetableWalker 195clk_domain=system.cpu_clk_domain
|
| 196eventq_index=0
|
185num_squash_per_cycle=4 186system=system 187port=system.cpu.toL2Bus.slave[3] 188 189[system.cpu.fuPool] 190type=FUPool 191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 192FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
| 197num_squash_per_cycle=4 198system=system 199port=system.cpu.toL2Bus.slave[3] 200 201[system.cpu.fuPool] 202type=FUPool 203children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 204FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
| 205eventq_index=0
|
193 194[system.cpu.fuPool.FUList0] 195type=FUDesc 196children=opList 197count=6
| 206 207[system.cpu.fuPool.FUList0] 208type=FUDesc 209children=opList 210count=6
|
| 211eventq_index=0
|
198opList=system.cpu.fuPool.FUList0.opList 199 200[system.cpu.fuPool.FUList0.opList] 201type=OpDesc
| 212opList=system.cpu.fuPool.FUList0.opList 213 214[system.cpu.fuPool.FUList0.opList] 215type=OpDesc
|
| 216eventq_index=0
|
202issueLat=1 203opClass=IntAlu 204opLat=1 205 206[system.cpu.fuPool.FUList1] 207type=FUDesc 208children=opList0 opList1 209count=2
| 217issueLat=1 218opClass=IntAlu 219opLat=1 220 221[system.cpu.fuPool.FUList1] 222type=FUDesc 223children=opList0 opList1 224count=2
|
| 225eventq_index=0
|
210opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 211 212[system.cpu.fuPool.FUList1.opList0] 213type=OpDesc
| 226opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 227 228[system.cpu.fuPool.FUList1.opList0] 229type=OpDesc
|
| 230eventq_index=0
|
214issueLat=1 215opClass=IntMult 216opLat=3 217 218[system.cpu.fuPool.FUList1.opList1] 219type=OpDesc
| 231issueLat=1 232opClass=IntMult 233opLat=3 234 235[system.cpu.fuPool.FUList1.opList1] 236type=OpDesc
|
| 237eventq_index=0
|
220issueLat=19 221opClass=IntDiv 222opLat=20 223 224[system.cpu.fuPool.FUList2] 225type=FUDesc 226children=opList0 opList1 opList2 227count=4
| 238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4
|
| 246eventq_index=0
|
228opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 229 230[system.cpu.fuPool.FUList2.opList0] 231type=OpDesc
| 247opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 248 249[system.cpu.fuPool.FUList2.opList0] 250type=OpDesc
|
| 251eventq_index=0
|
232issueLat=1 233opClass=FloatAdd 234opLat=2 235 236[system.cpu.fuPool.FUList2.opList1] 237type=OpDesc
| 252issueLat=1 253opClass=FloatAdd 254opLat=2 255 256[system.cpu.fuPool.FUList2.opList1] 257type=OpDesc
|
| 258eventq_index=0
|
238issueLat=1 239opClass=FloatCmp 240opLat=2 241 242[system.cpu.fuPool.FUList2.opList2] 243type=OpDesc
| 259issueLat=1 260opClass=FloatCmp 261opLat=2 262 263[system.cpu.fuPool.FUList2.opList2] 264type=OpDesc
|
| 265eventq_index=0
|
244issueLat=1 245opClass=FloatCvt 246opLat=2 247 248[system.cpu.fuPool.FUList3] 249type=FUDesc 250children=opList0 opList1 opList2 251count=2
| 266issueLat=1 267opClass=FloatCvt 268opLat=2 269 270[system.cpu.fuPool.FUList3] 271type=FUDesc 272children=opList0 opList1 opList2 273count=2
|
| 274eventq_index=0
|
252opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 253 254[system.cpu.fuPool.FUList3.opList0] 255type=OpDesc
| 275opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 276 277[system.cpu.fuPool.FUList3.opList0] 278type=OpDesc
|
| 279eventq_index=0
|
256issueLat=1 257opClass=FloatMult 258opLat=4 259 260[system.cpu.fuPool.FUList3.opList1] 261type=OpDesc
| 280issueLat=1 281opClass=FloatMult 282opLat=4 283 284[system.cpu.fuPool.FUList3.opList1] 285type=OpDesc
|
| 286eventq_index=0
|
262issueLat=12 263opClass=FloatDiv 264opLat=12 265 266[system.cpu.fuPool.FUList3.opList2] 267type=OpDesc
| 287issueLat=12 288opClass=FloatDiv 289opLat=12 290 291[system.cpu.fuPool.FUList3.opList2] 292type=OpDesc
|
| 293eventq_index=0
|
268issueLat=24 269opClass=FloatSqrt 270opLat=24 271 272[system.cpu.fuPool.FUList4] 273type=FUDesc 274children=opList 275count=0
| 294issueLat=24 295opClass=FloatSqrt 296opLat=24 297 298[system.cpu.fuPool.FUList4] 299type=FUDesc 300children=opList 301count=0
|
| 302eventq_index=0
|
276opList=system.cpu.fuPool.FUList4.opList 277 278[system.cpu.fuPool.FUList4.opList] 279type=OpDesc
| 303opList=system.cpu.fuPool.FUList4.opList 304 305[system.cpu.fuPool.FUList4.opList] 306type=OpDesc
|
| 307eventq_index=0
|
280issueLat=1 281opClass=MemRead 282opLat=1 283 284[system.cpu.fuPool.FUList5] 285type=FUDesc 286children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 287count=4
| 308issueLat=1 309opClass=MemRead 310opLat=1 311 312[system.cpu.fuPool.FUList5] 313type=FUDesc 314children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 315count=4
|
| 316eventq_index=0
|
288opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 289 290[system.cpu.fuPool.FUList5.opList00] 291type=OpDesc
| 317opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 318 319[system.cpu.fuPool.FUList5.opList00] 320type=OpDesc
|
| 321eventq_index=0
|
292issueLat=1 293opClass=SimdAdd 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList01] 297type=OpDesc
| 322issueLat=1 323opClass=SimdAdd 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList01] 327type=OpDesc
|
| 328eventq_index=0
|
298issueLat=1 299opClass=SimdAddAcc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList02] 303type=OpDesc
| 329issueLat=1 330opClass=SimdAddAcc 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList02] 334type=OpDesc
|
| 335eventq_index=0
|
304issueLat=1 305opClass=SimdAlu 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList03] 309type=OpDesc
| 336issueLat=1 337opClass=SimdAlu 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList03] 341type=OpDesc
|
| 342eventq_index=0
|
310issueLat=1 311opClass=SimdCmp 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList04] 315type=OpDesc
| 343issueLat=1 344opClass=SimdCmp 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList04] 348type=OpDesc
|
| 349eventq_index=0
|
316issueLat=1 317opClass=SimdCvt 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList05] 321type=OpDesc
| 350issueLat=1 351opClass=SimdCvt 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList05] 355type=OpDesc
|
| 356eventq_index=0
|
322issueLat=1 323opClass=SimdMisc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList06] 327type=OpDesc
| 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList06] 362type=OpDesc
|
| 363eventq_index=0
|
328issueLat=1 329opClass=SimdMult 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList07] 333type=OpDesc
| 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList07] 369type=OpDesc
|
| 370eventq_index=0
|
334issueLat=1 335opClass=SimdMultAcc 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList08] 339type=OpDesc
| 371issueLat=1 372opClass=SimdMultAcc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList08] 376type=OpDesc
|
| 377eventq_index=0
|
340issueLat=1 341opClass=SimdShift 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList09] 345type=OpDesc
| 378issueLat=1 379opClass=SimdShift 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList09] 383type=OpDesc
|
| 384eventq_index=0
|
346issueLat=1 347opClass=SimdShiftAcc 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList10] 351type=OpDesc
| 385issueLat=1 386opClass=SimdShiftAcc 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList10] 390type=OpDesc
|
| 391eventq_index=0
|
352issueLat=1 353opClass=SimdSqrt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList11] 357type=OpDesc
| 392issueLat=1 393opClass=SimdSqrt 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList11] 397type=OpDesc
|
| 398eventq_index=0
|
358issueLat=1 359opClass=SimdFloatAdd 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList12] 363type=OpDesc
| 399issueLat=1 400opClass=SimdFloatAdd 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList12] 404type=OpDesc
|
| 405eventq_index=0
|
364issueLat=1 365opClass=SimdFloatAlu 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList13] 369type=OpDesc
| 406issueLat=1 407opClass=SimdFloatAlu 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList13] 411type=OpDesc
|
| 412eventq_index=0
|
370issueLat=1 371opClass=SimdFloatCmp 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList14] 375type=OpDesc
| 413issueLat=1 414opClass=SimdFloatCmp 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList14] 418type=OpDesc
|
| 419eventq_index=0
|
376issueLat=1 377opClass=SimdFloatCvt 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList15] 381type=OpDesc
| 420issueLat=1 421opClass=SimdFloatCvt 422opLat=1 423 424[system.cpu.fuPool.FUList5.opList15] 425type=OpDesc
|
| 426eventq_index=0
|
382issueLat=1 383opClass=SimdFloatDiv 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList16] 387type=OpDesc
| 427issueLat=1 428opClass=SimdFloatDiv 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList16] 432type=OpDesc
|
| 433eventq_index=0
|
388issueLat=1 389opClass=SimdFloatMisc 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList17] 393type=OpDesc
| 434issueLat=1 435opClass=SimdFloatMisc 436opLat=1 437 438[system.cpu.fuPool.FUList5.opList17] 439type=OpDesc
|
| 440eventq_index=0
|
394issueLat=1 395opClass=SimdFloatMult 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList18] 399type=OpDesc
| 441issueLat=1 442opClass=SimdFloatMult 443opLat=1 444 445[system.cpu.fuPool.FUList5.opList18] 446type=OpDesc
|
| 447eventq_index=0
|
400issueLat=1 401opClass=SimdFloatMultAcc 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList19] 405type=OpDesc
| 448issueLat=1 449opClass=SimdFloatMultAcc 450opLat=1 451 452[system.cpu.fuPool.FUList5.opList19] 453type=OpDesc
|
| 454eventq_index=0
|
406issueLat=1 407opClass=SimdFloatSqrt 408opLat=1 409 410[system.cpu.fuPool.FUList6] 411type=FUDesc 412children=opList 413count=0
| 455issueLat=1 456opClass=SimdFloatSqrt 457opLat=1 458 459[system.cpu.fuPool.FUList6] 460type=FUDesc 461children=opList 462count=0
|
| 463eventq_index=0
|
414opList=system.cpu.fuPool.FUList6.opList 415 416[system.cpu.fuPool.FUList6.opList] 417type=OpDesc
| 464opList=system.cpu.fuPool.FUList6.opList 465 466[system.cpu.fuPool.FUList6.opList] 467type=OpDesc
|
| 468eventq_index=0
|
418issueLat=1 419opClass=MemWrite 420opLat=1 421 422[system.cpu.fuPool.FUList7] 423type=FUDesc 424children=opList0 opList1 425count=4
| 469issueLat=1 470opClass=MemWrite 471opLat=1 472 473[system.cpu.fuPool.FUList7] 474type=FUDesc 475children=opList0 opList1 476count=4
|
| 477eventq_index=0
|
426opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 427 428[system.cpu.fuPool.FUList7.opList0] 429type=OpDesc
| 478opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 479 480[system.cpu.fuPool.FUList7.opList0] 481type=OpDesc
|
| 482eventq_index=0
|
430issueLat=1 431opClass=MemRead 432opLat=1 433 434[system.cpu.fuPool.FUList7.opList1] 435type=OpDesc
| 483issueLat=1 484opClass=MemRead 485opLat=1 486 487[system.cpu.fuPool.FUList7.opList1] 488type=OpDesc
|
| 489eventq_index=0
|
436issueLat=1 437opClass=MemWrite 438opLat=1 439 440[system.cpu.fuPool.FUList8] 441type=FUDesc 442children=opList 443count=1
| 490issueLat=1 491opClass=MemWrite 492opLat=1 493 494[system.cpu.fuPool.FUList8] 495type=FUDesc 496children=opList 497count=1
|
| 498eventq_index=0
|
444opList=system.cpu.fuPool.FUList8.opList 445 446[system.cpu.fuPool.FUList8.opList] 447type=OpDesc
| 499opList=system.cpu.fuPool.FUList8.opList 500 501[system.cpu.fuPool.FUList8.opList] 502type=OpDesc
|
| 503eventq_index=0
|
448issueLat=3 449opClass=IprAccess 450opLat=3 451 452[system.cpu.icache] 453type=BaseCache 454children=tags 455addr_ranges=0:18446744073709551615 456assoc=2 457clk_domain=system.cpu_clk_domain
| 504issueLat=3 505opClass=IprAccess 506opLat=3 507 508[system.cpu.icache] 509type=BaseCache 510children=tags 511addr_ranges=0:18446744073709551615 512assoc=2 513clk_domain=system.cpu_clk_domain
|
| 514eventq_index=0
|
458forward_snoops=true 459hit_latency=2 460is_top_level=true 461max_miss_count=0 462mshrs=4 463prefetch_on_access=false 464prefetcher=Null 465response_latency=2 466size=131072 467system=system 468tags=system.cpu.icache.tags 469tgts_per_mshr=20 470two_queue=false 471write_buffers=8 472cpu_side=system.cpu.icache_port 473mem_side=system.cpu.toL2Bus.slave[0] 474 475[system.cpu.icache.tags] 476type=LRU 477assoc=2 478block_size=64 479clk_domain=system.cpu_clk_domain
| 515forward_snoops=true 516hit_latency=2 517is_top_level=true 518max_miss_count=0 519mshrs=4 520prefetch_on_access=false 521prefetcher=Null 522response_latency=2 523size=131072 524system=system 525tags=system.cpu.icache.tags 526tgts_per_mshr=20 527two_queue=false 528write_buffers=8 529cpu_side=system.cpu.icache_port 530mem_side=system.cpu.toL2Bus.slave[0] 531 532[system.cpu.icache.tags] 533type=LRU 534assoc=2 535block_size=64 536clk_domain=system.cpu_clk_domain
|
| 537eventq_index=0
|
480hit_latency=2 481size=131072 482 483[system.cpu.interrupts] 484type=X86LocalApic 485clk_domain=system.cpu.apic_clk_domain
| 538hit_latency=2 539size=131072 540 541[system.cpu.interrupts] 542type=X86LocalApic 543clk_domain=system.cpu.apic_clk_domain
|
| 544eventq_index=0
|
486int_latency=1000 487pio_addr=2305843009213693952 488pio_latency=100000 489system=system 490int_master=system.membus.slave[2] 491int_slave=system.membus.master[2] 492pio=system.membus.master[1] 493 494[system.cpu.isa] 495type=X86ISA
| 545int_latency=1000 546pio_addr=2305843009213693952 547pio_latency=100000 548system=system 549int_master=system.membus.slave[2] 550int_slave=system.membus.master[2] 551pio=system.membus.master[1] 552 553[system.cpu.isa] 554type=X86ISA
|
| 555eventq_index=0
|
496 497[system.cpu.itb] 498type=X86TLB 499children=walker
| 556 557[system.cpu.itb] 558type=X86TLB 559children=walker
|
| 560eventq_index=0
|
500size=64 501walker=system.cpu.itb.walker 502 503[system.cpu.itb.walker] 504type=X86PagetableWalker 505clk_domain=system.cpu_clk_domain
| 561size=64 562walker=system.cpu.itb.walker 563 564[system.cpu.itb.walker] 565type=X86PagetableWalker 566clk_domain=system.cpu_clk_domain
|
| 567eventq_index=0
|
506num_squash_per_cycle=4 507system=system 508port=system.cpu.toL2Bus.slave[2] 509 510[system.cpu.l2cache] 511type=BaseCache 512children=tags 513addr_ranges=0:18446744073709551615 514assoc=8 515clk_domain=system.cpu_clk_domain
| 568num_squash_per_cycle=4 569system=system 570port=system.cpu.toL2Bus.slave[2] 571 572[system.cpu.l2cache] 573type=BaseCache 574children=tags 575addr_ranges=0:18446744073709551615 576assoc=8 577clk_domain=system.cpu_clk_domain
|
| 578eventq_index=0
|
516forward_snoops=true 517hit_latency=20 518is_top_level=false 519max_miss_count=0 520mshrs=20 521prefetch_on_access=false 522prefetcher=Null 523response_latency=20 524size=2097152 525system=system 526tags=system.cpu.l2cache.tags 527tgts_per_mshr=12 528two_queue=false 529write_buffers=8 530cpu_side=system.cpu.toL2Bus.master[0] 531mem_side=system.membus.slave[1] 532 533[system.cpu.l2cache.tags] 534type=LRU 535assoc=8 536block_size=64 537clk_domain=system.cpu_clk_domain
| 579forward_snoops=true 580hit_latency=20 581is_top_level=false 582max_miss_count=0 583mshrs=20 584prefetch_on_access=false 585prefetcher=Null 586response_latency=20 587size=2097152 588system=system 589tags=system.cpu.l2cache.tags 590tgts_per_mshr=12 591two_queue=false 592write_buffers=8 593cpu_side=system.cpu.toL2Bus.master[0] 594mem_side=system.membus.slave[1] 595 596[system.cpu.l2cache.tags] 597type=LRU 598assoc=8 599block_size=64 600clk_domain=system.cpu_clk_domain
|
| 601eventq_index=0
|
538hit_latency=20 539size=2097152 540 541[system.cpu.toL2Bus] 542type=CoherentBus 543clk_domain=system.cpu_clk_domain
| 602hit_latency=20 603size=2097152 604 605[system.cpu.toL2Bus] 606type=CoherentBus 607clk_domain=system.cpu_clk_domain
|
| 608eventq_index=0
|
544header_cycles=1 545system=system 546use_default_range=false 547width=32 548master=system.cpu.l2cache.cpu_side 549slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 550 551[system.cpu.tracer] 552type=ExeTracer
| 609header_cycles=1 610system=system 611use_default_range=false 612width=32 613master=system.cpu.l2cache.cpu_side 614slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 615 616[system.cpu.tracer] 617type=ExeTracer
|
| 618eventq_index=0
|
553 554[system.cpu.workload] 555type=LiveProcess 556cmd=parser 2.1.dict -batch 557cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 558egid=100 559env= 560errout=cerr 561euid=100
| 619 620[system.cpu.workload] 621type=LiveProcess 622cmd=parser 2.1.dict -batch 623cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 624egid=100 625env= 626errout=cerr 627euid=100
|
562executable=/dist/m5/cpu2000/binaries/x86/linux/parser
| 628eventq_index=0 629executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
563gid=100
| 630gid=100
|
564input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
| 631input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
565max_stack_size=67108864 566output=cout 567pid=100 568ppid=99 569simpoint=114600000000 570system=system 571uid=100 572 573[system.cpu_clk_domain] 574type=SrcClockDomain 575clock=500
| 632max_stack_size=67108864 633output=cout 634pid=100 635ppid=99 636simpoint=114600000000 637system=system 638uid=100 639 640[system.cpu_clk_domain] 641type=SrcClockDomain 642clock=500
|
| 643eventq_index=0
|
576voltage_domain=system.voltage_domain 577 578[system.membus] 579type=CoherentBus 580clk_domain=system.clk_domain
| 644voltage_domain=system.voltage_domain 645 646[system.membus] 647type=CoherentBus 648clk_domain=system.clk_domain
|
| 649eventq_index=0
|
581header_cycles=1 582system=system 583use_default_range=false 584width=8 585master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 586slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 587 588[system.physmem] 589type=SimpleDRAM 590activation_limit=4 591addr_mapping=RaBaChCo 592banks_per_rank=8 593burst_length=8 594channels=1 595clk_domain=system.clk_domain 596conf_table_reported=true 597device_bus_width=8 598device_rowbuffer_size=1024 599devices_per_rank=8
| 650header_cycles=1 651system=system 652use_default_range=false 653width=8 654master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 655slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 656 657[system.physmem] 658type=SimpleDRAM 659activation_limit=4 660addr_mapping=RaBaChCo 661banks_per_rank=8 662burst_length=8 663channels=1 664clk_domain=system.clk_domain 665conf_table_reported=true 666device_bus_width=8 667device_rowbuffer_size=1024 668devices_per_rank=8
|
| 669eventq_index=0
|
600in_addr_map=true 601mem_sched_policy=frfcfs 602null=false 603page_policy=open 604range=0:134217727 605ranks_per_channel=2 606read_buffer_size=32 607static_backend_latency=10000 608static_frontend_latency=10000 609tBURST=5000 610tCL=13750
| 670in_addr_map=true 671mem_sched_policy=frfcfs 672null=false 673page_policy=open 674range=0:134217727 675ranks_per_channel=2 676read_buffer_size=32 677static_backend_latency=10000 678static_frontend_latency=10000 679tBURST=5000 680tCL=13750
|
| 681tRAS=35000
|
611tRCD=13750 612tREFI=7800000 613tRFC=300000 614tRP=13750
| 682tRCD=13750 683tREFI=7800000 684tRFC=300000 685tRP=13750
|
| 686tRRD=6250
|
615tWTR=7500 616tXAW=40000 617write_buffer_size=32
| 687tWTR=7500 688tXAW=40000 689write_buffer_size=32
|
618write_thresh_perc=70
| 690write_high_thresh_perc=70 691write_low_thresh_perc=0
|
619port=system.membus.master[0] 620 621[system.voltage_domain] 622type=VoltageDomain
| 692port=system.membus.master[0] 693 694[system.voltage_domain] 695type=VoltageDomain
|
| 696eventq_index=0
|
623voltage=1.000000 624
| 697voltage=1.000000 698
|