1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 165 unchanged lines hidden (view full) ---

174localHistoryTableSize=2048
175localPredictorSize=2048
176numThreads=1
177useIndirect=true
178
179[system.cpu.dcache]
180type=Cache
181children=tags
182addr_ranges=0:18446744073709551615
183assoc=2
184clk_domain=system.cpu_clk_domain
185clusivity=mostly_incl
186default_p_state=UNDEFINED
187demand_mshr_reserve=1
188eventq_index=0
189hit_latency=2
190is_read_only=false

--- 356 unchanged lines hidden (view full) ---

547eventq_index=0
548opClass=IprAccess
549opLat=3
550pipelined=false
551
552[system.cpu.icache]
553type=Cache
554children=tags
555addr_ranges=0:18446744073709551615
556assoc=2
557clk_domain=system.cpu_clk_domain
558clusivity=mostly_incl
559default_p_state=UNDEFINED
560demand_mshr_reserve=1
561eventq_index=0
562hit_latency=2
563is_read_only=true

--- 70 unchanged lines hidden (view full) ---

634p_state_clk_gate_min=1000
635power_model=Null
636system=system
637port=system.cpu.toL2Bus.slave[2]
638
639[system.cpu.l2cache]
640type=Cache
641children=tags
642addr_ranges=0:18446744073709551615
643assoc=8
644clk_domain=system.cpu_clk_domain
645clusivity=mostly_incl
646default_p_state=UNDEFINED
647demand_mshr_reserve=1
648eventq_index=0
649hit_latency=20
650is_read_only=false

--- 100 unchanged lines hidden (view full) ---

751domains=
752enable=false
753eventq_index=0
754sys_clk_domain=system.clk_domain
755transition_latency=100000000
756
757[system.membus]
758type=CoherentXBar
759clk_domain=system.clk_domain
760default_p_state=UNDEFINED
761eventq_index=0
762forward_latency=4
763frontend_latency=3
764p_state_clk_gate_bins=20
765p_state_clk_gate_max=1000000000000
766p_state_clk_gate_min=1000
767point_of_coherency=true
768power_model=Null
769response_latency=2
770snoop_filter=Null
771snoop_response_latency=4
772system=system
773use_default_range=false
774width=16
775master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
776slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
777
778[system.physmem]
779type=DRAMCtrl
780IDD0=0.075000
781IDD02=0.000000
782IDD2N=0.050000
783IDD2N2=0.000000
784IDD2P0=0.000000
785IDD2P02=0.000000
786IDD2P1=0.000000
787IDD2P12=0.000000
788IDD3N=0.057000
789IDD3N2=0.000000
790IDD3P0=0.000000
791IDD3P02=0.000000
792IDD3P1=0.000000
793IDD3P12=0.000000
794IDD4R=0.187000
795IDD4R2=0.000000
796IDD4W=0.165000
797IDD4W2=0.000000
798IDD5=0.220000
799IDD52=0.000000
800IDD6=0.000000
801IDD62=0.000000
802VDD=1.500000
803VDD2=0.000000
804activation_limit=4
805addr_mapping=RoRaBaCoCh
806bank_groups_per_rank=0
807banks_per_rank=8
808burst_length=8
809channels=1
810clk_domain=system.clk_domain
811conf_table_reported=true
812default_p_state=UNDEFINED
813device_bus_width=8
814device_rowbuffer_size=1024
815device_size=536870912
816devices_per_rank=8
817dll=true
818eventq_index=0
819in_addr_map=true
820max_accesses_per_row=16
821mem_sched_policy=frfcfs
822min_writes_per_switch=16
823null=false
824p_state_clk_gate_bins=20
825p_state_clk_gate_max=1000000000000
826p_state_clk_gate_min=1000
827page_policy=open_adaptive
828power_model=Null
829range=0:134217727
830ranks_per_channel=2
831read_buffer_size=32
832static_backend_latency=10000
833static_frontend_latency=10000
834tBURST=5000
835tCCD_L=0
836tCK=1250
837tCL=13750

--- 5 unchanged lines hidden (view full) ---

843tRP=13750
844tRRD=6000
845tRRD_L=0
846tRTP=7500
847tRTW=2500
848tWR=15000
849tWTR=7500
850tXAW=30000
851tXP=0
852tXPDLL=0
853tXS=0
854tXSDLL=0
855write_buffer_size=64
856write_high_thresh_perc=85
857write_low_thresh_perc=50
858port=system.membus.master[0]
859
860[system.voltage_domain]
861type=VoltageDomain
862eventq_index=0
863voltage=1.000000
864