| stats.txt (9285:9901180cd573) | stats.txt (9322:01c8c5ff2c3b) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.717833 # Number of seconds simulated 4sim_ticks 717832876000 # Number of ticks simulated 5final_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.717366 # Number of seconds simulated 4sim_ticks 717366012000 # Number of ticks simulated 5final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1074460 # Simulator instruction rate (inst/s) 8host_op_rate 1210735 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1527332222 # Simulator tick rate (ticks/s) 10host_mem_usage 237040 # Number of bytes of host memory used 11host_seconds 469.99 # Real time elapsed on the host | 7host_inst_rate 512177 # Simulator instruction rate (inst/s) 8host_op_rate 577137 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 727580493 # Simulator tick rate (ticks/s) 10host_mem_usage 234620 # Number of bytes of host memory used 11host_seconds 985.96 # Real time elapsed on the host |
| 12sim_insts 504986853 # Number of instructions simulated 13sim_ops 569034839 # Number of ops (including micro ops) simulated | 12sim_insts 504986853 # Number of instructions simulated 13sim_ops 569034839 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9842240 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6574720 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 548 # Number of system calls | 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 548 # Number of system calls |
| 80system.cpu.numCycles 1435665752 # number of cpu cycles simulated | 80system.cpu.numCycles 1434732024 # number of cpu cycles simulated |
| 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.committedInsts 504986853 # Number of instructions committed 84system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed 85system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses 86system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 87system.cpu.num_func_calls 19311615 # number of times a function call or return occured 88system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls 89system.cpu.num_int_insts 470727695 # number of integer instructions 90system.cpu.num_fp_insts 16 # number of float instructions 91system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read 92system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written 93system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 94system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 95system.cpu.num_mem_refs 182890034 # number of memory refs 96system.cpu.num_load_insts 126029555 # Number of load instructions 97system.cpu.num_store_insts 56860479 # Number of store instructions 98system.cpu.num_idle_cycles 0 # Number of idle cycles | 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.committedInsts 504986853 # Number of instructions committed 84system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed 85system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses 86system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 87system.cpu.num_func_calls 19311615 # number of times a function call or return occured 88system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls 89system.cpu.num_int_insts 470727695 # number of integer instructions 90system.cpu.num_fp_insts 16 # number of float instructions 91system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read 92system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written 93system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 94system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 95system.cpu.num_mem_refs 182890034 # number of memory refs 96system.cpu.num_load_insts 126029555 # Number of load instructions 97system.cpu.num_store_insts 56860479 # Number of store instructions 98system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 99system.cpu.num_busy_cycles 1435665752 # Number of busy cycles | 99system.cpu.num_busy_cycles 1434732024 # Number of busy cycles |
| 100system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 101system.cpu.idle_fraction 0 # Percentage of idle cycles 102system.cpu.icache.replacements 9788 # number of replacements | 100system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 101system.cpu.idle_fraction 0 # Percentage of idle cycles 102system.cpu.icache.replacements 9788 # number of replacements |
| 103system.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use | 103system.cpu.icache.tagsinuse 982.663229 # Cycle average of tags in use |
| 104system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. 105system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. 106system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. 107system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 104system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. 105system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. 106system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. 107system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 108system.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor 109system.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy 110system.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy | 108system.cpu.icache.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor 109system.cpu.icache.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy 110system.cpu.icache.occ_percent::total 0.479816 # Average percentage of cache occupancy |
| 111system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits 112system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits 113system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits 114system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits 115system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits 116system.cpu.icache.overall_hits::total 516599855 # number of overall hits 117system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 118system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 119system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 120system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 121system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 122system.cpu.icache.overall_misses::total 11521 # number of overall misses | 111system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits 112system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits 113system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits 114system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits 115system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits 116system.cpu.icache.overall_hits::total 516599855 # number of overall hits 117system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 118system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 119system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 120system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 121system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 122system.cpu.icache.overall_misses::total 11521 # number of overall misses |
| 123system.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles 124system.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles 125system.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles 126system.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles 127system.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles 128system.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles | 123system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles 124system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles 125system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles 126system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles 127system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles 128system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles |
| 129system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) 130system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) 131system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses 132system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses 133system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses 134system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses 135system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 136system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 137system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 138system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 139system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 140system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses | 129system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) 130system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) 131system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses 132system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses 133system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses 134system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses 135system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 136system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 137system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 138system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 139system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 140system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses |
| 141system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency 142system.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency 143system.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency 144system.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency 145system.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency 146system.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency | 141system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency 142system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency 143system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency 144system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency 145system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency 146system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency |
| 147system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 148system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 149system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 150system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 151system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 152system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 153system.cpu.icache.fast_writes 0 # number of fast writes performed 154system.cpu.icache.cache_copies 0 # number of cache copies performed 155system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 156system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 157system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 158system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 159system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 160system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses | 147system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 148system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 149system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 150system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 151system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 152system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 153system.cpu.icache.fast_writes 0 # number of fast writes performed 154system.cpu.icache.cache_copies 0 # number of cache copies performed 155system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 156system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 157system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 158system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 159system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 160system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses |
| 161system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles 162system.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles 163system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles 164system.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles 165system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles 166system.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles | 161system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles 162system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles 163system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles 164system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles 165system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles 166system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles |
| 167system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 168system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 169system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 170system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 171system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 172system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses | 167system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 168system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 169system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 170system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 171system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 172system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses |
| 173system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency 174system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency 175system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency 176system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency 177system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency 178system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency | 173system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency 174system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency 175system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency 176system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency 177system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency 178system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency |
| 179system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 180system.cpu.dcache.replacements 1134822 # number of replacements | 179system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 180system.cpu.dcache.replacements 1134822 # number of replacements |
| 181system.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use | 181system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use |
| 182system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. 183system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. 184system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. 185system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. | 182system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. 183system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. 184system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. 185system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. |
| 186system.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor 187system.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy 188system.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy | 186system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor 187system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy 188system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy |
| 189system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits 190system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits 191system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 192system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 193system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 194system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 195system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 196system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 201system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses 202system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses 203system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 204system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 205system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses 206system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses 207system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 208system.cpu.dcache.overall_misses::total 1138918 # number of overall misses | 189system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits 190system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits 191system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 192system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 193system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 194system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 195system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 196system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 201system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses 202system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses 203system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 204system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 205system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses 206system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses 207system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 208system.cpu.dcache.overall_misses::total 1138918 # number of overall misses |
| 209system.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles 210system.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles 211system.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles 212system.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles 213system.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles 214system.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles 215system.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles 216system.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles | 209system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles 210system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles 211system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles 212system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles 213system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles 214system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles 215system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles 216system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles |
| 217system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) 218system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) 219system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 220system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 221system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 222system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 223system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 224system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 229system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses 230system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses 231system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 232system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 233system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses 234system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses 235system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses 236system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses | 217system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) 218system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) 219system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 220system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 221system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 222system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 223system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 224system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 229system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses 230system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses 231system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 232system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 233system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses 234system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses 235system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses 236system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses |
| 237system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency 238system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency 239system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency 240system.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency 241system.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency 242system.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency 243system.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency 244system.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency | 237system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency 238system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency 239system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency 240system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency 241system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency 242system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency 243system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency 244system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency |
| 245system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 249system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 250system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 251system.cpu.dcache.fast_writes 0 # number of fast writes performed 252system.cpu.dcache.cache_copies 0 # number of cache copies performed | 245system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 249system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 250system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 251system.cpu.dcache.fast_writes 0 # number of fast writes performed 252system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 253system.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks 254system.cpu.dcache.writebacks::total 1061444 # number of writebacks | 253system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks 254system.cpu.dcache.writebacks::total 1064905 # number of writebacks |
| 255system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses 256system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses 257system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 258system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 259system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses 260system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses 261system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 262system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses | 255system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses 256system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses 257system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 258system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 259system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses 260system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses 261system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 262system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses |
| 263system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10613061000 # number of ReadReq MSHR miss cycles 264system.cpu.dcache.ReadReq_mshr_miss_latency::total 10613061000 # number of ReadReq MSHR miss cycles 265system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257505000 # number of WriteReq MSHR miss cycles 266system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257505000 # number of WriteReq MSHR miss cycles 267system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870566000 # number of demand (read+write) MSHR miss cycles 268system.cpu.dcache.demand_mshr_miss_latency::total 18870566000 # number of demand (read+write) MSHR miss cycles 269system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870566000 # number of overall MSHR miss cycles 270system.cpu.dcache.overall_mshr_miss_latency::total 18870566000 # number of overall MSHR miss cycles | 263system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles 264system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles 265system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles 266system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles 267system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles 268system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles 269system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles 270system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles |
| 271system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses 272system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses 273system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 274system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 275system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses 276system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses 277system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses 278system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses | 271system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses 272system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses 273system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 274system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 275system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses 276system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses 277system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses 278system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses |
| 279system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13560.279202 # average ReadReq mshr miss latency 280system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13560.279202 # average ReadReq mshr miss latency 281system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.310784 # average WriteReq mshr miss latency 282system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.310784 # average WriteReq mshr miss latency 283system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency 284system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency 285system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency 286system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency | 279system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency 280system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency 281system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency 282system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency 283system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency 284system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency 285system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency 286system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency |
| 287system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 287system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 288system.cpu.l2cache.replacements 122482 # number of replacements 289system.cpu.l2cache.tagsinuse 26931.505779 # Cycle average of tags in use 290system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks. 291system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks. 292system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks. 293system.cpu.l2cache.warmup_cycle 343812481000 # Cycle when the warmup percentage was hit. 294system.cpu.l2cache.occ_blocks::writebacks 23220.335885 # Average occupied blocks per requestor 295system.cpu.l2cache.occ_blocks::cpu.inst 246.652044 # Average occupied blocks per requestor 296system.cpu.l2cache.occ_blocks::cpu.data 3464.517849 # Average occupied blocks per requestor 297system.cpu.l2cache.occ_percent::writebacks 0.708628 # Average percentage of cache occupancy 298system.cpu.l2cache.occ_percent::cpu.inst 0.007527 # Average percentage of cache occupancy 299system.cpu.l2cache.occ_percent::cpu.data 0.105729 # Average percentage of cache occupancy 300system.cpu.l2cache.occ_percent::total 0.821884 # Average percentage of cache occupancy 301system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits 302system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits 303system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits 304system.cpu.l2cache.Writeback_hits::writebacks 1061444 # number of Writeback hits 305system.cpu.l2cache.Writeback_hits::total 1061444 # number of Writeback hits 306system.cpu.l2cache.ReadExReq_hits::cpu.data 252959 # number of ReadExReq hits 307system.cpu.l2cache.ReadExReq_hits::total 252959 # number of ReadExReq hits 308system.cpu.l2cache.demand_hits::cpu.inst 8734 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::cpu.data 987920 # number of demand (read+write) hits 310system.cpu.l2cache.demand_hits::total 996654 # number of demand (read+write) hits 311system.cpu.l2cache.overall_hits::cpu.inst 8734 # number of overall hits 312system.cpu.l2cache.overall_hits::cpu.data 987920 # number of overall hits 313system.cpu.l2cache.overall_hits::total 996654 # number of overall hits 314system.cpu.l2cache.ReadReq_misses::cpu.inst 2787 # number of ReadReq misses 315system.cpu.l2cache.ReadReq_misses::cpu.data 47697 # number of ReadReq misses 316system.cpu.l2cache.ReadReq_misses::total 50484 # number of ReadReq misses 317system.cpu.l2cache.ReadExReq_misses::cpu.data 103301 # number of ReadExReq misses 318system.cpu.l2cache.ReadExReq_misses::total 103301 # number of ReadExReq misses 319system.cpu.l2cache.demand_misses::cpu.inst 2787 # number of demand (read+write) misses 320system.cpu.l2cache.demand_misses::cpu.data 150998 # number of demand (read+write) misses 321system.cpu.l2cache.demand_misses::total 153785 # number of demand (read+write) misses 322system.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses 323system.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses 324system.cpu.l2cache.overall_misses::total 153785 # number of overall misses 325system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144931000 # number of ReadReq miss cycles 326system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480793000 # number of ReadReq miss cycles 327system.cpu.l2cache.ReadReq_miss_latency::total 2625724000 # number of ReadReq miss cycles 328system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371655000 # number of ReadExReq miss cycles 329system.cpu.l2cache.ReadExReq_miss_latency::total 5371655000 # number of ReadExReq miss cycles 330system.cpu.l2cache.demand_miss_latency::cpu.inst 144931000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.demand_miss_latency::cpu.data 7852448000 # number of demand (read+write) miss cycles 332system.cpu.l2cache.demand_miss_latency::total 7997379000 # number of demand (read+write) miss cycles 333system.cpu.l2cache.overall_miss_latency::cpu.inst 144931000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::cpu.data 7852448000 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_latency::total 7997379000 # number of overall miss cycles | 288system.cpu.l2cache.replacements 109895 # number of replacements 289system.cpu.l2cache.tagsinuse 27243.192324 # Cycle average of tags in use 290system.cpu.l2cache.total_refs 1668833 # Total number of references to valid blocks. 291system.cpu.l2cache.sampled_refs 141072 # Sample count of references to valid blocks. 292system.cpu.l2cache.avg_refs 11.829654 # Average number of references to valid blocks. 293system.cpu.l2cache.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. 294system.cpu.l2cache.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor 295system.cpu.l2cache.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor 296system.cpu.l2cache.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor 297system.cpu.l2cache.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy 298system.cpu.l2cache.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy 299system.cpu.l2cache.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy 300system.cpu.l2cache.occ_percent::total 0.831396 # Average percentage of cache occupancy 301system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits 302system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits 303system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits 304system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits 305system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits 306system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits 307system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits 308system.cpu.l2cache.demand_hits::cpu.inst 8751 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::cpu.data 999039 # number of demand (read+write) hits 310system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits 311system.cpu.l2cache.overall_hits::cpu.inst 8751 # number of overall hits 312system.cpu.l2cache.overall_hits::cpu.data 999039 # number of overall hits 313system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits 314system.cpu.l2cache.ReadReq_misses::cpu.inst 2770 # number of ReadReq misses 315system.cpu.l2cache.ReadReq_misses::cpu.data 39085 # number of ReadReq misses 316system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses 317system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses 318system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses 319system.cpu.l2cache.demand_misses::cpu.inst 2770 # number of demand (read+write) misses 320system.cpu.l2cache.demand_misses::cpu.data 139879 # number of demand (read+write) misses 321system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses 322system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses 323system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses 324system.cpu.l2cache.overall_misses::total 142649 # number of overall misses 325system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles 326system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles 327system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles 328system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles 329system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles 330system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles 332system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles 333system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles |
| 336system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 337system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 338system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) | 336system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 337system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 338system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) |
| 339system.cpu.l2cache.Writeback_accesses::writebacks 1061444 # number of Writeback accesses(hits+misses) 340system.cpu.l2cache.Writeback_accesses::total 1061444 # number of Writeback accesses(hits+misses) | 339system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses) 340system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses) |
| 341system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 342system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 343system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 344system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 345system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 346system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 347system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 348system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses | 341system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 342system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 343system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 344system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 345system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 346system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 347system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 348system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses |
| 349system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.241906 # miss rate for ReadReq accesses 350system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses 351system.cpu.l2cache.ReadReq_miss_rate::total 0.063568 # miss rate for ReadReq accesses 352system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.289960 # miss rate for ReadExReq accesses 353system.cpu.l2cache.ReadExReq_miss_rate::total 0.289960 # miss rate for ReadExReq accesses 354system.cpu.l2cache.demand_miss_rate::cpu.inst 0.241906 # miss rate for demand accesses 355system.cpu.l2cache.demand_miss_rate::cpu.data 0.132580 # miss rate for demand accesses 356system.cpu.l2cache.demand_miss_rate::total 0.133675 # miss rate for demand accesses 357system.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses 358system.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses 359system.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses 360system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.511661 # average ReadReq miss latency 361system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52011.510158 # average ReadReq miss latency 362system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.013390 # average ReadReq miss latency 363system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.029041 # average ReadExReq miss latency 364system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.029041 # average ReadExReq miss latency 365system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency 366system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency 367system.cpu.l2cache.demand_avg_miss_latency::total 52003.634945 # average overall miss latency 368system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency 370system.cpu.l2cache.overall_avg_miss_latency::total 52003.634945 # average overall miss latency | 349system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240431 # miss rate for ReadReq accesses 350system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049939 # miss rate for ReadReq accesses 351system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses 352system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses 353system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses 354system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240431 # miss rate for demand accesses 355system.cpu.l2cache.demand_miss_rate::cpu.data 0.122817 # miss rate for demand accesses 356system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses 357system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses 358system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses 359system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses 360system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency 361system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency 362system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency 363system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency 364system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency 365system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency 366system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency 367system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency 368system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency 370system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency |
| 371system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 376system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 377system.cpu.l2cache.fast_writes 0 # number of fast writes performed 378system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 371system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 376system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 377system.cpu.l2cache.fast_writes 0 # number of fast writes performed 378system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 379system.cpu.l2cache.writebacks::writebacks 102730 # number of writebacks 380system.cpu.l2cache.writebacks::total 102730 # number of writebacks 381system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2787 # number of ReadReq MSHR misses 382system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 47697 # number of ReadReq MSHR misses 383system.cpu.l2cache.ReadReq_mshr_misses::total 50484 # number of ReadReq MSHR misses 384system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103301 # number of ReadExReq MSHR misses 385system.cpu.l2cache.ReadExReq_mshr_misses::total 103301 # number of ReadExReq MSHR misses 386system.cpu.l2cache.demand_mshr_misses::cpu.inst 2787 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.demand_mshr_misses::cpu.data 150998 # number of demand (read+write) MSHR misses 388system.cpu.l2cache.demand_mshr_misses::total 153785 # number of demand (read+write) MSHR misses 389system.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses 390system.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses 391system.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses 392system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111487000 # number of ReadReq MSHR miss cycles 393system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1908429000 # number of ReadReq MSHR miss cycles 394system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019916000 # number of ReadReq MSHR miss cycles 395system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132043000 # number of ReadExReq MSHR miss cycles 396system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132043000 # number of ReadExReq MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111487000 # number of demand (read+write) MSHR miss cycles 398system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6040472000 # number of demand (read+write) MSHR miss cycles 399system.cpu.l2cache.demand_mshr_miss_latency::total 6151959000 # number of demand (read+write) MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111487000 # number of overall MSHR miss cycles 401system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6040472000 # number of overall MSHR miss cycles 402system.cpu.l2cache.overall_mshr_miss_latency::total 6151959000 # number of overall MSHR miss cycles 403system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses 404system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses 405system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses 406system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.289960 # mshr miss rate for ReadExReq accesses 407system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.289960 # mshr miss rate for ReadExReq accesses 408system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for demand accesses 409system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for demand accesses 410system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 # mshr miss rate for demand accesses 411system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses 412system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses 413system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses 414system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.511661 # average ReadReq mshr miss latency 415system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40011.510158 # average ReadReq mshr miss latency 416system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.013390 # average ReadReq mshr miss latency 417system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.029041 # average ReadExReq mshr miss latency 418system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.029041 # average ReadExReq mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency 421system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency 424system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency | 379system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks 380system.cpu.l2cache.writebacks::total 95953 # number of writebacks 381system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2770 # number of ReadReq MSHR misses 382system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39085 # number of ReadReq MSHR misses 383system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses 384system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses 385system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses 386system.cpu.l2cache.demand_mshr_misses::cpu.inst 2770 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.demand_mshr_misses::cpu.data 139879 # number of demand (read+write) MSHR misses 388system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses 389system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses 390system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses 391system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses 392system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles 393system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles 394system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles 395system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles 396system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles 398system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles 399system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles 401system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles 402system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles 403system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses 404system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses 405system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses 406system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses 407system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses 408system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses 409system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses 410system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses 411system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses 412system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses 413system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses 414system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency 415system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency 416system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency 417system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency 418system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency 421system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency 424system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency |
| 425system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 426 427---------- End Simulation Statistics ---------- | 425system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 426 427---------- End Simulation Statistics ---------- |