| stats.txt (11388:bd4125134e77) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.708539 # Number of seconds simulated 4sim_ticks 708539449500 # Number of ticks simulated 5final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.708539 # Number of seconds simulated 4sim_ticks 708539449500 # Number of ticks simulated 5final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 318121 # Simulator instruction rate (inst/s) 8host_op_rate 344511 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 446353500 # Simulator tick rate (ticks/s) 10host_mem_usage 303968 # Number of bytes of host memory used 11host_seconds 1587.40 # Real time elapsed on the host | 7host_inst_rate 973862 # Simulator instruction rate (inst/s) 8host_op_rate 1054649 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1366418821 # Simulator tick rate (ticks/s) 10host_mem_usage 273224 # Number of bytes of host memory used 11host_seconds 518.54 # Real time elapsed on the host |
| 12sim_insts 504984064 # Number of instructions simulated 13sim_ops 546875315 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory --- 277 unchanged lines hidden (view full) --- 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 504984064 # Number of instructions simulated 13sim_ops 546875315 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory --- 277 unchanged lines hidden (view full) --- 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 305system.cpu.dcache.fast_writes 0 # number of fast writes performed 306system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 307system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks 308system.cpu.dcache.writebacks::total 1065708 # number of writebacks 309system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses 310system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses 311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses 312system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses --- 26 unchanged lines hidden (view full) --- 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency 342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency 346system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency 348system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency | 305system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks 306system.cpu.dcache.writebacks::total 1065708 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses 308system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses 309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses 310system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses 311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses --- 26 unchanged lines hidden (view full) --- 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency |
| 349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 350system.cpu.icache.tags.replacements 9788 # number of replacements 351system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use 352system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. 353system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 354system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. 355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor 357system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 402system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency 404system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 347system.cpu.icache.tags.replacements 9788 # number of replacements 348system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use 349system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. 350system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 351system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. 352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 353system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor 354system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 410system.cpu.icache.fast_writes 0 # number of fast writes performed 411system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 412system.cpu.icache.writebacks::writebacks 9788 # number of writebacks 413system.cpu.icache.writebacks::total 9788 # number of writebacks 414system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 415system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 416system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 417system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 418system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 419system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 430system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 431system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 432system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency 433system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency 434system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency 435system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency 436system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency 437system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency | 407system.cpu.icache.writebacks::writebacks 9788 # number of writebacks 408system.cpu.icache.writebacks::total 9788 # number of writebacks 409system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 410system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 411system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 412system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 413system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 414system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 426system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency |
| 438system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 439system.cpu.l2cache.tags.replacements 110394 # number of replacements 440system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use 441system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. 442system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. 443system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. 444system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. 445system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor 446system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor --- 91 unchanged lines hidden (view full) --- 538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency 539system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency 540system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 543system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 544system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 545system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 433system.cpu.l2cache.tags.replacements 110394 # number of replacements 434system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use 435system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. 436system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. 437system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. 438system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. 439system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor 440system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor --- 91 unchanged lines hidden (view full) --- 532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 546system.cpu.l2cache.fast_writes 0 # number of fast writes performed 547system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 548system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks 549system.cpu.l2cache.writebacks::total 96330 # number of writebacks 550system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses 551system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses 552system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses 553system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses 554system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses 555system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency 595system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency 596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency 597system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency 598system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency 599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency 600system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency 601system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency | 540system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks 541system.cpu.l2cache.writebacks::total 96330 # number of writebacks 542system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses 543system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses 544system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses 545system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses 546system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses 547system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency 587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency 588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency |
| 602system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 603system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. 604system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. 605system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 606system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. 607system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 608system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 609system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution --- 57 unchanged lines hidden --- | 594system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. 595system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. 596system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 597system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. 598system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 599system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 600system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution --- 57 unchanged lines hidden --- |