Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.708526 # Number of seconds simulated
4sim_ticks 708526400500 # Number of ticks simulated
5final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.708539 # Number of seconds simulated
4sim_ticks 708539449500 # Number of ticks simulated
5final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 942956 # Simulator instruction rate (inst/s)
8host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1323022561 # Simulator tick rate (ticks/s)
10host_mem_usage 320452 # Number of bytes of host memory used
11host_seconds 535.54 # Real time elapsed on the host
12sim_insts 504986854 # Number of instructions simulated
13sim_ops 546878105 # Number of ops (including micro ops) simulated

7host_inst_rate 318121 # Simulator instruction rate (inst/s)
8host_op_rate 344511 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 446353500 # Simulator tick rate (ticks/s)
10host_mem_usage 303968 # Number of bytes of host memory used
11host_seconds 1587.40 # Real time elapsed on the host
12sim_insts 504984064 # Number of instructions simulated
13sim_ops 546875315 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory

28system.physmem.bw_read::cpu.inst 208026 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 12651475 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 12859501 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 208026 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 208026 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 8701327 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8701327 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8701327 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 208026 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 12651475 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21560828 # Total bandwidth to/from this memory (bytes/s)

28system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)

39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 548 # Number of system calls

157system.cpu.numCycles 1417052801 # number of cpu cycles simulated

157system.cpu.numCycles 1417078899 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

160system.cpu.committedInsts 504986854 # Number of instructions committed
161system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses

160system.cpu.committedInsts 504984064 # Number of instructions committed
161system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses

163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 19311615 # number of times a function call or return occured

165system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
166system.cpu.num_int_insts 448454356 # number of integer instructions

165system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
166system.cpu.num_int_insts 448447005 # number of integer instructions

167system.cpu.num_fp_insts 16 # number of float instructions

168system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read
169system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written

168system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read
169system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written

170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written

172system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
174system.cpu.num_mem_refs 172745235 # number of memory refs
175system.cpu.num_load_insts 115884756 # Number of load instructions
176system.cpu.num_store_insts 56860479 # Number of store instructions

172system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
174system.cpu.num_mem_refs 172743505 # number of memory refs
175system.cpu.num_load_insts 115883283 # Number of load instructions
176system.cpu.num_store_insts 56860222 # Number of store instructions

177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 1417052800.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles

181system.cpu.Branches 121548302 # Number of branches fetched

181system.cpu.Branches 121552863 # Number of branches fetched

182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction

183system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction

183system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction

184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
187system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
188system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
189system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
190system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
191system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction

--- 12 unchanged lines hidden (view full) ---

204system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
205system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
206system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
207system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
208system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
209system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction

212system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
213system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction

212system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
213system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction

214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

216system.cpu.op_class::total 548695379 # Class of executed instruction
217system.cpu.dcache.tags.replacements 1134822 # number of replacements
218system.cpu.dcache.tags.tagsinuse 4065.260615 # Cycle average of tags in use
219system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.

216system.cpu.op_class::total 548692589 # Class of executed instruction
217system.cpu.dcache.tags.replacements 1136276 # number of replacements
218system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
219system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.

222system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.

223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.260615 # Average occupied blocks per requestor

223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor

224system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

233system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses
235system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits
236system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits
237system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
238system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits

233system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
235system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
236system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
237system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
238system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits

239system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
240system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
241system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
242system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
243system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
244system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits

245system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits
246system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits
247system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits
248system.cpu.dcache.overall_hits::total 167203374 # number of overall hits
249system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses
250system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses
251system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
252system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses

245system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits
246system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits
247system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits
248system.cpu.dcache.overall_hits::total 167200190 # number of overall hits
249system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses
250system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses
251system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses
252system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses

253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses

255system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses
256system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
257system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
258system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
259system.cpu.dcache.ReadReq_miss_latency::cpu.data 12104797500 # number of ReadReq miss cycles
260system.cpu.dcache.ReadReq_miss_latency::total 12104797500 # number of ReadReq miss cycles
261system.cpu.dcache.WriteReq_miss_latency::cpu.data 9574077500 # number of WriteReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::total 9574077500 # number of WriteReq miss cycles
263system.cpu.dcache.demand_miss_latency::cpu.data 21678875000 # number of demand (read+write) miss cycles
264system.cpu.dcache.demand_miss_latency::total 21678875000 # number of demand (read+write) miss cycles
265system.cpu.dcache.overall_miss_latency::cpu.data 21678875000 # number of overall miss cycles
266system.cpu.dcache.overall_miss_latency::total 21678875000 # number of overall miss cycles
267system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
268system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
269system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
270system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)

255system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses
256system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses
257system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses
258system.cpu.dcache.overall_misses::total 1140372 # number of overall misses
259system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
260system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
261system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
263system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
264system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
265system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
266system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
267system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses)
268system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses)
269system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
270system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)

271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
275system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
276system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)

277system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses
278system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses
279system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses
280system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses
281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses
282system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses
283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
284system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses

277system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses
278system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses
279system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses
280system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses
281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses
282system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses
283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses
284system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses

285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses

287system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses
288system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
289system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
290system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636 # average ReadReq miss latency
292system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636 # average ReadReq miss latency
293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155 # average WriteReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155 # average WriteReq miss latency
295system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925 # average overall miss latency
296system.cpu.dcache.demand_avg_miss_latency::total 19034.639925 # average overall miss latency
297system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::total 19034.623213 # average overall miss latency

287system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses
288system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses
289system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses
290system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses
291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
292system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
295system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
296system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
297system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency

299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305system.cpu.dcache.fast_writes 0 # number of fast writes performed
306system.cpu.dcache.cache_copies 0 # number of cache copies performed

307system.cpu.dcache.writebacks::writebacks 1064678 # number of writebacks
308system.cpu.dcache.writebacks::total 1064678 # number of writebacks
309system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses
310system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses
311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
312system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses

307system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
308system.cpu.dcache.writebacks::total 1065708 # number of writebacks
309system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
310system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses
311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses
312system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses

313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses

315system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses
316system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
317system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
318system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11322140500 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.ReadReq_mshr_miss_latency::total 11322140500 # number of ReadReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9217817500 # number of WriteReq MSHR miss cycles
322system.cpu.dcache.WriteReq_mshr_miss_latency::total 9217817500 # number of WriteReq MSHR miss cycles

315system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses
316system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses
317system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses
318system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses
319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles
322system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles

323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles

325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20539958000 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.demand_mshr_miss_latency::total 20539958000 # number of demand (read+write) MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20540019000 # number of overall MSHR miss cycles
328system.cpu.dcache.overall_mshr_miss_latency::total 20540019000 # number of overall MSHR miss cycles
329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses

325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles
328system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles
329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses
330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses
331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses
332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses

333system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses
334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses

335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses
336system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
338system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636 # average ReadReq mshr miss latency
340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636 # average ReadReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155 # average WriteReq mshr miss latency
342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155 # average WriteReq mshr miss latency

335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses
336system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses
337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses
338system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses
339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency
340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency

343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency

345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925 # average overall mshr miss latency
346system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650 # average overall mshr miss latency
348system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650 # average overall mshr miss latency

345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
346system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
348system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency

349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
350system.cpu.icache.tags.replacements 9788 # number of replacements

351system.cpu.icache.tags.tagsinuse 983.180611 # Cycle average of tags in use
352system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks.

351system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
352system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.

353system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.

354system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks.

354system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks.

355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

356system.cpu.icache.tags.occ_blocks::cpu.inst 983.180611 # Average occupied blocks per requestor
357system.cpu.icache.tags.occ_percent::cpu.inst 0.480069 # Average percentage of cache occupancy
358system.cpu.icache.tags.occ_percent::total 0.480069 # Average percentage of cache occupancy

356system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
357system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
358system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy

359system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
362system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
363system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
364system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
365system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id

366system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses
367system.cpu.icache.tags.data_accesses 1033234275 # Number of data accesses
368system.cpu.icache.ReadReq_hits::cpu.inst 516599856 # number of ReadReq hits
369system.cpu.icache.ReadReq_hits::total 516599856 # number of ReadReq hits
370system.cpu.icache.demand_hits::cpu.inst 516599856 # number of demand (read+write) hits
371system.cpu.icache.demand_hits::total 516599856 # number of demand (read+write) hits
372system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits
373system.cpu.icache.overall_hits::total 516599856 # number of overall hits

366system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
367system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
368system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
369system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
370system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
371system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits
372system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits
373system.cpu.icache.overall_hits::total 516597066 # number of overall hits

374system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
375system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
376system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
377system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
378system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
379system.cpu.icache.overall_misses::total 11521 # number of overall misses

380system.cpu.icache.ReadReq_miss_latency::cpu.inst 263208000 # number of ReadReq miss cycles
381system.cpu.icache.ReadReq_miss_latency::total 263208000 # number of ReadReq miss cycles
382system.cpu.icache.demand_miss_latency::cpu.inst 263208000 # number of demand (read+write) miss cycles
383system.cpu.icache.demand_miss_latency::total 263208000 # number of demand (read+write) miss cycles
384system.cpu.icache.overall_miss_latency::cpu.inst 263208000 # number of overall miss cycles
385system.cpu.icache.overall_miss_latency::total 263208000 # number of overall miss cycles
386system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses)
387system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses)
388system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses
389system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses
390system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses
391system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses

380system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles
381system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles
382system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles
383system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles
384system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles
385system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles
386system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses)
387system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses)
388system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses
389system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses
390system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses
391system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses

392system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
393system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
394system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
395system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
396system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
397system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses

398system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22845.933513 # average ReadReq miss latency
399system.cpu.icache.ReadReq_avg_miss_latency::total 22845.933513 # average ReadReq miss latency
400system.cpu.icache.demand_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency
401system.cpu.icache.demand_avg_miss_latency::total 22845.933513 # average overall miss latency
402system.cpu.icache.overall_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency
403system.cpu.icache.overall_avg_miss_latency::total 22845.933513 # average overall miss latency

398system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency
399system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency
400system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
401system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency
402system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
403system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency

404system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
405system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
406system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
407system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
408system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
409system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
410system.cpu.icache.fast_writes 0 # number of fast writes performed
411system.cpu.icache.cache_copies 0 # number of cache copies performed
412system.cpu.icache.writebacks::writebacks 9788 # number of writebacks
413system.cpu.icache.writebacks::total 9788 # number of writebacks
414system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
415system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
416system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
417system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
418system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
419system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses

420system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251687000 # number of ReadReq MSHR miss cycles
421system.cpu.icache.ReadReq_mshr_miss_latency::total 251687000 # number of ReadReq MSHR miss cycles
422system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251687000 # number of demand (read+write) MSHR miss cycles
423system.cpu.icache.demand_mshr_miss_latency::total 251687000 # number of demand (read+write) MSHR miss cycles
424system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251687000 # number of overall MSHR miss cycles
425system.cpu.icache.overall_mshr_miss_latency::total 251687000 # number of overall MSHR miss cycles

420system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles
421system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles
422system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles
423system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles
424system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles
425system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles

426system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
427system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
428system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
429system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
430system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
431system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses

432system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21845.933513 # average ReadReq mshr miss latency
433system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21845.933513 # average ReadReq mshr miss latency
434system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency
435system.cpu.icache.demand_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency
436system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency
437system.cpu.icache.overall_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency

432system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
433system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
434system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
435system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
436system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
437system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency

438system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
439system.cpu.l2cache.tags.replacements 110394 # number of replacements

440system.cpu.l2cache.tags.tagsinuse 27250.637055 # Cycle average of tags in use
441system.cpu.l2cache.tags.total_refs 1744409 # Total number of references to valid blocks.

440system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
441system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.

442system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.

443system.cpu.l2cache.tags.avg_refs 12.320839 # Average number of references to valid blocks.
444system.cpu.l2cache.tags.warmup_cycle 339114860000 # Cycle when the warmup percentage was hit.
445system.cpu.l2cache.tags.occ_blocks::writebacks 23374.350264 # Average occupied blocks per requestor
446system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.190674 # Average occupied blocks per requestor
447system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.096117 # Average occupied blocks per requestor
448system.cpu.l2cache.tags.occ_percent::writebacks 0.713329 # Average percentage of cache occupancy

443system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
444system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
445system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
446system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
447system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor
448system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy

449system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy

450system.cpu.l2cache.tags.occ_percent::cpu.data 0.110965 # Average percentage of cache occupancy
451system.cpu.l2cache.tags.occ_percent::total 0.831623 # Average percentage of cache occupancy

450system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy
451system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy

452system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
453system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
454system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
456system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
457system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id

458system.cpu.l2cache.tags.tag_accesses 18830546 # Number of tag accesses
459system.cpu.l2cache.tags.data_accesses 18830546 # Number of data accesses
460system.cpu.l2cache.WritebackDirty_hits::writebacks 1064678 # number of WritebackDirty hits
461system.cpu.l2cache.WritebackDirty_hits::total 1064678 # number of WritebackDirty hits

458system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
459system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
460system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
461system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits

462system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
463system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits

464system.cpu.l2cache.ReadExReq_hits::cpu.data 255472 # number of ReadExReq hits
465system.cpu.l2cache.ReadExReq_hits::total 255472 # number of ReadExReq hits

464system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
465system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits

466system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits
467system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits

468system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743385 # number of ReadSharedReq hits
469system.cpu.l2cache.ReadSharedReq_hits::total 743385 # number of ReadSharedReq hits

468system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits
469system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits

470system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits

471system.cpu.l2cache.demand_hits::cpu.data 998857 # number of demand (read+write) hits
472system.cpu.l2cache.demand_hits::total 1008075 # number of demand (read+write) hits

471system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits
472system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits

473system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits

474system.cpu.l2cache.overall_hits::cpu.data 998857 # number of overall hits
475system.cpu.l2cache.overall_hits::total 1008075 # number of overall hits

474system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits
475system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits

476system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses
477system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses
478system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses
479system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses
480system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses
481system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses
482system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses
483system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses
484system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses
485system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses
486system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses
487system.cpu.l2cache.overall_misses::total 142364 # number of overall misses

488system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000938500 # number of ReadExReq miss cycles
489system.cpu.l2cache.ReadExReq_miss_latency::total 6000938500 # number of ReadExReq miss cycles
490system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137230000 # number of ReadCleanReq miss cycles
491system.cpu.l2cache.ReadCleanReq_miss_latency::total 137230000 # number of ReadCleanReq miss cycles
492system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339453000 # number of ReadSharedReq miss cycles
493system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339453000 # number of ReadSharedReq miss cycles
494system.cpu.l2cache.demand_miss_latency::cpu.inst 137230000 # number of demand (read+write) miss cycles
495system.cpu.l2cache.demand_miss_latency::cpu.data 8340391500 # number of demand (read+write) miss cycles
496system.cpu.l2cache.demand_miss_latency::total 8477621500 # number of demand (read+write) miss cycles
497system.cpu.l2cache.overall_miss_latency::cpu.inst 137230000 # number of overall miss cycles
498system.cpu.l2cache.overall_miss_latency::cpu.data 8340391500 # number of overall miss cycles
499system.cpu.l2cache.overall_miss_latency::total 8477621500 # number of overall miss cycles
500system.cpu.l2cache.WritebackDirty_accesses::writebacks 1064678 # number of WritebackDirty accesses(hits+misses)
501system.cpu.l2cache.WritebackDirty_accesses::total 1064678 # number of WritebackDirty accesses(hits+misses)

488system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles
489system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles
490system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles
491system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles
492system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles
493system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles
494system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles
495system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles
496system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles
497system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles
498system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles
499system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles
500system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses)
501system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses)

502system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses)
503system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses)

504system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
505system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)

504system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses)
505system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses)

506system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses)
507system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses)

508system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 782658 # number of ReadSharedReq accesses(hits+misses)
509system.cpu.l2cache.ReadSharedReq_accesses::total 782658 # number of ReadSharedReq accesses(hits+misses)

508system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses)
509system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses)

510system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses

511system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
512system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses

511system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses
512system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses

513system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses

514system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
515system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
516system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282906 # miss rate for ReadExReq accesses
517system.cpu.l2cache.ReadExReq_miss_rate::total 0.282906 # miss rate for ReadExReq accesses

514system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses
515system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses
516system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses
517system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses

518system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses
519system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses

520system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050179 # miss rate for ReadSharedReq accesses
521system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050179 # miss rate for ReadSharedReq accesses

520system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses
521system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses

522system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses

523system.cpu.l2cache.demand_miss_rate::cpu.data 0.122977 # miss rate for demand accesses
524system.cpu.l2cache.demand_miss_rate::total 0.123748 # miss rate for demand accesses

523system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses
524system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses

525system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses

526system.cpu.l2cache.overall_miss_rate::cpu.data 0.122977 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::total 0.123748 # miss rate for overall accesses
528system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.208160 # average ReadExReq miss latency
529system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.208160 # average ReadExReq miss latency
530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59587.494572 # average ReadCleanReq miss latency
531system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59587.494572 # average ReadCleanReq miss latency
532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59568.991419 # average ReadSharedReq miss latency
533system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59568.991419 # average ReadSharedReq miss latency
534system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency
535system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency
536system.cpu.l2cache.demand_avg_miss_latency::total 59548.913349 # average overall miss latency
537system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency
539system.cpu.l2cache.overall_avg_miss_latency::total 59548.913349 # average overall miss latency

526system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses
528system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency
529system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency
530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency
531system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency
532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency
533system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency
534system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
535system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
536system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency
537system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
539system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency

540system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
541system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
542system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
543system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
544system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
545system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
546system.cpu.l2cache.fast_writes 0 # number of fast writes performed
547system.cpu.l2cache.cache_copies 0 # number of cache copies performed

--- 8 unchanged lines hidden (view full) ---

556system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses
557system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses
558system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses
559system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses
560system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses
561system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses
562system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses
563system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses

564system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993058500 # number of ReadExReq MSHR miss cycles
565system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993058500 # number of ReadExReq MSHR miss cycles
566system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114200000 # number of ReadCleanReq MSHR miss cycles
567system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114200000 # number of ReadCleanReq MSHR miss cycles
568system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946723000 # number of ReadSharedReq MSHR miss cycles
569system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946723000 # number of ReadSharedReq MSHR miss cycles
570system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114200000 # number of demand (read+write) MSHR miss cycles
571system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939781500 # number of demand (read+write) MSHR miss cycles
572system.cpu.l2cache.demand_mshr_miss_latency::total 7053981500 # number of demand (read+write) MSHR miss cycles
573system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114200000 # number of overall MSHR miss cycles
574system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939781500 # number of overall MSHR miss cycles
575system.cpu.l2cache.overall_mshr_miss_latency::total 7053981500 # number of overall MSHR miss cycles

564system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles
565system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles
566system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles
567system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles
568system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles
569system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles
570system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles
571system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles
572system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles
573system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles
574system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles
575system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles

576system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
577system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

578system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282906 # mshr miss rate for ReadExReq accesses
579system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282906 # mshr miss rate for ReadExReq accesses

578system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
579system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses

580system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses
581system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses

582system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050179 # mshr miss rate for ReadSharedReq accesses
583system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050179 # mshr miss rate for ReadSharedReq accesses

582system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
583system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses

584system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses

585system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses
586system.cpu.l2cache.demand_mshr_miss_rate::total 0.123748 # mshr miss rate for demand accesses

585system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
586system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses

587system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses

588system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses
589system.cpu.l2cache.overall_mshr_miss_rate::total 0.123748 # mshr miss rate for overall accesses
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160 # average ReadExReq mshr miss latency
591system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160 # average ReadExReq mshr miss latency
592system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572 # average ReadCleanReq mshr miss latency
593system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572 # average ReadCleanReq mshr miss latency
594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419 # average ReadSharedReq mshr miss latency
595system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419 # average ReadSharedReq mshr miss latency
596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency
597system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency
598system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency
599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency
600system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency
601system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency

588system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
589system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
591system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
592system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
593system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
595system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
597system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
598system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
600system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
601system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency

602system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

603system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter.
604system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
605system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

603system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
604system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
605system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

606system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
607system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
608system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

609system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution

609system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution

611system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution

612system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution
613system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
614system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution

612system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
613system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
614system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution

615system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution

616system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution

616system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution

617system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes)

618system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes)
619system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes)

618system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes)
619system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes)

620system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes)

621system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes)
622system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes)

621system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
622system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)

623system.cpu.toL2Bus.snoops 110394 # Total snoops (count)

624system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram
625system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram
626system.cpu.toL2Bus.snoop_fanout::stdev 0.066862 # Request fanout histogram

624system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
625system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
626system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram

627system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

628system.cpu.toL2Bus.snoop_fanout::0 1255174 99.55% 99.55% # Request fanout histogram
629system.cpu.toL2Bus.snoop_fanout::1 5658 0.45% 100.00% # Request fanout histogram

628system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
629system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram

630system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
631system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
633system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

634system.cpu.toL2Bus.snoop_fanout::total 1260833 # Request fanout histogram
635system.cpu.toL2Bus.reqLayer0.occupancy 2221990500 # Layer occupancy (ticks)

634system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
635system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)

636system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
637system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
638system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

639system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)

639system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)

640system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
641system.membus.trans_dist::ReadResp 41576 # Transaction distribution
642system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
643system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
644system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
645system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
646system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
647system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)

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654system.membus.snoop_fanout::stdev 0 # Request fanout histogram
655system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
656system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
657system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
658system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
659system.membus.snoop_fanout::min_value 0 # Request fanout histogram
660system.membus.snoop_fanout::max_value 0 # Request fanout histogram
661system.membus.snoop_fanout::total 250615 # Request fanout histogram

662system.membus.reqLayer0.occupancy 644475328 # Layer occupancy (ticks)

662system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)