| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.707533 # Number of seconds simulated 4sim_ticks 707533448500 # Number of ticks simulated 5final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.707537 # Number of seconds simulated 4sim_ticks 707536959500 # Number of ticks simulated 5final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1147583 # Simulator instruction rate (inst/s) 8host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1607870578 # Simulator tick rate (ticks/s) 10host_mem_usage 316160 # Number of bytes of host memory used 11host_seconds 440.04 # Real time elapsed on the host | 7host_inst_rate 1064510 # Simulator instruction rate (inst/s) 8host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1491485099 # Simulator tick rate (ticks/s) 10host_mem_usage 319084 # Number of bytes of host memory used 11host_seconds 474.38 # Real time elapsed on the host |
| 12sim_insts 504986854 # Number of instructions simulated 13sim_ops 546878105 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 175360 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8946752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9122112 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 175360 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 175360 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6146048 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6146048 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2740 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 139793 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory | 12sim_insts 504986854 # Number of instructions simulated 13sim_ops 546878105 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 175360 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8946752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9122112 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 175360 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 175360 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6146048 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6146048 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2740 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 139793 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory |
| 28system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s) | 28system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s) |
| 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 548 # Number of system calls | 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 548 # Number of system calls |
| 157system.cpu.numCycles 1415066897 # number of cpu cycles simulated | 157system.cpu.numCycles 1415073919 # number of cpu cycles simulated |
| 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 504986854 # Number of instructions committed 161system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 164system.cpu.num_func_calls 19311615 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written 174system.cpu.num_mem_refs 172745235 # number of memory refs 175system.cpu.num_load_insts 115884756 # Number of load instructions 176system.cpu.num_store_insts 56860479 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 504986854 # Number of instructions committed 161system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 164system.cpu.num_func_calls 19311615 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written 174system.cpu.num_mem_refs 172745235 # number of memory refs 175system.cpu.num_load_insts 115884756 # Number of load instructions 176system.cpu.num_store_insts 56860479 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 178system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles | 178system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles |
| 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 121548302 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction 184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 212system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction 213system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 548695379 # Class of executed instruction 217system.cpu.dcache.tags.replacements 1134822 # number of replacements | 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 121548302 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction 184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 212system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction 213system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 548695379 # Class of executed instruction 217system.cpu.dcache.tags.replacements 1134822 # number of replacements |
| 218system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use | 218system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use |
| 219system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. | 219system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. |
| 222system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor | 222system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor |
| 224system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id --- 19 unchanged lines hidden (view full) --- 251system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 255system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses 256system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses 257system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 258system.cpu.dcache.overall_misses::total 1138918 # number of overall misses | 224system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id --- 19 unchanged lines hidden (view full) --- 251system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 255system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses 256system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses 257system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 258system.cpu.dcache.overall_misses::total 1138918 # number of overall misses |
| 259system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles 260system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles | 259system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles 260system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles |
| 261system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles 262system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles | 261system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles 262system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles |
| 263system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles 264system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles 265system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles 266system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles | 263system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles 264system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles 265system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles 266system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles |
| 267system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 284system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses 286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses | 267system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 284system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses 286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses |
| 291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency 292system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency | 291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency 292system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency |
| 293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency 294system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency | 293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency 294system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency |
| 295system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency 296system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency | 295system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency 296system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency |
| 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu.dcache.fast_writes 0 # number of fast writes performed 306system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 312system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 315system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses 316system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses 317system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 318system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses | 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu.dcache.fast_writes 0 # number of fast writes performed 306system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 312system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 315system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses 316system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses 317system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 318system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses |
| 319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles 320system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles | 319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles 320system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles |
| 321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles 322system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles 323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles 324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles | 321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles 322system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles 323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles 324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles |
| 325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles 326system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles 327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles 328system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles | 325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles 326system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles 327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles 328system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles |
| 329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 333system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses 334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses 335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses 336system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses 337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses 338system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses | 329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 333system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses 334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses 335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses 336system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses 337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses 338system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses |
| 339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency 340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency | 339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency 340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency |
| 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency 342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency 344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency | 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency 342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency 344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency |
| 345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency 346system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency 348system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency | 345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency 346system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency 348system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency |
| 349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 350system.cpu.icache.tags.replacements 9788 # number of replacements | 349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 350system.cpu.icache.tags.replacements 9788 # number of replacements |
| 351system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use | 351system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use |
| 352system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. 353system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 354system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. 355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 352system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. 353system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 354system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. 355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 356system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor 357system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy 358system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy | 356system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor 357system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy 358system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy |
| 359system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 365system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 366system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 372system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits 373system.cpu.icache.overall_hits::total 516599856 # number of overall hits 374system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 375system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 376system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 377system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 378system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 379system.cpu.icache.overall_misses::total 11521 # number of overall misses | 359system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 365system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 366system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 372system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits 373system.cpu.icache.overall_hits::total 516599856 # number of overall hits 374system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 375system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 376system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 377system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 378system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 379system.cpu.icache.overall_misses::total 11521 # number of overall misses |
| 380system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles 381system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles 382system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles 383system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles 384system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles 385system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles | 380system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles 381system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles 382system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles 383system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles 384system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles 385system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles |
| 386system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) 387system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) 388system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses 389system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses 390system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses 391system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses 392system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 393system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 394system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 395system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 396system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 397system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses | 386system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) 387system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) 388system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses 389system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses 390system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses 391system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses 392system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 393system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 394system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 395system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 396system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 397system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses |
| 398system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency 399system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency 400system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency 401system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency 402system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency | 398system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency 399system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency 400system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency 401system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency 402system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency |
| 404system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 410system.cpu.icache.fast_writes 0 # number of fast writes performed 411system.cpu.icache.cache_copies 0 # number of cache copies performed 412system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 413system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 414system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 415system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 416system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 417system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses | 404system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 410system.cpu.icache.fast_writes 0 # number of fast writes performed 411system.cpu.icache.cache_copies 0 # number of cache copies performed 412system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 413system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 414system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 415system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 416system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 417system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses |
| 418system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles 419system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles 423system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles | 418system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles 419system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles 423system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles |
| 424system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 425system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 426system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 427system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 428system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 429system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses | 424system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 425system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 426system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 427system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 428system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 429system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses |
| 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency | 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency |
| 436system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 437system.cpu.l2cache.tags.replacements 109779 # number of replacements | 436system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 437system.cpu.l2cache.tags.replacements 109779 # number of replacements |
| 438system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use | 438system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use |
| 439system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. 440system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. 441system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. | 439system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. 440system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. 441system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. |
| 442system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit. 443system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor | 442system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit. 443system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor |
| 446system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy | 446system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy |
| 448system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy | 448system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy |
| 450system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27180 # Occupied blocks per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 18829920 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 18829920 # Number of data accesses --- 22 unchanged lines hidden (view full) --- 480system.cpu.l2cache.demand_misses::total 142533 # number of demand (read+write) misses 481system.cpu.l2cache.overall_misses::cpu.inst 2740 # number of overall misses 482system.cpu.l2cache.overall_misses::cpu.data 139793 # number of overall misses 483system.cpu.l2cache.overall_misses::total 142533 # number of overall misses 484system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 # number of ReadExReq miss cycles 485system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles 486system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles 487system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles | 450system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27180 # Occupied blocks per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 18829920 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 18829920 # Number of data accesses --- 22 unchanged lines hidden (view full) --- 480system.cpu.l2cache.demand_misses::total 142533 # number of demand (read+write) misses 481system.cpu.l2cache.overall_misses::cpu.inst 2740 # number of overall misses 482system.cpu.l2cache.overall_misses::cpu.data 139793 # number of overall misses 483system.cpu.l2cache.overall_misses::total 142533 # number of overall misses 484system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 # number of ReadExReq miss cycles 485system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles 486system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles 487system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles |
| 488system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles 489system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles | 488system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles 489system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles |
| 490system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles | 490system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles |
| 491system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles 492system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles | 491system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles 492system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles |
| 493system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles | 493system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles |
| 494system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles 495system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles | 494system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles 495system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles |
| 496system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) 497system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) 501system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) 502system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 782658 # number of ReadSharedReq accesses(hits+misses) 503system.cpu.l2cache.ReadSharedReq_accesses::total 782658 # number of ReadSharedReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 518system.cpu.l2cache.demand_miss_rate::total 0.123894 # miss rate for demand accesses 519system.cpu.l2cache.overall_miss_rate::cpu.inst 0.237827 # miss rate for overall accesses 520system.cpu.l2cache.overall_miss_rate::cpu.data 0.122742 # miss rate for overall accesses 521system.cpu.l2cache.overall_miss_rate::total 0.123894 # miss rate for overall accesses 522system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 # average ReadExReq miss latency 523system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency 524system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency 525system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency | 496system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) 497system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) 501system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) 502system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 782658 # number of ReadSharedReq accesses(hits+misses) 503system.cpu.l2cache.ReadSharedReq_accesses::total 782658 # number of ReadSharedReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 518system.cpu.l2cache.demand_miss_rate::total 0.123894 # miss rate for demand accesses 519system.cpu.l2cache.overall_miss_rate::cpu.inst 0.237827 # miss rate for overall accesses 520system.cpu.l2cache.overall_miss_rate::cpu.data 0.122742 # miss rate for overall accesses 521system.cpu.l2cache.overall_miss_rate::total 0.123894 # miss rate for overall accesses 522system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 # average ReadExReq miss latency 523system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency 524system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency 525system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency |
| 526system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency 527system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency | 526system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency 527system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency |
| 528system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency | 528system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency |
| 529system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency 530system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency | 529system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency 530system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency |
| 531system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency | 531system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency |
| 532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency | 532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency |
| 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.l2cache.fast_writes 0 # number of fast writes performed 541system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 554system.cpu.l2cache.demand_mshr_misses::total 142533 # number of demand (read+write) MSHR misses 555system.cpu.l2cache.overall_mshr_misses::cpu.inst 2740 # number of overall MSHR misses 556system.cpu.l2cache.overall_mshr_misses::cpu.data 139793 # number of overall MSHR misses 557system.cpu.l2cache.overall_mshr_misses::total 142533 # number of overall MSHR misses 558system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 # number of ReadExReq MSHR miss cycles 559system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles 560system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles 561system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles | 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.l2cache.fast_writes 0 # number of fast writes performed 541system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 554system.cpu.l2cache.demand_mshr_misses::total 142533 # number of demand (read+write) MSHR misses 555system.cpu.l2cache.overall_mshr_misses::cpu.inst 2740 # number of overall MSHR misses 556system.cpu.l2cache.overall_mshr_misses::cpu.data 139793 # number of overall MSHR misses 557system.cpu.l2cache.overall_mshr_misses::total 142533 # number of overall MSHR misses 558system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 # number of ReadExReq MSHR miss cycles 559system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles 560system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles 561system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles |
| 562system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles 563system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles | 562system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles 563system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles |
| 564system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles | 564system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles |
| 565system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles 566system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles | 565system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles 566system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles |
| 567system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles | 567system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles |
| 568system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles 569system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles | 568system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles 569system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles |
| 570system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 571system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 572system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses 573system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282751 # mshr miss rate for ReadExReq accesses 574system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for ReadCleanReq accesses 575system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237827 # mshr miss rate for ReadCleanReq accesses 576system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.049907 # mshr miss rate for ReadSharedReq accesses 577system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.049907 # mshr miss rate for ReadSharedReq accesses 578system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for demand accesses 579system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for demand accesses 580system.cpu.l2cache.demand_mshr_miss_rate::total 0.123894 # mshr miss rate for demand accesses 581system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for overall accesses 582system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for overall accesses 583system.cpu.l2cache.overall_mshr_miss_rate::total 0.123894 # mshr miss rate for overall accesses 584system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 # average ReadExReq mshr miss latency 585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency 586system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency 587system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency | 570system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 571system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 572system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses 573system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282751 # mshr miss rate for ReadExReq accesses 574system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for ReadCleanReq accesses 575system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237827 # mshr miss rate for ReadCleanReq accesses 576system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.049907 # mshr miss rate for ReadSharedReq accesses 577system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.049907 # mshr miss rate for ReadSharedReq accesses 578system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for demand accesses 579system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for demand accesses 580system.cpu.l2cache.demand_mshr_miss_rate::total 0.123894 # mshr miss rate for demand accesses 581system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for overall accesses 582system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for overall accesses 583system.cpu.l2cache.overall_mshr_miss_rate::total 0.123894 # mshr miss rate for overall accesses 584system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 # average ReadExReq mshr miss latency 585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency 586system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency 587system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency |
| 588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency 589system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency | 588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency 589system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency |
| 590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency | 590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency |
| 591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency | 591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency |
| 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency | 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency |
| 594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency 595system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency | 594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency 595system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency |
| 596system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 596system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 597system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. 598system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. 599system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 600system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter. 601system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 602system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 597system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution 600system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution 604system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) 605system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) 606system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) 607system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) 608system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141043072 # Cumulative packet size per connected master and slave (bytes) 609system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) 610system.cpu.toL2Bus.snoops 109779 # Total snoops (count) 611system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram | 603system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution 610system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) 614system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141043072 # Cumulative packet size per connected master and slave (bytes) 615system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) 616system.cpu.toL2Bus.snoops 109779 # Total snoops (count) 617system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram |
| 612system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram 613system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram | 618system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram |
| 614system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 620system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 615system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 616system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram | 621system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram |
| 618system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 624system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 619system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 625system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 620system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram 622system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) 623system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 624system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 625system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 626system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) 627system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) --- 13 unchanged lines hidden (view full) --- 641system.membus.snoop_fanout::stdev 0 # Request fanout histogram 642system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 643system.membus.snoop_fanout::0 251058 100.00% 100.00% # Request fanout histogram 644system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 645system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 646system.membus.snoop_fanout::min_value 0 # Request fanout histogram 647system.membus.snoop_fanout::max_value 0 # Request fanout histogram 648system.membus.snoop_fanout::total 251058 # Request fanout histogram | 626system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram 628system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) 629system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 630system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 631system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 632system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) 633system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) --- 13 unchanged lines hidden (view full) --- 647system.membus.snoop_fanout::stdev 0 # Request fanout histogram 648system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 649system.membus.snoop_fanout::0 251058 100.00% 100.00% # Request fanout histogram 650system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 651system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 652system.membus.snoop_fanout::min_value 0 # Request fanout histogram 653system.membus.snoop_fanout::max_value 0 # Request fanout histogram 654system.membus.snoop_fanout::total 251058 # Request fanout histogram |
| 649system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks) | 655system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks) |
| 650system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 656system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 651system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks) | 657system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks) |
| 652system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 653 654---------- End Simulation Statistics ---------- | 658system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 659 660---------- End Simulation Statistics ---------- |