Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.707539 # Number of seconds simulated
4sim_ticks 707539023000 # Number of ticks simulated
5final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.707538 # Number of seconds simulated
4sim_ticks 707538046500 # Number of ticks simulated
5final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1166033 # Simulator instruction rate (inst/s)
8host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1633733414 # Simulator tick rate (ticks/s)
10host_mem_usage 312880 # Number of bytes of host memory used
11host_seconds 433.08 # Real time elapsed on the host

7host_inst_rate 1058036 # Simulator instruction rate (inst/s)
8host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1482416058 # Simulator tick rate (ticks/s)
10host_mem_usage 313032 # Number of bytes of host memory used
11host_seconds 477.29 # Real time elapsed on the host

12sim_insts 504986853 # Number of instructions simulated
13sim_ops 546878104 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s)

31system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s)

33system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)

33system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s)

36system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s)

39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 548 # Number of system calls

157system.cpu.numCycles 1415078046 # number of cpu cycles simulated

157system.cpu.numCycles 1415076093 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 504986853 # Number of instructions committed
161system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 19311615 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
174system.cpu.num_mem_refs 172745235 # number of memory refs
175system.cpu.num_load_insts 115884756 # Number of load instructions
176system.cpu.num_store_insts 56860479 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 121548301 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction
184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction

--- 23 unchanged lines hidden (view full) ---

210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
212system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
213system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 548695378 # Class of executed instruction
217system.cpu.dcache.tags.replacements 1134822 # number of replacements

218system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use

218system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use

219system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.

222system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor

222system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor

224system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id

--- 19 unchanged lines hidden (view full) ---

251system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
252system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
255system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses
256system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
257system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
258system.cpu.dcache.overall_misses::total 1138918 # number of overall misses

259system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles
260system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles
261system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles
263system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles
264system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles
265system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles
266system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles

259system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles
260system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles
261system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles
263system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles
264system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles
265system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles
266system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles

267system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
268system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
269system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
270system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
284system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
287system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses
288system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
289system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
290system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses

291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency
292system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency
293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency
295system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency
296system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency
297system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency

291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency
292system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency
293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency
295system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency
296system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency
297system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency

299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305system.cpu.dcache.fast_writes 0 # number of fast writes performed
306system.cpu.dcache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
312system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
315system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses
316system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
317system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
318system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses

319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles
322system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles
323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles
328system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles

319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles
322system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles
323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles
328system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles

329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
333system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses
334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses
335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses
336system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
338system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses

339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency
340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency
342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
346system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
348system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency

339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency
340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency
342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency
343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency
346system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency
348system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency

349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
350system.cpu.icache.tags.replacements 9788 # number of replacements

351system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use

351system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use

352system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
353system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
354system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

356system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor

356system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor

357system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
358system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
359system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
362system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
363system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
364system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id

--- 7 unchanged lines hidden (view full) ---

372system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits
373system.cpu.icache.overall_hits::total 516599855 # number of overall hits
374system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
375system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
376system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
377system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
378system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
379system.cpu.icache.overall_misses::total 11521 # number of overall misses

380system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles
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434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
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434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency
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442system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit.
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444system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904965 # Average occupied blocks per requestor
445system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.493984 # Average occupied blocks per requestor

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450system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
451system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id
454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id
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456system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses
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--- 5 unchanged lines hidden (view full) ---

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572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency
573system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency
574system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency
575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency
576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
578system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
579system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
581system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency

582system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
583system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
584system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
585system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
586system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
587system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
588system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
589system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
590system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
591system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
592system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
593system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
594system.cpu.toL2Bus.snoops 0 # Total snoops (count)
595system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram

596system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram

596system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram

597system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
598system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
599system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
600system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram

602system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
603system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
604system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram
605system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram

602system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram
603system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram

606system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

604system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

607system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
608system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram

605system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
606system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

609system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
610system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
611system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
612system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
613system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
614system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
615system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
616system.membus.trans_dist::ReadReq 41855 # Transaction distribution

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628system.membus.snoop_fanout::stdev 0 # Request fanout histogram
629system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
630system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram
631system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
632system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
633system.membus.snoop_fanout::min_value 0 # Request fanout histogram
634system.membus.snoop_fanout::max_value 0 # Request fanout histogram
635system.membus.snoop_fanout::total 238603 # Request fanout histogram

607system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
608system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
609system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
610system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
611system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
612system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
613system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
614system.membus.trans_dist::ReadReq 41855 # Transaction distribution

--- 11 unchanged lines hidden (view full) ---

626system.membus.snoop_fanout::stdev 0 # Request fanout histogram
627system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
628system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram
629system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
630system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
631system.membus.snoop_fanout::min_value 0 # Request fanout histogram
632system.membus.snoop_fanout::max_value 0 # Request fanout histogram
633system.membus.snoop_fanout::total 238603 # Request fanout histogram

636system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)

634system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks)

637system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

635system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

638system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
639system.membus.respLayer1.utilization 0.2 # Layer utilization (%)

636system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks)
637system.membus.respLayer1.utilization 0.1 # Layer utilization (%)