7,11c7,13
< host_inst_rate 1518630 # Simulator instruction rate (inst/s)
< host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
< host_mem_usage 222536 # Number of bytes of host memory used
< host_seconds 374.70 # Real time elapsed on the host
< sim_insts 569034848 # Number of instructions simulated
---
> host_inst_rate 1769028 # Simulator instruction rate (inst/s)
> host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2530070907 # Simulator tick rate (ticks/s)
> host_mem_usage 225284 # Number of bytes of host memory used
> host_seconds 285.46 # Real time elapsed on the host
> sim_insts 504986861 # Number of instructions simulated
> sim_ops 569034848 # Number of ops (including micro ops) simulated
68c70,71
< system.cpu.num_insts 569034848 # Number of instructions executed
---
> system.cpu.committedInsts 504986861 # Number of instructions committed
> system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed
92,111c95,127
< system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
< system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
< system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
< system.cpu.icache.overall_hits 516599864 # number of overall hits
< system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
< system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
< system.cpu.icache.overall_misses 11521 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
---
> system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits
> system.cpu.icache.overall_hits::total 516599864 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
> system.cpu.icache.overall_misses::total 11521 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
120,139c136,153
< system.cpu.icache.writebacks 0 # number of writebacks
< system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
< system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
< system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
< system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
147,176c161,211
< system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
< system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits 176840705 # number of overall hits
< system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
< system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses 1138918 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
---
> system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits
> system.cpu.dcache.overall_hits::total 176840705 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
> system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
185,208c220,245
< system.cpu.dcache.writebacks 1025440 # number of writebacks
< system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
< system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
< system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
---
> system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks
> system.cpu.dcache.writebacks::total 1025440 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
216,245c253,321
< system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
< system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
< system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits 919235 # number of overall hits
< system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses 231204 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
---
> system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits
> system.cpu.l2cache.overall_hits::total 919235 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses
> system.cpu.l2cache.overall_misses::total 231204 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
254,277c330,367
< system.cpu.l2cache.writebacks 172302 # number of writebacks
< system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
< system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
< system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
---
> system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
> system.cpu.l2cache.writebacks::total 172302 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< host_inst_rate 1518630 # Simulator instruction rate (inst/s)
< host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
< host_mem_usage 222536 # Number of bytes of host memory used
< host_seconds 374.70 # Real time elapsed on the host
< sim_insts 569034848 # Number of instructions simulated
---
> host_inst_rate 1769028 # Simulator instruction rate (inst/s)
> host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2530070907 # Simulator tick rate (ticks/s)
> host_mem_usage 225284 # Number of bytes of host memory used
> host_seconds 285.46 # Real time elapsed on the host
> sim_insts 504986861 # Number of instructions simulated
> sim_ops 569034848 # Number of ops (including micro ops) simulated
68c70,71
< system.cpu.num_insts 569034848 # Number of instructions executed
---
> system.cpu.committedInsts 504986861 # Number of instructions committed
> system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed
92,111c95,127
< system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
< system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
< system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
< system.cpu.icache.overall_hits 516599864 # number of overall hits
< system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
< system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
< system.cpu.icache.overall_misses 11521 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
---
> system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits
> system.cpu.icache.overall_hits::total 516599864 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
> system.cpu.icache.overall_misses::total 11521 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
120,139c136,153
< system.cpu.icache.writebacks 0 # number of writebacks
< system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
< system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
< system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
< system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
147,176c161,211
< system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
< system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits 176840705 # number of overall hits
< system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
< system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses 1138918 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
---
> system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits
> system.cpu.dcache.overall_hits::total 176840705 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
> system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
185,208c220,245
< system.cpu.dcache.writebacks 1025440 # number of writebacks
< system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
< system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
< system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
---
> system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks
> system.cpu.dcache.writebacks::total 1025440 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
216,245c253,321
< system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
< system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
< system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits 919235 # number of overall hits
< system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses 231204 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
---
> system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits
> system.cpu.l2cache.overall_hits::total 919235 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses
> system.cpu.l2cache.overall_misses::total 231204 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
254,277c330,367
< system.cpu.l2cache.writebacks 172302 # number of writebacks
< system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
< system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
< system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
---
> system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
> system.cpu.l2cache.writebacks::total 172302 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency