3,5c3,5
< sim_seconds 0.708539 # Number of seconds simulated
< sim_ticks 708539449500 # Number of ticks simulated
< final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.708700 # Number of seconds simulated
> sim_ticks 708700329500 # Number of ticks simulated
> final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 665557 # Simulator instruction rate (inst/s)
< host_op_rate 720769 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 933837970 # Simulator tick rate (ticks/s)
< host_mem_usage 269828 # Number of bytes of host memory used
< host_seconds 758.74 # Real time elapsed on the host
---
> host_inst_rate 820539 # Simulator instruction rate (inst/s)
> host_op_rate 888607 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1151553403 # Simulator tick rate (ticks/s)
> host_mem_usage 275232 # Number of bytes of host memory used
> host_seconds 615.43 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory
25,40c25,40
< system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
72c72
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
102c102
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
132c132
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
163,164c163,164
< system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1417078899 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1417400659 # number of cpu cycles simulated
185c185
< system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles
224c224
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
226c226
< system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use
230,233c230,233
< system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy
243c243
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
268,275c268,275
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles
300,307c300,307
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency
314,315c314,315
< system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
< system.cpu.dcache.writebacks::total 1065708 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks
> system.cpu.dcache.writebacks::total 1065429 # number of writebacks
326,335c326,335
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles
346,356c346,356
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
358c358
< system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use
363,365c363,365
< system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy
375c375
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
388,393c388,393
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles
406,411c406,411
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency
426,431c426,431
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles
438,468c438,468
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 110394 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 110813 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits
471,472c471,472
< system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits
475,476c475,476
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits
478,479c478,479
< system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits
481,484c481,484
< system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses
---
> system.cpu.l2cache.overall_hits::cpu.data 999933 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1009151 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 100833 # number of ReadExReq misses
487,488c487,488
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 39606 # number of ReadSharedReq misses
490,491c490,491
< system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses
493,508c493,508
< system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses
< system.cpu.l2cache.overall_misses::total 142364 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses
> system.cpu.l2cache.overall_misses::total 142742 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses)
523,524c523,524
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses
527,528c527,528
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses
530,531c530,531
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses
533,546c533,546
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency
553,554c553,554
< system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
< system.cpu.l2cache.writebacks::total 96330 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks
> system.cpu.l2cache.writebacks::total 96648 # number of writebacks
557,558c557,558
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses
561,562c561,562
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses
564,565c564,565
< system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 142742 # number of demand (read+write) MSHR misses
567,580c567,580
< system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles
583,584c583,584
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses
587,588c587,588
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses
590,591c590,591
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses
593,606c593,606
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency
610,611c610,611
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
613c613
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
615c615
< system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution
617c617
< system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution
626,632c626,632
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 6165120 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 110813 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram
634,635c634,635
< system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram
640,641c640,641
< system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks)
647,657c647,663
< system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 41576 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
< system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
< system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
< system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 41909 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution
> system.membus.trans_dist::CleanEvict 12014 # Transaction distribution
> system.membus.trans_dist::ReadExReq 100833 # Transaction distribution
> system.membus.trans_dist::ReadExResp 100833 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes)
660c666
< system.membus.snoop_fanout::samples 250615 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 142743 # Request fanout histogram
664c670
< system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram
669,670c675,676
< system.membus.snoop_fanout::total 250615 # Request fanout histogram
< system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 142743 # Request fanout histogram
> system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks)
672c678
< system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks)
< sim_seconds 0.708539 # Number of seconds simulated
< sim_ticks 708539449500 # Number of ticks simulated
< final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.708700 # Number of seconds simulated
> sim_ticks 708700329500 # Number of ticks simulated
> final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 665557 # Simulator instruction rate (inst/s)
< host_op_rate 720769 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 933837970 # Simulator tick rate (ticks/s)
< host_mem_usage 269828 # Number of bytes of host memory used
< host_seconds 758.74 # Real time elapsed on the host
---
> host_inst_rate 820539 # Simulator instruction rate (inst/s)
> host_op_rate 888607 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1151553403 # Simulator tick rate (ticks/s)
> host_mem_usage 275232 # Number of bytes of host memory used
> host_seconds 615.43 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory
25,40c25,40
< system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
72c72
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
102c102
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
132c132
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
163,164c163,164
< system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1417078899 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1417400659 # number of cpu cycles simulated
185c185
< system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles
224c224
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
226c226
< system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use
230,233c230,233
< system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy
243c243
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
268,275c268,275
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles
300,307c300,307
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency
314,315c314,315
< system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
< system.cpu.dcache.writebacks::total 1065708 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks
> system.cpu.dcache.writebacks::total 1065429 # number of writebacks
326,335c326,335
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles
346,356c346,356
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
358c358
< system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use
363,365c363,365
< system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy
375c375
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
388,393c388,393
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles
406,411c406,411
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency
426,431c426,431
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles
438,468c438,468
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 110394 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 110813 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits
471,472c471,472
< system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits
475,476c475,476
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits
478,479c478,479
< system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits
481,484c481,484
< system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses
---
> system.cpu.l2cache.overall_hits::cpu.data 999933 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1009151 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 100833 # number of ReadExReq misses
487,488c487,488
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 39606 # number of ReadSharedReq misses
490,491c490,491
< system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses
493,508c493,508
< system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses
< system.cpu.l2cache.overall_misses::total 142364 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses
> system.cpu.l2cache.overall_misses::total 142742 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses)
523,524c523,524
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses
527,528c527,528
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses
530,531c530,531
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses
533,546c533,546
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency
553,554c553,554
< system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
< system.cpu.l2cache.writebacks::total 96330 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks
> system.cpu.l2cache.writebacks::total 96648 # number of writebacks
557,558c557,558
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses
561,562c561,562
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses
564,565c564,565
< system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 142742 # number of demand (read+write) MSHR misses
567,580c567,580
< system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles
583,584c583,584
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses
587,588c587,588
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses
590,591c590,591
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses
593,606c593,606
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency
610,611c610,611
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
613c613
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
615c615
< system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution
617c617
< system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution
626,632c626,632
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 6165120 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 110813 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram
634,635c634,635
< system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram
640,641c640,641
< system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks)
647,657c647,663
< system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 41576 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
< system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
< system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
< system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 41909 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution
> system.membus.trans_dist::CleanEvict 12014 # Transaction distribution
> system.membus.trans_dist::ReadExReq 100833 # Transaction distribution
> system.membus.trans_dist::ReadExResp 100833 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes)
660c666
< system.membus.snoop_fanout::samples 250615 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 142743 # Request fanout histogram
664c670
< system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram
669,670c675,676
< system.membus.snoop_fanout::total 250615 # Request fanout histogram
< system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 142743 # Request fanout histogram
> system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks)
672c678
< system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks)