3,5c3,5
< sim_seconds 0.707533 # Number of seconds simulated
< sim_ticks 707533448500 # Number of ticks simulated
< final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.707537 # Number of seconds simulated
> sim_ticks 707536959500 # Number of ticks simulated
> final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1147583 # Simulator instruction rate (inst/s)
< host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1607870578 # Simulator tick rate (ticks/s)
< host_mem_usage 316160 # Number of bytes of host memory used
< host_seconds 440.04 # Real time elapsed on the host
---
> host_inst_rate 1064510 # Simulator instruction rate (inst/s)
> host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1491485099 # Simulator tick rate (ticks/s)
> host_mem_usage 319084 # Number of bytes of host memory used
> host_seconds 474.38 # Real time elapsed on the host
28,38c28,38
< system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 1415066897 # number of cpu cycles simulated
---
> system.cpu.numCycles 1415073919 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor
259,260c259,260
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles
263,266c263,266
< system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles
291,292c291,292
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency
295,298c295,298
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency
319,320c319,320
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles
325,328c325,328
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles
339,340c339,340
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency
345,348c345,348
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency
351c351
< system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use
356,358c356,358
< system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
380,385c380,385
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles
398,403c398,403
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency
418,423c418,423
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles
430,435c430,435
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
438c438
< system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use
442,445c442,445
< system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor
448,449c448,449
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy
488,489c488,489
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles
491,492c491,492
< system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles
494,495c494,495
< system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles
526,527c526,527
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency
529,530c529,530
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency
532,533c532,533
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency
562,563c562,563
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles
565,566c565,566
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles
568,569c568,569
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles
588,589c588,589
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency
591,592c591,592
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
594,595c594,595
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
596a597,602
> system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
612,613c618,619
< system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram
615,617c621,623
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
619c625
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
649c655
< system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks)
651c657
< system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks)
< sim_seconds 0.707533 # Number of seconds simulated
< sim_ticks 707533448500 # Number of ticks simulated
< final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.707537 # Number of seconds simulated
> sim_ticks 707536959500 # Number of ticks simulated
> final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1147583 # Simulator instruction rate (inst/s)
< host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1607870578 # Simulator tick rate (ticks/s)
< host_mem_usage 316160 # Number of bytes of host memory used
< host_seconds 440.04 # Real time elapsed on the host
---
> host_inst_rate 1064510 # Simulator instruction rate (inst/s)
> host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1491485099 # Simulator tick rate (ticks/s)
> host_mem_usage 319084 # Number of bytes of host memory used
> host_seconds 474.38 # Real time elapsed on the host
28,38c28,38
< system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 1415066897 # number of cpu cycles simulated
---
> system.cpu.numCycles 1415073919 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor
259,260c259,260
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles
263,266c263,266
< system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles
291,292c291,292
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency
295,298c295,298
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency
319,320c319,320
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles
325,328c325,328
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles
339,340c339,340
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency
345,348c345,348
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency
351c351
< system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use
356,358c356,358
< system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
380,385c380,385
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles
398,403c398,403
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency
418,423c418,423
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles
430,435c430,435
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
438c438
< system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use
442,445c442,445
< system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor
448,449c448,449
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy
488,489c488,489
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles
491,492c491,492
< system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles
494,495c494,495
< system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles
526,527c526,527
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency
529,530c529,530
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency
532,533c532,533
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency
562,563c562,563
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles
565,566c565,566
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles
568,569c568,569
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles
588,589c588,589
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency
591,592c591,592
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
594,595c594,595
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
596a597,602
> system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
612,613c618,619
< system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram
615,617c621,623
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
619c625
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
649c655
< system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks)
651c657
< system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks)