3,5c3,5
< sim_seconds 0.707539 # Number of seconds simulated
< sim_ticks 707539023000 # Number of ticks simulated
< final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.707538 # Number of seconds simulated
> sim_ticks 707538046500 # Number of ticks simulated
> final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1166033 # Simulator instruction rate (inst/s)
< host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1633733414 # Simulator tick rate (ticks/s)
< host_mem_usage 312880 # Number of bytes of host memory used
< host_seconds 433.08 # Real time elapsed on the host
---
> host_inst_rate 1058036 # Simulator instruction rate (inst/s)
> host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1482416058 # Simulator tick rate (ticks/s)
> host_mem_usage 313032 # Number of bytes of host memory used
> host_seconds 477.29 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 1415078046 # number of cpu cycles simulated
---
> system.cpu.numCycles 1415076093 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor
259,266c259,266
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles
291,298c291,298
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency
319,328c319,328
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles
339,348c339,348
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency
351c351
< system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use
356c356
< system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor
380,385c380,385
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 266293500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 266293500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 266293500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 266293500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 266293500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 266293500 # number of overall miss cycles
398,403c398,403
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 23113.748807 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 23113.748807 # average overall miss latency
418,423c418,423
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249012000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 249012000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249012000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 249012000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249012000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 249012000 # number of overall MSHR miss cycles
430,435c430,435
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21613.748807 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21613.748807 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency
438c438
< system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 27249.388139 # Cycle average of tags in use
442,445c442,445
< system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 338494304500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989190 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904965 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.493984 # Average occupied blocks per requestor
449c449
< system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy
482,492c482,492
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145605500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054496500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 145605500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7350225500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 145605500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7350225500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles
517,527c517,527
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.162455 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.833056 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency
549,559c549,559
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112218500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583343000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112218500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665507000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112218500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665507000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles
571,581c571,581
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
596c596
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
602,605c602,603
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
607,608c605,606
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
636c634
< system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks)
638,639c636,637
< system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
< sim_seconds 0.707539 # Number of seconds simulated
< sim_ticks 707539023000 # Number of ticks simulated
< final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.707538 # Number of seconds simulated
> sim_ticks 707538046500 # Number of ticks simulated
> final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1166033 # Simulator instruction rate (inst/s)
< host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1633733414 # Simulator tick rate (ticks/s)
< host_mem_usage 312880 # Number of bytes of host memory used
< host_seconds 433.08 # Real time elapsed on the host
---
> host_inst_rate 1058036 # Simulator instruction rate (inst/s)
> host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1482416058 # Simulator tick rate (ticks/s)
> host_mem_usage 313032 # Number of bytes of host memory used
> host_seconds 477.29 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 1415078046 # number of cpu cycles simulated
---
> system.cpu.numCycles 1415076093 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor
259,266c259,266
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles
291,298c291,298
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency
319,328c319,328
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles
339,348c339,348
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency
351c351
< system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use
356c356
< system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor
380,385c380,385
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 266293500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 266293500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 266293500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 266293500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 266293500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 266293500 # number of overall miss cycles
398,403c398,403
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 23113.748807 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 23113.748807 # average overall miss latency
418,423c418,423
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249012000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 249012000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249012000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 249012000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249012000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 249012000 # number of overall MSHR miss cycles
430,435c430,435
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21613.748807 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21613.748807 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency
438c438
< system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 27249.388139 # Cycle average of tags in use
442,445c442,445
< system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 338494304500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989190 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904965 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.493984 # Average occupied blocks per requestor
449c449
< system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy
482,492c482,492
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145605500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054496500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 145605500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7350225500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 145605500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7350225500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles
517,527c517,527
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.162455 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.833056 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency
549,559c549,559
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112218500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583343000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112218500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665507000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112218500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665507000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles
571,581c571,581
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
596c596
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
602,605c602,603
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
607,608c605,606
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
636c634
< system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks)
638,639c636,637
< system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.1 # Layer utilization (%)