Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt

stats.txt (10812:bacaefeb126a)	stats.txt (10827:7f5467f2f8b8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.707538 # Number of seconds simulated 4sim_ticks 707538047500 # Number of ticks simulated 5final_tick 707538047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 813114 # Simulator instruction rate (inst/s) 8host_op_rate 880566 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1139256199 # Simulator tick rate (ticks/s) 10host_mem_usage 308656 # Number of bytes of host memory used 11host_seconds 621.05 # Real time elapsed on the host 12sim_insts 504986854 # Number of instructions simulated 13sim_ops 546878105 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 177216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8952320 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 177216 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 177216 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2769 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 139880 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 250469 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12652775 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 250469 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 250469 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 250469 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12652775 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 548 # Number of system calls 157system.cpu.numCycles 1415076095 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 504986854 # Number of instructions committed 161system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 164system.cpu.num_func_calls 19311615 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls 166system.cpu.num_int_insts 448454356 # number of integer instructions 167system.cpu.num_fp_insts 16 # number of float instructions 168system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read 169system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written 174system.cpu.num_mem_refs 172745235 # number of memory refs 175system.cpu.num_load_insts 115884756 # Number of load instructions 176system.cpu.num_store_insts 56860479 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 1415076094.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 121548302 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction 184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 212system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction 213system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 548695379 # Class of executed instruction 217system.cpu.dcache.tags.replacements 1134822 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4065.318385 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 11716394000 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318385 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 239system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits 240system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits 241system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 242system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 243system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 244system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 245system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits 246system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits 247system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits 248system.cpu.dcache.overall_hits::total 167203374 # number of overall hits 249system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses 250system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses 251system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 255system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses 256system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses 257system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 258system.cpu.dcache.overall_misses::total 1138918 # number of overall misses 259system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818699500 # number of ReadReq miss cycles 260system.cpu.dcache.ReadReq_miss_latency::total 11818699500 # number of ReadReq miss cycles 261system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles 262system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles 263system.cpu.dcache.demand_miss_latency::cpu.data 20687471500 # number of demand (read+write) miss cycles 264system.cpu.dcache.demand_miss_latency::total 20687471500 # number of demand (read+write) miss cycles 265system.cpu.dcache.overall_miss_latency::cpu.data 20687471500 # number of overall miss cycles 266system.cpu.dcache.overall_miss_latency::total 20687471500 # number of overall miss cycles 267system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 275system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 276system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 277system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses 278system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses 279system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses 280system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses 281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses 282system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses 283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 284system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses 286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses 291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532 # average ReadReq miss latency 292system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532 # average ReadReq miss latency 293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency 294system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency 295system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777 # average overall miss latency 296system.cpu.dcache.demand_avg_miss_latency::total 18164.160777 # average overall miss latency 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 18164.144829 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu.dcache.fast_writes 0 # number of fast writes performed 306system.cpu.dcache.cache_copies 0 # number of cache copies performed 307system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks 308system.cpu.dcache.writebacks::total 1064905 # number of writebacks 309system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses 310system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses 311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 312system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 315system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses 316system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses 317system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 318system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses 319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644714000 # number of ReadReq MSHR miss cycles 320system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644714000 # number of ReadReq MSHR miss cycles 321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles 322system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles 323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles 324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles 325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979096000 # number of demand (read+write) MSHR miss cycles 326system.cpu.dcache.demand_mshr_miss_latency::total 18979096000 # number of demand (read+write) MSHR miss cycles 327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979149500 # number of overall MSHR miss cycles 328system.cpu.dcache.overall_mshr_miss_latency::total 18979149500 # number of overall MSHR miss cycles 329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 333system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses 334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses 335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses 336system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses 337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses 338system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses 339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.739532 # average ReadReq mshr miss latency 340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.739532 # average ReadReq mshr miss latency 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency 342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency 344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.160777 # average overall mshr miss latency 346system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.160777 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120 # average overall mshr miss latency 348system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.193120 # average overall mshr miss latency 349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 350system.cpu.icache.tags.replacements 9788 # number of replacements 351system.cpu.icache.tags.tagsinuse 983.372130 # Cycle average of tags in use 352system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. 353system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 354system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. 355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.icache.tags.occ_blocks::cpu.inst 983.372130 # Average occupied blocks per requestor 357system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy 358system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy 359system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 365system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 366system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses 367system.cpu.icache.tags.data_accesses 1033234275 # Number of data accesses 368system.cpu.icache.ReadReq_hits::cpu.inst 516599856 # number of ReadReq hits 369system.cpu.icache.ReadReq_hits::total 516599856 # number of ReadReq hits 370system.cpu.icache.demand_hits::cpu.inst 516599856 # number of demand (read+write) hits 371system.cpu.icache.demand_hits::total 516599856 # number of demand (read+write) hits 372system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits 373system.cpu.icache.overall_hits::total 516599856 # number of overall hits 374system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 375system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 376system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 377system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 378system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 379system.cpu.icache.overall_misses::total 11521 # number of overall misses 380system.cpu.icache.ReadReq_miss_latency::cpu.inst 266251500 # number of ReadReq miss cycles 381system.cpu.icache.ReadReq_miss_latency::total 266251500 # number of ReadReq miss cycles 382system.cpu.icache.demand_miss_latency::cpu.inst 266251500 # number of demand (read+write) miss cycles 383system.cpu.icache.demand_miss_latency::total 266251500 # number of demand (read+write) miss cycles 384system.cpu.icache.overall_miss_latency::cpu.inst 266251500 # number of overall miss cycles 385system.cpu.icache.overall_miss_latency::total 266251500 # number of overall miss cycles 386system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) 387system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) 388system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses 389system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses 390system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses 391system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses 392system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 393system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 394system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 395system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 396system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 397system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses 398system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23110.103290 # average ReadReq miss latency 399system.cpu.icache.ReadReq_avg_miss_latency::total 23110.103290 # average ReadReq miss latency 400system.cpu.icache.demand_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency 401system.cpu.icache.demand_avg_miss_latency::total 23110.103290 # average overall miss latency 402system.cpu.icache.overall_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::total 23110.103290 # average overall miss latency 404system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 410system.cpu.icache.fast_writes 0 # number of fast writes performed 411system.cpu.icache.cache_copies 0 # number of cache copies performed 412system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 413system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 414system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 415system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 416system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 417system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 418system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 248970000 # number of ReadReq MSHR miss cycles 419system.cpu.icache.ReadReq_mshr_miss_latency::total 248970000 # number of ReadReq MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::cpu.inst 248970000 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.demand_mshr_miss_latency::total 248970000 # number of demand (read+write) MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::cpu.inst 248970000 # number of overall MSHR miss cycles 423system.cpu.icache.overall_mshr_miss_latency::total 248970000 # number of overall MSHR miss cycles 424system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 425system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 426system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 427system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 428system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 429system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21610.103290 # average ReadReq mshr miss latency 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21610.103290 # average ReadReq mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency 436system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 437system.cpu.l2cache.tags.replacements 109895 # number of replacements 438system.cpu.l2cache.tags.tagsinuse 27249.388101 # Cycle average of tags in use 439system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. 440system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. 441system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. 442system.cpu.l2cache.tags.warmup_cycle 338494305500 # Cycle when the warmup percentage was hit. 443system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989157 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.672992 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.725951 # Average occupied blocks per requestor 446system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008779 # Average percentage of cache occupancy 448system.cpu.l2cache.tags.occ_percent::cpu.data 0.109092 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy 450system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses 458system.cpu.l2cache.ReadReq_hits::cpu.inst 8752 # number of ReadReq hits 459system.cpu.l2cache.ReadReq_hits::cpu.data 743572 # number of ReadReq hits 460system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits 461system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits 462system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits 463system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits 464system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits 465system.cpu.l2cache.demand_hits::cpu.inst 8752 # number of demand (read+write) hits 466system.cpu.l2cache.demand_hits::cpu.data 999038 # number of demand (read+write) hits 467system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits 468system.cpu.l2cache.overall_hits::cpu.inst 8752 # number of overall hits 469system.cpu.l2cache.overall_hits::cpu.data 999038 # number of overall hits 470system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits 471system.cpu.l2cache.ReadReq_misses::cpu.inst 2769 # number of ReadReq misses 472system.cpu.l2cache.ReadReq_misses::cpu.data 39086 # number of ReadReq misses 473system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses 474system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses 475system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses 476system.cpu.l2cache.demand_misses::cpu.inst 2769 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::cpu.data 139880 # number of demand (read+write) misses 478system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses 479system.cpu.l2cache.overall_misses::cpu.inst 2769 # number of overall misses 480system.cpu.l2cache.overall_misses::cpu.data 139880 # number of overall misses 481system.cpu.l2cache.overall_misses::total 142649 # number of overall misses 482system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145553000 # number of ReadReq miss cycles 483system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054549000 # number of ReadReq miss cycles 484system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles 485system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles 486system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles 487system.cpu.l2cache.demand_miss_latency::cpu.inst 145553000 # number of demand (read+write) miss cycles 488system.cpu.l2cache.demand_miss_latency::cpu.data 7350278000 # number of demand (read+write) miss cycles 489system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles 490system.cpu.l2cache.overall_miss_latency::cpu.inst 145553000 # number of overall miss cycles 491system.cpu.l2cache.overall_miss_latency::cpu.data 7350278000 # number of overall miss cycles 492system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles 493system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 494system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 495system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) 496system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses) 497system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 501system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 502system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 503system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 504system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 505system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses 506system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240344 # miss rate for ReadReq accesses 507system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049940 # miss rate for ReadReq accesses 508system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses 509system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses 510system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses 511system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240344 # miss rate for demand accesses 512system.cpu.l2cache.demand_miss_rate::cpu.data 0.122818 # miss rate for demand accesses 513system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses 514system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240344 # miss rate for overall accesses 515system.cpu.l2cache.overall_miss_rate::cpu.data 0.122818 # miss rate for overall accesses 516system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses 517system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.185988 # average ReadReq miss latency 518system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.831397 # average ReadReq miss latency 519system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency 520system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency 521system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency 522system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.185988 # average overall miss latency 523system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026022 # average overall miss latency 524system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency 525system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.185988 # average overall miss latency 526system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026022 # average overall miss latency 527system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency 528system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 531system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 532system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 533system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 534system.cpu.l2cache.fast_writes 0 # number of fast writes performed 535system.cpu.l2cache.cache_copies 0 # number of cache copies performed 536system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks 537system.cpu.l2cache.writebacks::total 95953 # number of writebacks 538system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2769 # number of ReadReq MSHR misses 539system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39086 # number of ReadReq MSHR misses 540system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses 541system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses 542system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses 543system.cpu.l2cache.demand_mshr_misses::cpu.inst 2769 # number of demand (read+write) MSHR misses 544system.cpu.l2cache.demand_mshr_misses::cpu.data 139880 # number of demand (read+write) MSHR misses 545system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses 546system.cpu.l2cache.overall_mshr_misses::cpu.inst 2769 # number of overall MSHR misses 547system.cpu.l2cache.overall_mshr_misses::cpu.data 139880 # number of overall MSHR misses 548system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses 549system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112178000 # number of ReadReq MSHR miss cycles 550system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583383500 # number of ReadReq MSHR miss cycles 551system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles 552system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles 553system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles 554system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112178000 # number of demand (read+write) MSHR miss cycles 555system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665547500 # number of demand (read+write) MSHR miss cycles 556system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles 557system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112178000 # number of overall MSHR miss cycles 558system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665547500 # number of overall MSHR miss cycles 559system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles 560system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for ReadReq accesses 561system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049940 # mshr miss rate for ReadReq accesses 562system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses 563system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses 564system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses 565system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for demand accesses 566system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for demand accesses 567system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses 568system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for overall accesses 569system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for overall accesses 570system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636 # average ReadReq mshr miss latency 573system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency 574system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency 575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency 576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency 577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency 578system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency 579system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency 580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency 581system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency 582system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 583system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution 586system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution 587system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution 588system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) 591system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) 593system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) 594system.cpu.toL2Bus.snoops 0 # Total snoops (count) 595system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.707538 # Number of seconds simulated 4sim_ticks 707538047500 # Number of ticks simulated 5final_tick 707538047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 813114 # Simulator instruction rate (inst/s) 8host_op_rate 880566 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1139256199 # Simulator tick rate (ticks/s) 10host_mem_usage 308656 # Number of bytes of host memory used 11host_seconds 621.05 # Real time elapsed on the host 12sim_insts 504986854 # Number of instructions simulated 13sim_ops 546878105 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 177216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8952320 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 177216 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 177216 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2769 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 139880 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 250469 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12652775 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 250469 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 250469 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 250469 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12652775 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 548 # Number of system calls 157system.cpu.numCycles 1415076095 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 504986854 # Number of instructions committed 161system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 164system.cpu.num_func_calls 19311615 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls 166system.cpu.num_int_insts 448454356 # number of integer instructions 167system.cpu.num_fp_insts 16 # number of float instructions 168system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read 169system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written 174system.cpu.num_mem_refs 172745235 # number of memory refs 175system.cpu.num_load_insts 115884756 # Number of load instructions 176system.cpu.num_store_insts 56860479 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 1415076094.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 121548302 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction 184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 212system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction 213system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 548695379 # Class of executed instruction 217system.cpu.dcache.tags.replacements 1134822 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4065.318385 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 11716394000 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318385 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 239system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits 240system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits 241system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 242system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 243system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 244system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 245system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits 246system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits 247system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits 248system.cpu.dcache.overall_hits::total 167203374 # number of overall hits 249system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses 250system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses 251system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 255system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses 256system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses 257system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 258system.cpu.dcache.overall_misses::total 1138918 # number of overall misses 259system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818699500 # number of ReadReq miss cycles 260system.cpu.dcache.ReadReq_miss_latency::total 11818699500 # number of ReadReq miss cycles 261system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles 262system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles 263system.cpu.dcache.demand_miss_latency::cpu.data 20687471500 # number of demand (read+write) miss cycles 264system.cpu.dcache.demand_miss_latency::total 20687471500 # number of demand (read+write) miss cycles 265system.cpu.dcache.overall_miss_latency::cpu.data 20687471500 # number of overall miss cycles 266system.cpu.dcache.overall_miss_latency::total 20687471500 # number of overall miss cycles 267system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 275system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 276system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 277system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses 278system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses 279system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses 280system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses 281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses 282system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses 283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 284system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses 286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses 291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532 # average ReadReq miss latency 292system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532 # average ReadReq miss latency 293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency 294system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency 295system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777 # average overall miss latency 296system.cpu.dcache.demand_avg_miss_latency::total 18164.160777 # average overall miss latency 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 18164.144829 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu.dcache.fast_writes 0 # number of fast writes performed 306system.cpu.dcache.cache_copies 0 # number of cache copies performed 307system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks 308system.cpu.dcache.writebacks::total 1064905 # number of writebacks 309system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses 310system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses 311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 312system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 315system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses 316system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses 317system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 318system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses 319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644714000 # number of ReadReq MSHR miss cycles 320system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644714000 # number of ReadReq MSHR miss cycles 321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles 322system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles 323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles 324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles 325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979096000 # number of demand (read+write) MSHR miss cycles 326system.cpu.dcache.demand_mshr_miss_latency::total 18979096000 # number of demand (read+write) MSHR miss cycles 327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979149500 # number of overall MSHR miss cycles 328system.cpu.dcache.overall_mshr_miss_latency::total 18979149500 # number of overall MSHR miss cycles 329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 333system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses 334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses 335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses 336system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses 337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses 338system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses 339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.739532 # average ReadReq mshr miss latency 340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.739532 # average ReadReq mshr miss latency 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency 342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency 344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.160777 # average overall mshr miss latency 346system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.160777 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120 # average overall mshr miss latency 348system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.193120 # average overall mshr miss latency 349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 350system.cpu.icache.tags.replacements 9788 # number of replacements 351system.cpu.icache.tags.tagsinuse 983.372130 # Cycle average of tags in use 352system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. 353system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 354system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. 355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.icache.tags.occ_blocks::cpu.inst 983.372130 # Average occupied blocks per requestor 357system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy 358system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy 359system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 365system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 366system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses 367system.cpu.icache.tags.data_accesses 1033234275 # Number of data accesses 368system.cpu.icache.ReadReq_hits::cpu.inst 516599856 # number of ReadReq hits 369system.cpu.icache.ReadReq_hits::total 516599856 # number of ReadReq hits 370system.cpu.icache.demand_hits::cpu.inst 516599856 # number of demand (read+write) hits 371system.cpu.icache.demand_hits::total 516599856 # number of demand (read+write) hits 372system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits 373system.cpu.icache.overall_hits::total 516599856 # number of overall hits 374system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 375system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 376system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 377system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 378system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 379system.cpu.icache.overall_misses::total 11521 # number of overall misses 380system.cpu.icache.ReadReq_miss_latency::cpu.inst 266251500 # number of ReadReq miss cycles 381system.cpu.icache.ReadReq_miss_latency::total 266251500 # number of ReadReq miss cycles 382system.cpu.icache.demand_miss_latency::cpu.inst 266251500 # number of demand (read+write) miss cycles 383system.cpu.icache.demand_miss_latency::total 266251500 # number of demand (read+write) miss cycles 384system.cpu.icache.overall_miss_latency::cpu.inst 266251500 # number of overall miss cycles 385system.cpu.icache.overall_miss_latency::total 266251500 # number of overall miss cycles 386system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) 387system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) 388system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses 389system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses 390system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses 391system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses 392system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 393system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 394system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 395system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 396system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 397system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses 398system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23110.103290 # average ReadReq miss latency 399system.cpu.icache.ReadReq_avg_miss_latency::total 23110.103290 # average ReadReq miss latency 400system.cpu.icache.demand_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency 401system.cpu.icache.demand_avg_miss_latency::total 23110.103290 # average overall miss latency 402system.cpu.icache.overall_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::total 23110.103290 # average overall miss latency 404system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 410system.cpu.icache.fast_writes 0 # number of fast writes performed 411system.cpu.icache.cache_copies 0 # number of cache copies performed 412system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 413system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 414system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 415system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 416system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 417system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 418system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 248970000 # number of ReadReq MSHR miss cycles 419system.cpu.icache.ReadReq_mshr_miss_latency::total 248970000 # number of ReadReq MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::cpu.inst 248970000 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.demand_mshr_miss_latency::total 248970000 # number of demand (read+write) MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::cpu.inst 248970000 # number of overall MSHR miss cycles 423system.cpu.icache.overall_mshr_miss_latency::total 248970000 # number of overall MSHR miss cycles 424system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 425system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 426system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 427system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 428system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 429system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21610.103290 # average ReadReq mshr miss latency 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21610.103290 # average ReadReq mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency 436system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 437system.cpu.l2cache.tags.replacements 109895 # number of replacements 438system.cpu.l2cache.tags.tagsinuse 27249.388101 # Cycle average of tags in use 439system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. 440system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. 441system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. 442system.cpu.l2cache.tags.warmup_cycle 338494305500 # Cycle when the warmup percentage was hit. 443system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989157 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.672992 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.725951 # Average occupied blocks per requestor 446system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008779 # Average percentage of cache occupancy 448system.cpu.l2cache.tags.occ_percent::cpu.data 0.109092 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy 450system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses 458system.cpu.l2cache.ReadReq_hits::cpu.inst 8752 # number of ReadReq hits 459system.cpu.l2cache.ReadReq_hits::cpu.data 743572 # number of ReadReq hits 460system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits 461system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits 462system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits 463system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits 464system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits 465system.cpu.l2cache.demand_hits::cpu.inst 8752 # number of demand (read+write) hits 466system.cpu.l2cache.demand_hits::cpu.data 999038 # number of demand (read+write) hits 467system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits 468system.cpu.l2cache.overall_hits::cpu.inst 8752 # number of overall hits 469system.cpu.l2cache.overall_hits::cpu.data 999038 # number of overall hits 470system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits 471system.cpu.l2cache.ReadReq_misses::cpu.inst 2769 # number of ReadReq misses 472system.cpu.l2cache.ReadReq_misses::cpu.data 39086 # number of ReadReq misses 473system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses 474system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses 475system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses 476system.cpu.l2cache.demand_misses::cpu.inst 2769 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::cpu.data 139880 # number of demand (read+write) misses 478system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses 479system.cpu.l2cache.overall_misses::cpu.inst 2769 # number of overall misses 480system.cpu.l2cache.overall_misses::cpu.data 139880 # number of overall misses 481system.cpu.l2cache.overall_misses::total 142649 # number of overall misses 482system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145553000 # number of ReadReq miss cycles 483system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054549000 # number of ReadReq miss cycles 484system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles 485system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles 486system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles 487system.cpu.l2cache.demand_miss_latency::cpu.inst 145553000 # number of demand (read+write) miss cycles 488system.cpu.l2cache.demand_miss_latency::cpu.data 7350278000 # number of demand (read+write) miss cycles 489system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles 490system.cpu.l2cache.overall_miss_latency::cpu.inst 145553000 # number of overall miss cycles 491system.cpu.l2cache.overall_miss_latency::cpu.data 7350278000 # number of overall miss cycles 492system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles 493system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 494system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 495system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) 496system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses) 497system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 501system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 502system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 503system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 504system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 505system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses 506system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240344 # miss rate for ReadReq accesses 507system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049940 # miss rate for ReadReq accesses 508system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses 509system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses 510system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses 511system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240344 # miss rate for demand accesses 512system.cpu.l2cache.demand_miss_rate::cpu.data 0.122818 # miss rate for demand accesses 513system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses 514system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240344 # miss rate for overall accesses 515system.cpu.l2cache.overall_miss_rate::cpu.data 0.122818 # miss rate for overall accesses 516system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses 517system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.185988 # average ReadReq miss latency 518system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.831397 # average ReadReq miss latency 519system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency 520system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency 521system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency 522system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.185988 # average overall miss latency 523system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026022 # average overall miss latency 524system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency 525system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.185988 # average overall miss latency 526system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026022 # average overall miss latency 527system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency 528system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 531system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 532system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 533system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 534system.cpu.l2cache.fast_writes 0 # number of fast writes performed 535system.cpu.l2cache.cache_copies 0 # number of cache copies performed 536system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks 537system.cpu.l2cache.writebacks::total 95953 # number of writebacks 538system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2769 # number of ReadReq MSHR misses 539system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39086 # number of ReadReq MSHR misses 540system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses 541system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses 542system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses 543system.cpu.l2cache.demand_mshr_misses::cpu.inst 2769 # number of demand (read+write) MSHR misses 544system.cpu.l2cache.demand_mshr_misses::cpu.data 139880 # number of demand (read+write) MSHR misses 545system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses 546system.cpu.l2cache.overall_mshr_misses::cpu.inst 2769 # number of overall MSHR misses 547system.cpu.l2cache.overall_mshr_misses::cpu.data 139880 # number of overall MSHR misses 548system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses 549system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112178000 # number of ReadReq MSHR miss cycles 550system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583383500 # number of ReadReq MSHR miss cycles 551system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles 552system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles 553system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles 554system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112178000 # number of demand (read+write) MSHR miss cycles 555system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665547500 # number of demand (read+write) MSHR miss cycles 556system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles 557system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112178000 # number of overall MSHR miss cycles 558system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665547500 # number of overall MSHR miss cycles 559system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles 560system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for ReadReq accesses 561system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049940 # mshr miss rate for ReadReq accesses 562system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses 563system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses 564system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses 565system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for demand accesses 566system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for demand accesses 567system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses 568system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for overall accesses 569system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for overall accesses 570system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636 # average ReadReq mshr miss latency 573system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency 574system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency 575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency 576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency 577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency 578system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency 579system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency 580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency 581system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency 582system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 583system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution 586system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution 587system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution 588system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) 591system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) 593system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) 594system.cpu.toL2Bus.snoops 0 # Total snoops (count) 595system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
596system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram	596system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
597system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram	597system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
600system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 602system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram	600system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
604system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	602system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
605system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram	603system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
607system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram 608system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) 609system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 610system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 611system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 612system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) 613system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 614system.membus.trans_dist::ReadReq 41855 # Transaction distribution 615system.membus.trans_dist::ReadResp 41855 # Transaction distribution 616system.membus.trans_dist::Writeback 95953 # Transaction distribution 617system.membus.trans_dist::ReadExReq 100794 # Transaction distribution 618system.membus.trans_dist::ReadExResp 100794 # Transaction distribution 619system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) 620system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) 621system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) 622system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) 623system.membus.snoops 0 # Total snoops (count) 624system.membus.snoop_fanout::samples 238603 # Request fanout histogram 625system.membus.snoop_fanout::mean 0 # Request fanout histogram 626system.membus.snoop_fanout::stdev 0 # Request fanout histogram 627system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 628system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram 629system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 630system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 631system.membus.snoop_fanout::min_value 0 # Request fanout histogram 632system.membus.snoop_fanout::max_value 0 # Request fanout histogram 633system.membus.snoop_fanout::total 238603 # Request fanout histogram 634system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks) 635system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 636system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks) 637system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 638 639---------- End Simulation Statistics ----------	605system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram 606system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) 607system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 608system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 609system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 610system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) 611system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 612system.membus.trans_dist::ReadReq 41855 # Transaction distribution 613system.membus.trans_dist::ReadResp 41855 # Transaction distribution 614system.membus.trans_dist::Writeback 95953 # Transaction distribution 615system.membus.trans_dist::ReadExReq 100794 # Transaction distribution 616system.membus.trans_dist::ReadExResp 100794 # Transaction distribution 617system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) 618system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) 619system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) 620system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) 621system.membus.snoops 0 # Total snoops (count) 622system.membus.snoop_fanout::samples 238603 # Request fanout histogram 623system.membus.snoop_fanout::mean 0 # Request fanout histogram 624system.membus.snoop_fanout::stdev 0 # Request fanout histogram 625system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 626system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram 627system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 628system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 629system.membus.snoop_fanout::min_value 0 # Request fanout histogram 630system.membus.snoop_fanout::max_value 0 # Request fanout histogram 631system.membus.snoop_fanout::total 238603 # Request fanout histogram 632system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks) 633system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 634system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks) 635system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 636 637---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.707538 # Number of seconds simulated
4sim_ticks 707538047500 # Number of ticks simulated
5final_tick 707538047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 813114 # Simulator instruction rate (inst/s)
8host_op_rate 880566 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1139256199 # Simulator tick rate (ticks/s)
10host_mem_usage 308656 # Number of bytes of host memory used
11host_seconds 621.05 # Real time elapsed on the host
12sim_insts 504986854 # Number of instructions simulated
13sim_ops 546878105 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 177216 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8952320 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 177216 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 177216 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2769 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 139880 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 250469 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 12652775 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 250469 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 250469 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 250469 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 12652775 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s)
39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
69system.cpu.dtb.walker.walks 0 # Table walker walks requested
70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
77system.cpu.dtb.inst_hits 0 # ITB inst hits
78system.cpu.dtb.inst_misses 0 # ITB inst misses
79system.cpu.dtb.read_hits 0 # DTB read hits
80system.cpu.dtb.read_misses 0 # DTB read misses
81system.cpu.dtb.write_hits 0 # DTB write hits
82system.cpu.dtb.write_misses 0 # DTB write misses
83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92system.cpu.dtb.read_accesses 0 # DTB read accesses
93system.cpu.dtb.write_accesses 0 # DTB write accesses
94system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95system.cpu.dtb.hits 0 # DTB hits
96system.cpu.dtb.misses 0 # DTB misses
97system.cpu.dtb.accesses 0 # DTB accesses
98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
127system.cpu.itb.walker.walks 0 # Table walker walks requested
128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
135system.cpu.itb.inst_hits 0 # ITB inst hits
136system.cpu.itb.inst_misses 0 # ITB inst misses
137system.cpu.itb.read_hits 0 # DTB read hits
138system.cpu.itb.read_misses 0 # DTB read misses
139system.cpu.itb.write_hits 0 # DTB write hits
140system.cpu.itb.write_misses 0 # DTB write misses
141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 548 # Number of system calls
157system.cpu.numCycles 1415076095 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 504986854 # Number of instructions committed
161system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 19311615 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
166system.cpu.num_int_insts 448454356 # number of integer instructions
167system.cpu.num_fp_insts 16 # number of float instructions
168system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read
169system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
174system.cpu.num_mem_refs 172745235 # number of memory refs
175system.cpu.num_load_insts 115884756 # Number of load instructions
176system.cpu.num_store_insts 56860479 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
178system.cpu.num_busy_cycles 1415076094.998000 # Number of busy cycles
179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 121548302 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction
184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
187system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
188system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
189system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
190system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
191system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
192system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
193system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
194system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
195system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
196system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
197system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
198system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
199system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
200system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
201system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
202system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
203system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
204system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
205system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
206system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
207system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
208system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
209system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
212system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
213system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 548695379 # Class of executed instruction
217system.cpu.dcache.tags.replacements 1134822 # number of replacements
218system.cpu.dcache.tags.tagsinuse 4065.318385 # Cycle average of tags in use
219system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
222system.cpu.dcache.tags.warmup_cycle 11716394000 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318385 # Average occupied blocks per requestor
224system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
233system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses
235system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits
236system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits
237system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
238system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
239system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
240system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
241system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
242system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
243system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
244system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
245system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits
246system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits
247system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits
248system.cpu.dcache.overall_hits::total 167203374 # number of overall hits
249system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses
250system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses
251system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
252system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
255system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses
256system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
257system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
258system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
259system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818699500 # number of ReadReq miss cycles
260system.cpu.dcache.ReadReq_miss_latency::total 11818699500 # number of ReadReq miss cycles
261system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles
263system.cpu.dcache.demand_miss_latency::cpu.data 20687471500 # number of demand (read+write) miss cycles
264system.cpu.dcache.demand_miss_latency::total 20687471500 # number of demand (read+write) miss cycles
265system.cpu.dcache.overall_miss_latency::cpu.data 20687471500 # number of overall miss cycles
266system.cpu.dcache.overall_miss_latency::total 20687471500 # number of overall miss cycles
267system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
268system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
269system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
270system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
275system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
276system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
277system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses
278system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses
279system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses
280system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses
281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses
282system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses
283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
284system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
287system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses
288system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
289system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
290system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532 # average ReadReq miss latency
292system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532 # average ReadReq miss latency
293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency
295system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777 # average overall miss latency
296system.cpu.dcache.demand_avg_miss_latency::total 18164.160777 # average overall miss latency
297system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::total 18164.144829 # average overall miss latency
299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305system.cpu.dcache.fast_writes 0 # number of fast writes performed
306system.cpu.dcache.cache_copies 0 # number of cache copies performed
307system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks
308system.cpu.dcache.writebacks::total 1064905 # number of writebacks
309system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses
310system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses
311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
312system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
315system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses
316system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
317system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
318system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644714000 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644714000 # number of ReadReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles
322system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles
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328system.cpu.dcache.overall_mshr_miss_latency::total 18979149500 # number of overall MSHR miss cycles
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332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
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334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses
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336system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
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342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency
343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
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347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120 # average overall mshr miss latency
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432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency
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434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency
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570system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses
571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230 # average ReadReq mshr miss latency
572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636 # average ReadReq mshr miss latency
573system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency
574system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency
575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency
576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency
577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency
578system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
579system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency
580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency
581system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
582system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
583system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
584system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
585system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
586system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
587system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
588system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
589system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
590system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
591system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
592system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
593system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
594system.cpu.toL2Bus.snoops 0 # Total snoops (count)
595system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram

596system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram

596system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram

597system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
598system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
599system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

600system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
602system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram
603system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram

600system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram

604system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

602system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

605system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
606system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

603system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
604system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram