Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt

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1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.717366 # Number of seconds simulated 4sim_ticks 717366012000 # Number of ticks simulated 5final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.717366 # Number of seconds simulated 4sim_ticks 717366012000 # Number of ticks simulated 5final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1131056 # Simulator instruction rate (inst/s) 8host_op_rate 1274509 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1606737202 # Simulator tick rate (ticks/s) 10host_mem_usage 271980 # Number of bytes of host memory used 11host_seconds 446.47 # Real time elapsed on the host	7host_inst_rate 879063 # Simulator instruction rate (inst/s) 8host_op_rate 990556 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1248765490 # Simulator tick rate (ticks/s) 10host_mem_usage 313636 # Number of bytes of host memory used 11host_seconds 574.46 # Real time elapsed on the host
12sim_insts 504986853 # Number of instructions simulated 13sim_ops 569034839 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) 39system.membus.throughput 21286941 # Throughput (bytes/s) 40system.membus.trans_dist::ReadReq 41855 # Transaction distribution 41system.membus.trans_dist::ReadResp 41855 # Transaction distribution 42system.membus.trans_dist::Writeback 95953 # Transaction distribution 43system.membus.trans_dist::ReadExReq 100794 # Transaction distribution 44system.membus.trans_dist::ReadExResp 100794 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) 49system.membus.data_through_bus 15270528 # Total data (bytes) 50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 51system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 53system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 134system.cpu.itb.read_accesses 0 # DTB read accesses 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.inst_accesses 0 # ITB inst accesses 137system.cpu.itb.hits 0 # DTB hits 138system.cpu.itb.misses 0 # DTB misses 139system.cpu.itb.accesses 0 # DTB accesses 140system.cpu.workload.num_syscalls 548 # Number of system calls 141system.cpu.numCycles 1434732024 # number of cpu cycles simulated 142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 144system.cpu.committedInsts 504986853 # Number of instructions committed 145system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed 146system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses 147system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 148system.cpu.num_func_calls 19311615 # number of times a function call or return occured 149system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls 150system.cpu.num_int_insts 470727695 # number of integer instructions 151system.cpu.num_fp_insts 16 # number of float instructions 152system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read 153system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written 154system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 155system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 156system.cpu.num_mem_refs 182890034 # number of memory refs 157system.cpu.num_load_insts 126029555 # Number of load instructions 158system.cpu.num_store_insts 56860479 # Number of store instructions 159system.cpu.num_idle_cycles 0 # Number of idle cycles 160system.cpu.num_busy_cycles 1434732024 # Number of busy cycles 161system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 162system.cpu.idle_fraction 0 # Percentage of idle cycles 163system.cpu.Branches 121548301 # Number of branches fetched	12sim_insts 504986853 # Number of instructions simulated 13sim_ops 569034839 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) 39system.membus.throughput 21286941 # Throughput (bytes/s) 40system.membus.trans_dist::ReadReq 41855 # Transaction distribution 41system.membus.trans_dist::ReadResp 41855 # Transaction distribution 42system.membus.trans_dist::Writeback 95953 # Transaction distribution 43system.membus.trans_dist::ReadExReq 100794 # Transaction distribution 44system.membus.trans_dist::ReadExResp 100794 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) 49system.membus.data_through_bus 15270528 # Total data (bytes) 50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 51system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 53system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 134system.cpu.itb.read_accesses 0 # DTB read accesses 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.inst_accesses 0 # ITB inst accesses 137system.cpu.itb.hits 0 # DTB hits 138system.cpu.itb.misses 0 # DTB misses 139system.cpu.itb.accesses 0 # DTB accesses 140system.cpu.workload.num_syscalls 548 # Number of system calls 141system.cpu.numCycles 1434732024 # number of cpu cycles simulated 142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 144system.cpu.committedInsts 504986853 # Number of instructions committed 145system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed 146system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses 147system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 148system.cpu.num_func_calls 19311615 # number of times a function call or return occured 149system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls 150system.cpu.num_int_insts 470727695 # number of integer instructions 151system.cpu.num_fp_insts 16 # number of float instructions 152system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read 153system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written 154system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 155system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 156system.cpu.num_mem_refs 182890034 # number of memory refs 157system.cpu.num_load_insts 126029555 # Number of load instructions 158system.cpu.num_store_insts 56860479 # Number of store instructions 159system.cpu.num_idle_cycles 0 # Number of idle cycles 160system.cpu.num_busy_cycles 1434732024 # Number of busy cycles 161system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 162system.cpu.idle_fraction 0 # Percentage of idle cycles 163system.cpu.Branches 121548301 # Number of branches fetched
	164system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 165system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction 166system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction 167system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction 168system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction 169system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction 170system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction 171system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction 172system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction 173system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction 174system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction 175system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction 176system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction 177system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction 178system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction 179system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction 180system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction 181system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction 182system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction 183system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction 184system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction 185system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction 186system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction 187system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction 188system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction 189system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction 190system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction 191system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction 192system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction 193system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction 194system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction 195system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction 196system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 197system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 198system.cpu.op_class::total 570968717 # Class of executed instruction
164system.cpu.icache.tags.replacements 9788 # number of replacements 165system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use 166system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. 167system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 168system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. 169system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 170system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor 171system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy 172system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy 173system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 174system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 175system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 176system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id 177system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id 178system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id 179system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 180system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses 181system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses 182system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits 183system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits 184system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits 185system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits 186system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits 187system.cpu.icache.overall_hits::total 516599855 # number of overall hits 188system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 189system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 190system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 191system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 192system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 193system.cpu.icache.overall_misses::total 11521 # number of overall misses 194system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles 195system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles 196system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles 197system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles 198system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles 199system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles 200system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) 201system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) 202system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses 203system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses 204system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses 205system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses 206system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 207system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 208system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 209system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 210system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 211system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses 212system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency 213system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency 214system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency 215system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency 216system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency 217system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency 218system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 219system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 221system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 222system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 223system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 224system.cpu.icache.fast_writes 0 # number of fast writes performed 225system.cpu.icache.cache_copies 0 # number of cache copies performed 226system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 227system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 228system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 229system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 230system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 231system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 232system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles 233system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles 234system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles 235system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles 236system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles 237system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles 238system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 239system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 240system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 241system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 242system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 243system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 244system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency 245system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency 246system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency 247system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency 248system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency 249system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency 250system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 251system.cpu.l2cache.tags.replacements 109895 # number of replacements 252system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use 253system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. 254system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. 255system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. 256system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. 257system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor 258system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor 259system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor 260system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy 261system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy 262system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy 263system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy 264system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id 265system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 266system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 267system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id 268system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id 269system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id 270system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses 271system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses 272system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits 273system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits 274system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits 275system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits 276system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits 277system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits 278system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits 279system.cpu.l2cache.demand_hits::cpu.inst 8751 # number of demand (read+write) hits 280system.cpu.l2cache.demand_hits::cpu.data 999039 # number of demand (read+write) hits 281system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits 282system.cpu.l2cache.overall_hits::cpu.inst 8751 # number of overall hits 283system.cpu.l2cache.overall_hits::cpu.data 999039 # number of overall hits 284system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits 285system.cpu.l2cache.ReadReq_misses::cpu.inst 2770 # number of ReadReq misses 286system.cpu.l2cache.ReadReq_misses::cpu.data 39085 # number of ReadReq misses 287system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses 288system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses 289system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses 290system.cpu.l2cache.demand_misses::cpu.inst 2770 # number of demand (read+write) misses 291system.cpu.l2cache.demand_misses::cpu.data 139879 # number of demand (read+write) misses 292system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses 293system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses 294system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses 295system.cpu.l2cache.overall_misses::total 142649 # number of overall misses 296system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles 297system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles 298system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles 299system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles 300system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles 301system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles 302system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles 303system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles 304system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles 305system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles 306system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles 307system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 308system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 309system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) 310system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses) 311system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses) 312system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 313system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 314system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 315system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 316system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 317system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 318system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 319system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses 320system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240431 # miss rate for ReadReq accesses 321system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049939 # miss rate for ReadReq accesses 322system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses 323system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses 324system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses 325system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240431 # miss rate for demand accesses 326system.cpu.l2cache.demand_miss_rate::cpu.data 0.122817 # miss rate for demand accesses 327system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses 328system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses 329system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses 330system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses 331system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency 332system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency 333system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency 334system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency 335system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency 336system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency 337system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency 338system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency 339system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency 340system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency 341system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency 342system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 343system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 344system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 345system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 346system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 347system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 348system.cpu.l2cache.fast_writes 0 # number of fast writes performed 349system.cpu.l2cache.cache_copies 0 # number of cache copies performed 350system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks 351system.cpu.l2cache.writebacks::total 95953 # number of writebacks 352system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2770 # number of ReadReq MSHR misses 353system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39085 # number of ReadReq MSHR misses 354system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses 355system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses 356system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses 357system.cpu.l2cache.demand_mshr_misses::cpu.inst 2770 # number of demand (read+write) MSHR misses 358system.cpu.l2cache.demand_mshr_misses::cpu.data 139879 # number of demand (read+write) MSHR misses 359system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses 360system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses 361system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses 362system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses 363system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles 364system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles 365system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles 366system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles 367system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles 368system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles 369system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles 370system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles 371system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles 372system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles 373system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles 374system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses 375system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses 376system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses 377system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses 378system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses 379system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses 380system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses 381system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses 382system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses 383system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses 384system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses 385system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency 386system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency 387system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency 388system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency 389system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency 390system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency 391system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency 392system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency 393system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency 394system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency 395system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency 396system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 397system.cpu.dcache.tags.replacements 1134822 # number of replacements 398system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use 399system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. 400system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. 401system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. 402system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. 403system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor 404system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy 405system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy 406system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 407system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 408system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 409system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 410system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 411system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id 412system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 413system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses 414system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses 415system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits 416system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits 417system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 418system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 419system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 420system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 421system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 422system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 423system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits 424system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits 425system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits 426system.cpu.dcache.overall_hits::total 176840704 # number of overall hits 427system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses 428system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses 429system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 430system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 431system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses 432system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses 433system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 434system.cpu.dcache.overall_misses::total 1138918 # number of overall misses 435system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles 436system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles 437system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles 438system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles 439system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles 440system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles 441system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles 442system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles 443system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) 444system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) 445system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 446system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 449system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 450system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 451system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses 452system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses 453system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses 454system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses 455system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses 456system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 459system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses 460system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses 461system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses 462system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses 463system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency 464system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency 466system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency 468system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency 469system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency 470system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency 471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu.dcache.fast_writes 0 # number of fast writes performed 478system.cpu.dcache.cache_copies 0 # number of cache copies performed 479system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks 480system.cpu.dcache.writebacks::total 1064905 # number of writebacks 481system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses 482system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses 483system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 484system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 485system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses 486system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses 487system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 488system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses 489system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles 490system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles 491system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles 492system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles 493system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles 494system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles 495system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles 496system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles 497system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses 498system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses 499system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 500system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 501system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses 502system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses 503system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses 504system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses 505system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency 506system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency 507system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency 508system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency 510system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency 512system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency 513system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 514system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s) 515system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution 516system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution 517system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution 518system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution 519system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution 520system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) 521system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) 522system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) 523system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) 524system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) 525system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) 526system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes) 527system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 528system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) 529system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 530system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 531system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 532system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) 533system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 534 535---------- End Simulation Statistics ----------	199system.cpu.icache.tags.replacements 9788 # number of replacements 200system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use 201system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 205system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy 207system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy 208system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 209system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id 212system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id 213system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id 214system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 215system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses 216system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses 217system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits 218system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits 219system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits 220system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits 221system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits 222system.cpu.icache.overall_hits::total 516599855 # number of overall hits 223system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 224system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 225system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 226system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 227system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 228system.cpu.icache.overall_misses::total 11521 # number of overall misses 229system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles 230system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles 231system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles 232system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles 233system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles 234system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles 235system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) 236system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) 237system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses 238system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses 239system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses 240system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses 241system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 242system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 243system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 244system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 245system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 246system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses 247system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency 248system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency 249system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency 250system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency 251system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency 252system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency 253system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 256system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 257system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 258system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 259system.cpu.icache.fast_writes 0 # number of fast writes performed 260system.cpu.icache.cache_copies 0 # number of cache copies performed 261system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 262system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 263system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 264system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 265system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 266system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 267system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles 268system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles 269system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles 270system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles 271system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles 272system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles 273system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 274system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 275system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 276system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 277system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 278system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 279system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency 280system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency 281system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency 282system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency 283system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency 284system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency 285system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 286system.cpu.l2cache.tags.replacements 109895 # number of replacements 287system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use 288system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. 289system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. 290system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. 291system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. 292system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor 293system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor 294system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy 296system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id 300system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 302system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id 303system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id 304system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id 305system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses 306system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses 307system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits 308system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits 309system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits 310system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits 311system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits 312system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits 313system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits 314system.cpu.l2cache.demand_hits::cpu.inst 8751 # number of demand (read+write) hits 315system.cpu.l2cache.demand_hits::cpu.data 999039 # number of demand (read+write) hits 316system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits 317system.cpu.l2cache.overall_hits::cpu.inst 8751 # number of overall hits 318system.cpu.l2cache.overall_hits::cpu.data 999039 # number of overall hits 319system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits 320system.cpu.l2cache.ReadReq_misses::cpu.inst 2770 # number of ReadReq misses 321system.cpu.l2cache.ReadReq_misses::cpu.data 39085 # number of ReadReq misses 322system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses 323system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses 324system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses 325system.cpu.l2cache.demand_misses::cpu.inst 2770 # number of demand (read+write) misses 326system.cpu.l2cache.demand_misses::cpu.data 139879 # number of demand (read+write) misses 327system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses 328system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses 329system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses 330system.cpu.l2cache.overall_misses::total 142649 # number of overall misses 331system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles 332system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles 333system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles 334system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles 335system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles 336system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles 337system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles 338system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles 339system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles 340system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles 341system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles 342system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 343system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 344system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) 345system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses) 346system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses) 347system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 348system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 349system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 350system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 351system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 352system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 353system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 354system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses 355system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240431 # miss rate for ReadReq accesses 356system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049939 # miss rate for ReadReq accesses 357system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses 358system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses 359system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses 360system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240431 # miss rate for demand accesses 361system.cpu.l2cache.demand_miss_rate::cpu.data 0.122817 # miss rate for demand accesses 362system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses 363system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses 364system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses 365system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses 366system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency 367system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency 368system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency 369system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency 370system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency 371system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency 372system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency 373system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency 374system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency 375system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency 376system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency 377system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 381system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 382system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 383system.cpu.l2cache.fast_writes 0 # number of fast writes performed 384system.cpu.l2cache.cache_copies 0 # number of cache copies performed 385system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks 386system.cpu.l2cache.writebacks::total 95953 # number of writebacks 387system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2770 # number of ReadReq MSHR misses 388system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39085 # number of ReadReq MSHR misses 389system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses 390system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses 391system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses 392system.cpu.l2cache.demand_mshr_misses::cpu.inst 2770 # number of demand (read+write) MSHR misses 393system.cpu.l2cache.demand_mshr_misses::cpu.data 139879 # number of demand (read+write) MSHR misses 394system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses 395system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses 396system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses 397system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses 398system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles 399system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles 400system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles 401system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles 402system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles 403system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles 404system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles 405system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles 406system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles 407system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles 408system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles 409system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses 410system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses 411system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses 412system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses 413system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses 414system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses 415system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses 416system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses 417system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses 418system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses 419system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses 420system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency 421system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency 422system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency 423system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency 424system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency 425system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency 426system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency 427system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency 428system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency 429system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency 430system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency 431system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 432system.cpu.dcache.tags.replacements 1134822 # number of replacements 433system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use 434system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. 435system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. 436system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. 437system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. 438system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor 439system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy 440system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy 441system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id 447system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 448system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses 449system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses 450system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits 451system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits 452system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 453system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 454system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 455system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 456system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 457system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 458system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits 459system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits 460system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits 461system.cpu.dcache.overall_hits::total 176840704 # number of overall hits 462system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses 463system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses 464system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 465system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 466system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses 467system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses 468system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 469system.cpu.dcache.overall_misses::total 1138918 # number of overall misses 470system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles 471system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles 472system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles 473system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles 474system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles 475system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles 476system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles 477system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles 478system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) 479system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) 480system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 481system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 482system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 483system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 484system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 485system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 486system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses 487system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses 488system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses 489system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses 490system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses 491system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses 492system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 493system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 494system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses 495system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses 496system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses 497system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency 499system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency 501system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 507system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 511system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed 514system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks 515system.cpu.dcache.writebacks::total 1064905 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 520system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses 521system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses 522system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 523system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses 524system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles 531system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles 532system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 536system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses 537system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses 538system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses 539system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency 541system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency 543system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency 545system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency 547system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency 548system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 549system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s) 550system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution 555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) 556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) 557system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) 558system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) 559system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) 561system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes) 562system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 563system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) 564system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 565system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 566system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 567system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) 568system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 569 570---------- End Simulation Statistics ----------