1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.722234 # Number of seconds simulated
4sim_ticks 722234364000 # Number of ticks simulated
5final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1518630 # Simulator instruction rate (inst/s)
8host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
9host_mem_usage 222536 # Number of bytes of host memory used
10host_seconds 374.70 # Real time elapsed on the host
11sim_insts 569034848 # Number of instructions simulated
12system.physmem.bytes_read 14797056 # Number of bytes read from this memory
13system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
14system.physmem.bytes_written 11027328 # Number of bytes written to this memory
15system.physmem.num_reads 231204 # Number of read requests responded to by this memory
16system.physmem.num_writes 172302 # Number of write requests responded to by this memory
17system.physmem.num_other 0 # Number of other requests responded to by this memory
18system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
19system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
--- 40 unchanged lines hidden (view full) ---
60system.cpu.itb.inst_accesses 0 # ITB inst accesses
61system.cpu.itb.hits 0 # DTB hits
62system.cpu.itb.misses 0 # DTB misses
63system.cpu.itb.accesses 0 # DTB accesses
64system.cpu.workload.num_syscalls 548 # Number of system calls
65system.cpu.numCycles 1444468728 # number of cpu cycles simulated
66system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
67system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
68system.cpu.num_insts 569034848 # Number of instructions executed
69system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
70system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
71system.cpu.num_func_calls 15725605 # number of times a function call or return occured
72system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
73system.cpu.num_int_insts 470727703 # number of integer instructions
74system.cpu.num_fp_insts 16 # number of float instructions
75system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
76system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
--- 7 unchanged lines hidden (view full) ---
84system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
85system.cpu.idle_fraction 0 # Percentage of idle cycles
86system.cpu.icache.replacements 9788 # number of replacements
87system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
88system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
89system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
90system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
91system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
92system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
93system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
94system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
95system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
96system.cpu.icache.overall_hits 516599864 # number of overall hits
97system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
98system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
99system.cpu.icache.overall_misses 11521 # number of overall misses
100system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
101system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
102system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
103system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
104system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
105system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
106system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
107system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
108system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
109system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
110system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
111system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
112system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
113system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
114system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
115system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
116system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
117system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
118system.cpu.icache.fast_writes 0 # number of fast writes performed
119system.cpu.icache.cache_copies 0 # number of cache copies performed
120system.cpu.icache.writebacks 0 # number of writebacks
121system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
122system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
123system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
124system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
125system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
126system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
127system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
128system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
129system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
130system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
131system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
132system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
133system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
134system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
135system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
137system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
138system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
139system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
140system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
141system.cpu.dcache.replacements 1134822 # number of replacements
142system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
143system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
144system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
145system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
146system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
147system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
148system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
149system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
150system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
151system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
152system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
153system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
154system.cpu.dcache.overall_hits 176840705 # number of overall hits
155system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
156system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
157system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
158system.cpu.dcache.overall_misses 1138918 # number of overall misses
159system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
160system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
161system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
162system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
163system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
164system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
165system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
166system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
167system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
168system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
169system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
170system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
171system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
172system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
173system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
174system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
175system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
176system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
177system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
178system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
179system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
180system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
181system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
182system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
183system.cpu.dcache.fast_writes 0 # number of fast writes performed
184system.cpu.dcache.cache_copies 0 # number of cache copies performed
185system.cpu.dcache.writebacks 1025440 # number of writebacks
186system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
187system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
188system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
189system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
190system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
191system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
192system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
193system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
194system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
195system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
196system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
197system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
198system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
199system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
200system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
201system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
202system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
203system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
204system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
205system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
206system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
207system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
208system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
209system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
210system.cpu.l2cache.replacements 212089 # number of replacements
211system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
212system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
213system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
214system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
215system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
216system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
217system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
218system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
219system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
220system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
221system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
222system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
223system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
224system.cpu.l2cache.overall_hits 919235 # number of overall hits
225system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
226system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
227system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
228system.cpu.l2cache.overall_misses 231204 # number of overall misses
229system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
230system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
231system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
232system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
233system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
234system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
235system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
236system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
237system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
238system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
239system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
240system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
241system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
242system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
243system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
244system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
245system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
246system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
247system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
248system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
249system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
250system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
251system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
252system.cpu.l2cache.fast_writes 0 # number of fast writes performed
253system.cpu.l2cache.cache_copies 0 # number of cache copies performed
254system.cpu.l2cache.writebacks 172302 # number of writebacks
255system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
256system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
257system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
258system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
259system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
260system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
261system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
262system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
263system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
264system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
265system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
266system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
267system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
268system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
269system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
270system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
271system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
272system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
273system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
274system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
275system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
276system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
277system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
278system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
279
280---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.722234 # Number of seconds simulated
4sim_ticks 722234364000 # Number of ticks simulated
5final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1518630 # Simulator instruction rate (inst/s)
8host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
9host_mem_usage 222536 # Number of bytes of host memory used
10host_seconds 374.70 # Real time elapsed on the host
11sim_insts 569034848 # Number of instructions simulated
12system.physmem.bytes_read 14797056 # Number of bytes read from this memory
13system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
14system.physmem.bytes_written 11027328 # Number of bytes written to this memory
15system.physmem.num_reads 231204 # Number of read requests responded to by this memory
16system.physmem.num_writes 172302 # Number of write requests responded to by this memory
17system.physmem.num_other 0 # Number of other requests responded to by this memory
18system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
19system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
--- 40 unchanged lines hidden (view full) ---
60system.cpu.itb.inst_accesses 0 # ITB inst accesses
61system.cpu.itb.hits 0 # DTB hits
62system.cpu.itb.misses 0 # DTB misses
63system.cpu.itb.accesses 0 # DTB accesses
64system.cpu.workload.num_syscalls 548 # Number of system calls
65system.cpu.numCycles 1444468728 # number of cpu cycles simulated
66system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
67system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
68system.cpu.num_insts 569034848 # Number of instructions executed
69system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
70system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
71system.cpu.num_func_calls 15725605 # number of times a function call or return occured
72system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
73system.cpu.num_int_insts 470727703 # number of integer instructions
74system.cpu.num_fp_insts 16 # number of float instructions
75system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
76system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
--- 7 unchanged lines hidden (view full) ---
84system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
85system.cpu.idle_fraction 0 # Percentage of idle cycles
86system.cpu.icache.replacements 9788 # number of replacements
87system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
88system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
89system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
90system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
91system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
92system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
93system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
94system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
95system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
96system.cpu.icache.overall_hits 516599864 # number of overall hits
97system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
98system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
99system.cpu.icache.overall_misses 11521 # number of overall misses
100system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
101system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
102system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
103system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
104system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
105system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
106system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
107system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
108system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
109system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
110system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
111system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
112system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
113system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
114system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
115system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
116system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
117system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
118system.cpu.icache.fast_writes 0 # number of fast writes performed
119system.cpu.icache.cache_copies 0 # number of cache copies performed
120system.cpu.icache.writebacks 0 # number of writebacks
121system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
122system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
123system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
124system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
125system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
126system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
127system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
128system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
129system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
130system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
131system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
132system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
133system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
134system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
135system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
137system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
138system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
139system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
140system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
141system.cpu.dcache.replacements 1134822 # number of replacements
142system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
143system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
144system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
145system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
146system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
147system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
148system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
149system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
150system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
151system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
152system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
153system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
154system.cpu.dcache.overall_hits 176840705 # number of overall hits
155system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
156system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
157system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
158system.cpu.dcache.overall_misses 1138918 # number of overall misses
159system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
160system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
161system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
162system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
163system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
164system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
165system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
166system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
167system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
168system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
169system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
170system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
171system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
172system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
173system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
174system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
175system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
176system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
177system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
178system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
179system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
180system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
181system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
182system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
183system.cpu.dcache.fast_writes 0 # number of fast writes performed
184system.cpu.dcache.cache_copies 0 # number of cache copies performed
185system.cpu.dcache.writebacks 1025440 # number of writebacks
186system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
187system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
188system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
189system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
190system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
191system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
192system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
193system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
194system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
195system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
196system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
197system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
198system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
199system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
200system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
201system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
202system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
203system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
204system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
205system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
206system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
207system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
208system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
209system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
210system.cpu.l2cache.replacements 212089 # number of replacements
211system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
212system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
213system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
214system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
215system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
216system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
217system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
218system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
219system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
220system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
221system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
222system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
223system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
224system.cpu.l2cache.overall_hits 919235 # number of overall hits
225system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
226system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
227system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
228system.cpu.l2cache.overall_misses 231204 # number of overall misses
229system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
230system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
231system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
232system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
233system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
234system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
235system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
236system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
237system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
238system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
239system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
240system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
241system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
242system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
243system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
244system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
245system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
246system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
247system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
248system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
249system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
250system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
251system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
252system.cpu.l2cache.fast_writes 0 # number of fast writes performed
253system.cpu.l2cache.cache_copies 0 # number of cache copies performed
254system.cpu.l2cache.writebacks 172302 # number of writebacks
255system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
256system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
257system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
258system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
259system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
260system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
261system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
262system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
263system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
264system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
265system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
266system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
267system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
268system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
269system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
270system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
271system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
272system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
273system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
274system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
275system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
276system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
277system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
278system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
279
280---------- End Simulation Statistics ----------