1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.708539 # Number of seconds simulated
4sim_ticks 708539449500 # Number of ticks simulated
5final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1440714 # Simulator instruction rate (inst/s)
8host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2021455048 # Simulator tick rate (ticks/s)
10host_mem_usage 314896 # Number of bytes of host memory used
11host_seconds 350.51 # Real time elapsed on the host
12sim_insts 504984064 # Number of instructions simulated
13sim_ops 546875315 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
--- 7 unchanged lines hidden (view full) ---
31system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
69system.cpu.dtb.walker.walks 0 # Table walker walks requested
70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92system.cpu.dtb.read_accesses 0 # DTB read accesses
93system.cpu.dtb.write_accesses 0 # DTB write accesses
94system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95system.cpu.dtb.hits 0 # DTB hits
96system.cpu.dtb.misses 0 # DTB misses
97system.cpu.dtb.accesses 0 # DTB accesses
98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
127system.cpu.itb.walker.walks 0 # Table walker walks requested
128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 548 # Number of system calls
157system.cpu.numCycles 1417078899 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 504984064 # Number of instructions committed
161system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 19311615 # number of times a function call or return occured
--- 44 unchanged lines hidden (view full) ---
209system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
212system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
213system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 548692589 # Class of executed instruction
217system.cpu.dcache.tags.replacements 1136276 # number of replacements
218system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
219system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.
222system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
224system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
233system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
235system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
236system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
237system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
238system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits
239system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
240system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
241system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
242system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
--- 96 unchanged lines hidden (view full) ---
339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
347system.cpu.icache.tags.replacements 9788 # number of replacements
348system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
349system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
350system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
351system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks.
352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
353system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
354system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
355system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
356system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
357system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
362system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
363system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
364system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
365system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
366system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
367system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
368system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits
369system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits
370system.cpu.icache.overall_hits::total 516597066 # number of overall hits
371system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
372system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
--- 52 unchanged lines hidden (view full) ---
425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
426system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
430system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
432system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
433system.cpu.l2cache.tags.replacements 110394 # number of replacements
434system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
435system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
436system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
437system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
438system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
439system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
440system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
--- 5 unchanged lines hidden (view full) ---
446system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
447system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
448system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
449system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
451system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
452system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
453system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
454system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
455system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
456system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
457system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits
458system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
459system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits
460system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits
461system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits
--- 130 unchanged lines hidden (view full) ---
592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
594system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
595system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
596system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
597system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
598system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
599system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
600system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
602system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution
--- 16 unchanged lines hidden (view full) ---
624system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
625system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
626system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
627system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
628system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
629system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
630system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
631system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
632system.membus.trans_dist::ReadResp 41576 # Transaction distribution
633system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
634system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
635system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
636system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
637system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
638system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
639system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
--- 19 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.708539 # Number of seconds simulated
4sim_ticks 708539449500 # Number of ticks simulated
5final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1440714 # Simulator instruction rate (inst/s)
8host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2021455048 # Simulator tick rate (ticks/s)
10host_mem_usage 314896 # Number of bytes of host memory used
11host_seconds 350.51 # Real time elapsed on the host
12sim_insts 504984064 # Number of instructions simulated
13sim_ops 546875315 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
--- 7 unchanged lines hidden (view full) ---
31system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
69system.cpu.dtb.walker.walks 0 # Table walker walks requested
70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92system.cpu.dtb.read_accesses 0 # DTB read accesses
93system.cpu.dtb.write_accesses 0 # DTB write accesses
94system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95system.cpu.dtb.hits 0 # DTB hits
96system.cpu.dtb.misses 0 # DTB misses
97system.cpu.dtb.accesses 0 # DTB accesses
98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
127system.cpu.itb.walker.walks 0 # Table walker walks requested
128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 548 # Number of system calls
157system.cpu.numCycles 1417078899 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 504984064 # Number of instructions committed
161system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 19311615 # number of times a function call or return occured
--- 44 unchanged lines hidden (view full) ---
209system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
212system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
213system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 548692589 # Class of executed instruction
217system.cpu.dcache.tags.replacements 1136276 # number of replacements
218system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
219system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.
222system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
224system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
233system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
235system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
236system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
237system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
238system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits
239system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
240system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
241system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
242system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
--- 96 unchanged lines hidden (view full) ---
339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
347system.cpu.icache.tags.replacements 9788 # number of replacements
348system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
349system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
350system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
351system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks.
352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
353system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
354system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
355system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
356system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
357system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
362system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
363system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
364system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
365system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
366system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
367system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
368system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits
369system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits
370system.cpu.icache.overall_hits::total 516597066 # number of overall hits
371system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
372system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
--- 52 unchanged lines hidden (view full) ---
425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
426system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
430system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
432system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
433system.cpu.l2cache.tags.replacements 110394 # number of replacements
434system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
435system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
436system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
437system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
438system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
439system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
440system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
--- 5 unchanged lines hidden (view full) ---
446system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
447system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
448system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
449system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
451system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
452system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
453system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
454system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
455system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
456system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
457system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits
458system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
459system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits
460system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits
461system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits
--- 130 unchanged lines hidden (view full) ---
592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
594system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
595system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
596system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
597system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
598system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
599system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
600system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
602system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution
--- 16 unchanged lines hidden (view full) ---
624system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
625system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
626system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
627system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
628system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
629system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
630system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
631system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
632system.membus.trans_dist::ReadResp 41576 # Transaction distribution
633system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
634system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
635system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
636system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
637system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
638system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
639system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
--- 19 unchanged lines hidden ---