1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.707539 # Number of seconds simulated
4sim_ticks 707539023000 # Number of ticks simulated
5final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1172742 # Simulator instruction rate (inst/s)
8host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1643133313 # Simulator tick rate (ticks/s)
10host_mem_usage 319240 # Number of bytes of host memory used
11host_seconds 430.60 # Real time elapsed on the host
12sim_insts 504986853 # Number of instructions simulated
13sim_ops 546878104 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
--- 11 unchanged lines hidden (view full) ---
31system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
39system.membus.throughput 21582595 # Throughput (bytes/s)
40system.membus.trans_dist::ReadReq 41855 # Transaction distribution
41system.membus.trans_dist::ReadResp 41855 # Transaction distribution
42system.membus.trans_dist::Writeback 95953 # Transaction distribution
43system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
44system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
48system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
49system.membus.data_through_bus 15270528 # Total data (bytes)
50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
51system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
53system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
55system.cpu_clk_domain.clock 500 # Clock period in ticks
56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
--- 500 unchanged lines hidden (view full) ---
559system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
560system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
561system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
562system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
563system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
564system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
565system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
566system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
567system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s)
568system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
569system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
570system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
571system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
572system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
573system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
574system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
575system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
576system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
577system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
578system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
579system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
580system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
581system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
582system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
583system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
584system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
585system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
586system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
587
588---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.707539 # Number of seconds simulated
4sim_ticks 707539023000 # Number of ticks simulated
5final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1172742 # Simulator instruction rate (inst/s)
8host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1643133313 # Simulator tick rate (ticks/s)
10host_mem_usage 319240 # Number of bytes of host memory used
11host_seconds 430.60 # Real time elapsed on the host
12sim_insts 504986853 # Number of instructions simulated
13sim_ops 546878104 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
--- 11 unchanged lines hidden (view full) ---
31system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
39system.membus.throughput 21582595 # Throughput (bytes/s)
40system.membus.trans_dist::ReadReq 41855 # Transaction distribution
41system.membus.trans_dist::ReadResp 41855 # Transaction distribution
42system.membus.trans_dist::Writeback 95953 # Transaction distribution
43system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
44system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
48system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
49system.membus.data_through_bus 15270528 # Total data (bytes)
50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
51system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
53system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
55system.cpu_clk_domain.clock 500 # Clock period in ticks
56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
--- 500 unchanged lines hidden (view full) ---
559system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
560system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
561system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
562system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
563system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
564system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
565system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
566system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
567system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s)
568system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
569system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
570system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
571system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
572system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
573system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
574system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
575system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
576system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
577system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
578system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
579system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
580system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
581system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
582system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
583system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
584system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
585system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
586system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
587
588---------- End Simulation Statistics ----------