Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt

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sdiff udiff text old ( 11687:b3d5f0e9e258 ) new ( 11955:1170d039b31e )

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stats.txt (11687:b3d5f0e9e258)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.279361 # Number of seconds simulated 4sim_ticks 279360903000 # Number of ticks simulated 5final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2213544 # Simulator instruction rate (inst/s) 8host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1220693561 # Simulator tick rate (ticks/s) 10host_mem_usage 263256 # Number of bytes of host memory used 11host_seconds 228.85 # Real time elapsed on the host 12sim_insts 506578818 # Number of instructions simulated 13sim_ops 548692039 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory 19system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory 23system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 72system.cpu.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.inst_hits 0 # ITB inst hits 81system.cpu.dtb.inst_misses 0 # ITB inst misses 82system.cpu.dtb.read_hits 0 # DTB read hits 83system.cpu.dtb.read_misses 0 # DTB read misses 84system.cpu.dtb.write_hits 0 # DTB write hits 85system.cpu.dtb.write_misses 0 # DTB write misses 86system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.dtb.read_accesses 0 # DTB read accesses 96system.cpu.dtb.write_accesses 0 # DTB write accesses 97system.cpu.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.dtb.hits 0 # DTB hits 99system.cpu.dtb.misses 0 # DTB misses 100system.cpu.dtb.accesses 0 # DTB accesses 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 132system.cpu.itb.walker.walks 0 # Table walker walks requested 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.inst_hits 0 # ITB inst hits 141system.cpu.itb.inst_misses 0 # ITB inst misses 142system.cpu.itb.read_hits 0 # DTB read hits 143system.cpu.itb.read_misses 0 # DTB read misses 144system.cpu.itb.write_hits 0 # DTB write hits 145system.cpu.itb.write_misses 0 # DTB write misses 146system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.itb.read_accesses 0 # DTB read accesses 156system.cpu.itb.write_accesses 0 # DTB write accesses 157system.cpu.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.itb.hits 0 # DTB hits 159system.cpu.itb.misses 0 # DTB misses 160system.cpu.itb.accesses 0 # DTB accesses	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.279361 # Number of seconds simulated 4sim_ticks 279360903000 # Number of ticks simulated 5final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2213544 # Simulator instruction rate (inst/s) 8host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1220693561 # Simulator tick rate (ticks/s) 10host_mem_usage 263256 # Number of bytes of host memory used 11host_seconds 228.85 # Real time elapsed on the host 12sim_insts 506578818 # Number of instructions simulated 13sim_ops 548692039 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory 19system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory 23system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 72system.cpu.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.inst_hits 0 # ITB inst hits 81system.cpu.dtb.inst_misses 0 # ITB inst misses 82system.cpu.dtb.read_hits 0 # DTB read hits 83system.cpu.dtb.read_misses 0 # DTB read misses 84system.cpu.dtb.write_hits 0 # DTB write hits 85system.cpu.dtb.write_misses 0 # DTB write misses 86system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.dtb.read_accesses 0 # DTB read accesses 96system.cpu.dtb.write_accesses 0 # DTB write accesses 97system.cpu.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.dtb.hits 0 # DTB hits 99system.cpu.dtb.misses 0 # DTB misses 100system.cpu.dtb.accesses 0 # DTB accesses 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 132system.cpu.itb.walker.walks 0 # Table walker walks requested 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.inst_hits 0 # ITB inst hits 141system.cpu.itb.inst_misses 0 # ITB inst misses 142system.cpu.itb.read_hits 0 # DTB read hits 143system.cpu.itb.read_misses 0 # DTB read misses 144system.cpu.itb.write_hits 0 # DTB write hits 145system.cpu.itb.write_misses 0 # DTB write misses 146system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.itb.read_accesses 0 # DTB read accesses 156system.cpu.itb.write_accesses 0 # DTB write accesses 157system.cpu.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.itb.hits 0 # DTB hits 159system.cpu.itb.misses 0 # DTB misses 160system.cpu.itb.accesses 0 # DTB accesses
161system.cpu.workload.num_syscalls 548 # Number of system calls	161system.cpu.workload.numSyscalls 548 # Number of system calls
162system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states 163system.cpu.numCycles 558721807 # number of cpu cycles simulated 164system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.committedInsts 506578818 # Number of instructions committed 167system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed 168system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses 169system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 170system.cpu.num_func_calls 19311615 # number of times a function call or return occured 171system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls 172system.cpu.num_int_insts 448447005 # number of integer instructions 173system.cpu.num_fp_insts 16 # number of float instructions 174system.cpu.num_int_register_reads 749023721 # number of times the integer registers were read 175system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written 176system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 177system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 178system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read 179system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written 180system.cpu.num_mem_refs 172743505 # number of memory refs 181system.cpu.num_load_insts 115883283 # Number of load instructions 182system.cpu.num_store_insts 56860222 # Number of store instructions 183system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 184system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles 185system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 186system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 187system.cpu.Branches 121552863 # Number of branches fetched 188system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 189system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction 190system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 191system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 205system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 206system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 207system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 208system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 209system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 210system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 212system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 213system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 214system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 215system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 216system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 217system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 218system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 219system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 220system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction 221system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction 222system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 223system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction 224system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 225system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::total 548692589 # Class of executed instruction 227system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 228system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 229system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 233system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 234system.membus.trans_dist::ReadReq 630707528 # Transaction distribution 235system.membus.trans_dist::ReadResp 632196069 # Transaction distribution 236system.membus.trans_dist::WriteReq 54239049 # Transaction distribution 237system.membus.trans_dist::WriteResp 54239049 # Transaction distribution 238system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution 239system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution 240system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution 241system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution 242system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution 243system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes) 244system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes) 245system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes) 246system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes) 247system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes) 248system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes) 249system.membus.snoops 0 # Total snoops (count) 250system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 251system.membus.snoop_fanout::samples 687926230 # Request fanout histogram 252system.membus.snoop_fanout::mean 0 # Request fanout histogram 253system.membus.snoop_fanout::stdev 0 # Request fanout histogram 254system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 255system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram 256system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 257system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 258system.membus.snoop_fanout::min_value 0 # Request fanout histogram 259system.membus.snoop_fanout::max_value 0 # Request fanout histogram 260system.membus.snoop_fanout::total 687926230 # Request fanout histogram 261 262---------- End Simulation Statistics ----------	162system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states 163system.cpu.numCycles 558721807 # number of cpu cycles simulated 164system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.committedInsts 506578818 # Number of instructions committed 167system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed 168system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses 169system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 170system.cpu.num_func_calls 19311615 # number of times a function call or return occured 171system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls 172system.cpu.num_int_insts 448447005 # number of integer instructions 173system.cpu.num_fp_insts 16 # number of float instructions 174system.cpu.num_int_register_reads 749023721 # number of times the integer registers were read 175system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written 176system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 177system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 178system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read 179system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written 180system.cpu.num_mem_refs 172743505 # number of memory refs 181system.cpu.num_load_insts 115883283 # Number of load instructions 182system.cpu.num_store_insts 56860222 # Number of store instructions 183system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 184system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles 185system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 186system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 187system.cpu.Branches 121552863 # Number of branches fetched 188system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 189system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction 190system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 191system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 205system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 206system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 207system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 208system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 209system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 210system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 212system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 213system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 214system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 215system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 216system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 217system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 218system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 219system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 220system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction 221system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction 222system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 223system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction 224system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 225system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::total 548692589 # Class of executed instruction 227system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 228system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 229system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 233system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states 234system.membus.trans_dist::ReadReq 630707528 # Transaction distribution 235system.membus.trans_dist::ReadResp 632196069 # Transaction distribution 236system.membus.trans_dist::WriteReq 54239049 # Transaction distribution 237system.membus.trans_dist::WriteResp 54239049 # Transaction distribution 238system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution 239system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution 240system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution 241system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution 242system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution 243system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes) 244system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes) 245system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes) 246system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes) 247system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes) 248system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes) 249system.membus.snoops 0 # Total snoops (count) 250system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 251system.membus.snoop_fanout::samples 687926230 # Request fanout histogram 252system.membus.snoop_fanout::mean 0 # Request fanout histogram 253system.membus.snoop_fanout::stdev 0 # Request fanout histogram 254system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 255system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram 256system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 257system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 258system.membus.snoop_fanout::min_value 0 # Request fanout histogram 259system.membus.snoop_fanout::max_value 0 # Request fanout histogram 260system.membus.snoop_fanout::total 687926230 # Request fanout histogram 261 262---------- End Simulation Statistics ----------