Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt

stats.txt (10628:c9b7e0c69f88)	stats.txt (10726:8a20e2a1562d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.279362 # Number of seconds simulated 4sim_ticks 279362297500 # Number of ticks simulated 5final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.279362 # Number of seconds simulated 4sim_ticks 279362297500 # Number of ticks simulated 5final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1700410 # Simulator instruction rate (inst/s) 8host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 937717572 # Simulator tick rate (ticks/s) 10host_mem_usage 304668 # Number of bytes of host memory used 11host_seconds 297.92 # Real time elapsed on the host	7host_inst_rate 1941586 # Simulator instruction rate (inst/s) 8host_op_rate 2102994 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1070717412 # Simulator tick rate (ticks/s) 10host_mem_usage 304560 # Number of bytes of host memory used 11host_seconds 260.91 # Real time elapsed on the host
12sim_insts 506581607 # Number of instructions simulated 13sim_ops 548694828 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory 18system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory 22system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) 38system.cpu_clk_domain.clock 500 # Clock period in ticks 39system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 58system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 59system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 60system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 68system.cpu.dtb.walker.walks 0 # Table walker walks requested 69system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.inst_hits 0 # ITB inst hits 77system.cpu.dtb.inst_misses 0 # ITB inst misses 78system.cpu.dtb.read_hits 0 # DTB read hits 79system.cpu.dtb.read_misses 0 # DTB read misses 80system.cpu.dtb.write_hits 0 # DTB write hits 81system.cpu.dtb.write_misses 0 # DTB write misses 82system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 84system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 85system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 86system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 87system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 88system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 89system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.dtb.read_accesses 0 # DTB read accesses 92system.cpu.dtb.write_accesses 0 # DTB write accesses 93system.cpu.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.dtb.hits 0 # DTB hits 95system.cpu.dtb.misses 0 # DTB misses 96system.cpu.dtb.accesses 0 # DTB accesses 97system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 106system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 107system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 108system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 109system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 110system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 121system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 122system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 123system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 124system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 125system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 548 # Number of system calls 156system.cpu.numCycles 558724596 # number of cpu cycles simulated 157system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 158system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 159system.cpu.committedInsts 506581607 # Number of instructions committed 160system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed 161system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses 162system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 163system.cpu.num_func_calls 19311615 # number of times a function call or return occured 164system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls 165system.cpu.num_int_insts 448454356 # number of integer instructions 166system.cpu.num_fp_insts 16 # number of float instructions 167system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read 168system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written 169system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 170system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 171system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read 172system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written 173system.cpu.num_mem_refs 172745235 # number of memory refs 174system.cpu.num_load_insts 115884756 # Number of load instructions 175system.cpu.num_store_insts 56860479 # Number of store instructions 176system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 177system.cpu.num_busy_cycles 558724595.998000 # Number of busy cycles 178system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 179system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 180system.cpu.Branches 121548301 # Number of branches fetched 181system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 182system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction 183system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 184system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 185system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 187system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 188system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 189system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 190system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 191system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 205system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 206system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 207system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 208system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 209system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 210system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction 212system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction 213system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 214system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::total 548695378 # Class of executed instruction 216system.membus.trans_dist::ReadReq 630711790 # Transaction distribution 217system.membus.trans_dist::ReadResp 632200331 # Transaction distribution 218system.membus.trans_dist::WriteReq 54239306 # Transaction distribution 219system.membus.trans_dist::WriteResp 54239306 # Transaction distribution 220system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution 221system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution 222system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution 223system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution 224system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution 225system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) 226system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) 227system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) 228system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) 229system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) 230system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) 231system.membus.snoops 0 # Total snoops (count) 232system.membus.snoop_fanout::samples 687930749 # Request fanout histogram	12sim_insts 506581607 # Number of instructions simulated 13sim_ops 548694828 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory 18system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory 22system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) 38system.cpu_clk_domain.clock 500 # Clock period in ticks 39system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 58system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 59system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 60system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 68system.cpu.dtb.walker.walks 0 # Table walker walks requested 69system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.inst_hits 0 # ITB inst hits 77system.cpu.dtb.inst_misses 0 # ITB inst misses 78system.cpu.dtb.read_hits 0 # DTB read hits 79system.cpu.dtb.read_misses 0 # DTB read misses 80system.cpu.dtb.write_hits 0 # DTB write hits 81system.cpu.dtb.write_misses 0 # DTB write misses 82system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 84system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 85system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 86system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 87system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 88system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 89system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.dtb.read_accesses 0 # DTB read accesses 92system.cpu.dtb.write_accesses 0 # DTB write accesses 93system.cpu.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.dtb.hits 0 # DTB hits 95system.cpu.dtb.misses 0 # DTB misses 96system.cpu.dtb.accesses 0 # DTB accesses 97system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 106system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 107system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 108system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 109system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 110system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 121system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 122system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 123system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 124system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 125system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 548 # Number of system calls 156system.cpu.numCycles 558724596 # number of cpu cycles simulated 157system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 158system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 159system.cpu.committedInsts 506581607 # Number of instructions committed 160system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed 161system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses 162system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 163system.cpu.num_func_calls 19311615 # number of times a function call or return occured 164system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls 165system.cpu.num_int_insts 448454356 # number of integer instructions 166system.cpu.num_fp_insts 16 # number of float instructions 167system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read 168system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written 169system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 170system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 171system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read 172system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written 173system.cpu.num_mem_refs 172745235 # number of memory refs 174system.cpu.num_load_insts 115884756 # Number of load instructions 175system.cpu.num_store_insts 56860479 # Number of store instructions 176system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 177system.cpu.num_busy_cycles 558724595.998000 # Number of busy cycles 178system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 179system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 180system.cpu.Branches 121548301 # Number of branches fetched 181system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 182system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction 183system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 184system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 185system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 187system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 188system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 189system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 190system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 191system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 205system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 206system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 207system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 208system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 209system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 210system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction 212system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction 213system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 214system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::total 548695378 # Class of executed instruction 216system.membus.trans_dist::ReadReq 630711790 # Transaction distribution 217system.membus.trans_dist::ReadResp 632200331 # Transaction distribution 218system.membus.trans_dist::WriteReq 54239306 # Transaction distribution 219system.membus.trans_dist::WriteResp 54239306 # Transaction distribution 220system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution 221system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution 222system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution 223system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution 224system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution 225system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) 226system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) 227system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) 228system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) 229system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) 230system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) 231system.membus.snoops 0 # Total snoops (count) 232system.membus.snoop_fanout::samples 687930749 # Request fanout histogram
233system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram	233system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram
234system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram 235system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 236system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 237system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram	234system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram 235system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 236system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 237system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
238system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 239system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 240system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram 241system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram	238system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram 239system.membus.snoop_fanout::3 516611375 75.10% 100.00% # Request fanout histogram
242system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	240system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
243system.membus.snoop_fanout::min_value 4 # Request fanout histogram 244system.membus.snoop_fanout::max_value 5 # Request fanout histogram	241system.membus.snoop_fanout::min_value 2 # Request fanout histogram 242system.membus.snoop_fanout::max_value 3 # Request fanout histogram
245system.membus.snoop_fanout::total 687930749 # Request fanout histogram 246 247---------- End Simulation Statistics ----------	243system.membus.snoop_fanout::total 687930749 # Request fanout histogram 244 245---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.279362 # Number of seconds simulated
4sim_ticks 279362297500 # Number of ticks simulated
5final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1700410 # Simulator instruction rate (inst/s)
8host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 937717572 # Simulator tick rate (ticks/s)
10host_mem_usage 304668 # Number of bytes of host memory used
11host_seconds 297.92 # Real time elapsed on the host

7host_inst_rate 1941586 # Simulator instruction rate (inst/s)
8host_op_rate 2102994 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1070717412 # Simulator tick rate (ticks/s)
10host_mem_usage 304560 # Number of bytes of host memory used
11host_seconds 260.91 # Real time elapsed on the host

12sim_insts 506581607 # Number of instructions simulated
13sim_ops 548694828 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
18system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
22system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory
26system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s)
38system.cpu_clk_domain.clock 500 # Clock period in ticks
39system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
48system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
49system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
50system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
51system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
52system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
57system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
58system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
59system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
60system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
61system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
62system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
63system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
64system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
65system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
66system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
67system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
68system.cpu.dtb.walker.walks 0 # Table walker walks requested
69system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.inst_hits 0 # ITB inst hits
77system.cpu.dtb.inst_misses 0 # ITB inst misses
78system.cpu.dtb.read_hits 0 # DTB read hits
79system.cpu.dtb.read_misses 0 # DTB read misses
80system.cpu.dtb.write_hits 0 # DTB write hits
81system.cpu.dtb.write_misses 0 # DTB write misses
82system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
83system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
84system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
85system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
86system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
87system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
88system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
89system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
90system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
91system.cpu.dtb.read_accesses 0 # DTB read accesses
92system.cpu.dtb.write_accesses 0 # DTB write accesses
93system.cpu.dtb.inst_accesses 0 # ITB inst accesses
94system.cpu.dtb.hits 0 # DTB hits
95system.cpu.dtb.misses 0 # DTB misses
96system.cpu.dtb.accesses 0 # DTB accesses
97system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
106system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
107system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
108system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
109system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
110system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
111system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
115system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
116system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
117system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
118system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
119system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
120system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
121system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
122system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
123system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
124system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
125system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.inst_hits 0 # ITB inst hits
135system.cpu.itb.inst_misses 0 # ITB inst misses
136system.cpu.itb.read_hits 0 # DTB read hits
137system.cpu.itb.read_misses 0 # DTB read misses
138system.cpu.itb.write_hits 0 # DTB write hits
139system.cpu.itb.write_misses 0 # DTB write misses
140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 548 # Number of system calls
156system.cpu.numCycles 558724596 # number of cpu cycles simulated
157system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
158system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
159system.cpu.committedInsts 506581607 # Number of instructions committed
160system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed
161system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
162system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
163system.cpu.num_func_calls 19311615 # number of times a function call or return occured
164system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
165system.cpu.num_int_insts 448454356 # number of integer instructions
166system.cpu.num_fp_insts 16 # number of float instructions
167system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read
168system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
169system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
170system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
171system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read
172system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
173system.cpu.num_mem_refs 172745235 # number of memory refs
174system.cpu.num_load_insts 115884756 # Number of load instructions
175system.cpu.num_store_insts 56860479 # Number of store instructions
176system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
177system.cpu.num_busy_cycles 558724595.998000 # Number of busy cycles
178system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
179system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
180system.cpu.Branches 121548301 # Number of branches fetched
181system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
182system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction
183system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
184system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
185system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
186system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
187system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
188system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
189system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
190system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
191system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
192system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
193system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
194system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
195system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
196system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
197system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
198system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
199system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
200system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
201system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
202system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
203system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
204system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
205system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
206system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
207system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
208system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
209system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
210system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
211system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
212system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
213system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
214system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::total 548695378 # Class of executed instruction
216system.membus.trans_dist::ReadReq 630711790 # Transaction distribution
217system.membus.trans_dist::ReadResp 632200331 # Transaction distribution
218system.membus.trans_dist::WriteReq 54239306 # Transaction distribution
219system.membus.trans_dist::WriteResp 54239306 # Transaction distribution
220system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
221system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
222system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
223system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
224system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
225system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes)
226system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes)
227system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes)
228system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes)
229system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes)
230system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes)
231system.membus.snoops 0 # Total snoops (count)
232system.membus.snoop_fanout::samples 687930749 # Request fanout histogram

233system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram

233system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram

234system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
235system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
236system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
237system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram

238system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
239system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
240system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram
241system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram

238system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram
239system.membus.snoop_fanout::3 516611375 75.10% 100.00% # Request fanout histogram

242system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

240system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

243system.membus.snoop_fanout::min_value 4 # Request fanout histogram
244system.membus.snoop_fanout::max_value 5 # Request fanout histogram

241system.membus.snoop_fanout::min_value 2 # Request fanout histogram
242system.membus.snoop_fanout::max_value 3 # Request fanout histogram