1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.279362 # Number of seconds simulated
4sim_ticks 279362297500 # Number of ticks simulated
5final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 2087081 # Simulator instruction rate (inst/s)
8host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1150953174 # Simulator tick rate (ticks/s)
10host_mem_usage 299952 # Number of bytes of host memory used
11host_seconds 242.72 # Real time elapsed on the host
12sim_insts 506581607 # Number of instructions simulated
13sim_ops 548694828 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
18system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory
--- 10 unchanged lines hidden (view full) ---
30system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s)
38system.membus.trans_dist::ReadReq 630711790 # Transaction distribution
39system.membus.trans_dist::ReadResp 632200331 # Transaction distribution
40system.membus.trans_dist::WriteReq 54239306 # Transaction distribution
41system.membus.trans_dist::WriteResp 54239306 # Transaction distribution
42system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
43system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
44system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
45system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
46system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
47system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes)
48system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes)
49system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes)
50system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes)
51system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes)
52system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes)
53system.membus.snoops 0 # Total snoops (count)
54system.membus.snoop_fanout::samples 687930749 # Request fanout histogram
55system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram
56system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
57system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
58system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
59system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
60system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
61system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
62system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram
63system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram
64system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
65system.membus.snoop_fanout::min_value 4 # Request fanout histogram
66system.membus.snoop_fanout::max_value 5 # Request fanout histogram
67system.membus.snoop_fanout::total 687930749 # Request fanout histogram
68system.cpu_clk_domain.clock 500 # Clock period in ticks
69system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
70system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
71system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
72system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
73system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
74system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
75system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
76system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 5 unchanged lines hidden (view full) ---
82system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
83system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
84system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
85system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
86system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
87system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
88system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
89system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
90system.cpu.dtb.inst_hits 0 # ITB inst hits
91system.cpu.dtb.inst_misses 0 # ITB inst misses
92system.cpu.dtb.read_hits 0 # DTB read hits
93system.cpu.dtb.read_misses 0 # DTB read misses
94system.cpu.dtb.write_hits 0 # DTB write hits
95system.cpu.dtb.write_misses 0 # DTB write misses
96system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
97system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 5 unchanged lines hidden (view full) ---
103system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
104system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
105system.cpu.dtb.read_accesses 0 # DTB read accesses
106system.cpu.dtb.write_accesses 0 # DTB write accesses
107system.cpu.dtb.inst_accesses 0 # ITB inst accesses
108system.cpu.dtb.hits 0 # DTB hits
109system.cpu.dtb.misses 0 # DTB misses
110system.cpu.dtb.accesses 0 # DTB accesses
111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 5 unchanged lines hidden (view full) ---
124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
132system.cpu.itb.inst_hits 0 # ITB inst hits
133system.cpu.itb.inst_misses 0 # ITB inst misses
134system.cpu.itb.read_hits 0 # DTB read hits
135system.cpu.itb.read_misses 0 # DTB read misses
136system.cpu.itb.write_hits 0 # DTB write hits
137system.cpu.itb.write_misses 0 # DTB write misses
138system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
139system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 66 unchanged lines hidden (view full) ---
206system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
207system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
208system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
209system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
210system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
211system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
212system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
213system.cpu.op_class::total 548695378 # Class of executed instruction
214
215---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.279362 # Number of seconds simulated
4sim_ticks 279362297500 # Number of ticks simulated
5final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 2087081 # Simulator instruction rate (inst/s)
8host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1150953174 # Simulator tick rate (ticks/s)
10host_mem_usage 299952 # Number of bytes of host memory used
11host_seconds 242.72 # Real time elapsed on the host
12sim_insts 506581607 # Number of instructions simulated
13sim_ops 548694828 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
18system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory
--- 10 unchanged lines hidden (view full) ---
30system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s)
38system.membus.trans_dist::ReadReq 630711790 # Transaction distribution
39system.membus.trans_dist::ReadResp 632200331 # Transaction distribution
40system.membus.trans_dist::WriteReq 54239306 # Transaction distribution
41system.membus.trans_dist::WriteResp 54239306 # Transaction distribution
42system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
43system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
44system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
45system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
46system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
47system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes)
48system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes)
49system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes)
50system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes)
51system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes)
52system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes)
53system.membus.snoops 0 # Total snoops (count)
54system.membus.snoop_fanout::samples 687930749 # Request fanout histogram
55system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram
56system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
57system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
58system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
59system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
60system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
61system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
62system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram
63system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram
64system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
65system.membus.snoop_fanout::min_value 4 # Request fanout histogram
66system.membus.snoop_fanout::max_value 5 # Request fanout histogram
67system.membus.snoop_fanout::total 687930749 # Request fanout histogram
68system.cpu_clk_domain.clock 500 # Clock period in ticks
69system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
70system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
71system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
72system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
73system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
74system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
75system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
76system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 5 unchanged lines hidden (view full) ---
82system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
83system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
84system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
85system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
86system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
87system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
88system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
89system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
90system.cpu.dtb.inst_hits 0 # ITB inst hits
91system.cpu.dtb.inst_misses 0 # ITB inst misses
92system.cpu.dtb.read_hits 0 # DTB read hits
93system.cpu.dtb.read_misses 0 # DTB read misses
94system.cpu.dtb.write_hits 0 # DTB write hits
95system.cpu.dtb.write_misses 0 # DTB write misses
96system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
97system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 5 unchanged lines hidden (view full) ---
103system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
104system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
105system.cpu.dtb.read_accesses 0 # DTB read accesses
106system.cpu.dtb.write_accesses 0 # DTB write accesses
107system.cpu.dtb.inst_accesses 0 # ITB inst accesses
108system.cpu.dtb.hits 0 # DTB hits
109system.cpu.dtb.misses 0 # DTB misses
110system.cpu.dtb.accesses 0 # DTB accesses
111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 5 unchanged lines hidden (view full) ---
124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
132system.cpu.itb.inst_hits 0 # ITB inst hits
133system.cpu.itb.inst_misses 0 # ITB inst misses
134system.cpu.itb.read_hits 0 # DTB read hits
135system.cpu.itb.read_misses 0 # DTB read misses
136system.cpu.itb.write_hits 0 # DTB write hits
137system.cpu.itb.write_misses 0 # DTB write misses
138system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
139system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 66 unchanged lines hidden (view full) ---
206system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
207system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
208system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
209system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
210system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
211system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
212system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
213system.cpu.op_class::total 548695378 # Class of executed instruction
214
215---------- End Simulation Statistics ----------