| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.202724 # Number of seconds simulated 4sim_ticks 202723760000 # Number of ticks simulated 5final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.202742 # Number of seconds simulated 4sim_ticks 202741893000 # Number of ticks simulated 5final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 119496 # Simulator instruction rate (inst/s) 8host_op_rate 134724 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47946894 # Simulator tick rate (ticks/s) 10host_mem_usage 278932 # Number of bytes of host memory used 11host_seconds 4228.09 # Real time elapsed on the host | 7host_inst_rate 95210 # Simulator instruction rate (inst/s) 8host_op_rate 107343 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38205910 # Simulator tick rate (ticks/s) 10host_mem_usage 298452 # Number of bytes of host memory used 11host_seconds 5306.56 # Real time elapsed on the host |
| 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 569624283 # Number of ops (including micro ops) simulated | 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 569624283 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 148203 # Number of read requests accepted 38system.physmem.writeReqs 97674 # Number of write requests accepted 39system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue 43system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue | 14system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 148209 # Number of read requests accepted 38system.physmem.writeReqs 97655 # Number of write requests accepted 39system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue 43system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue |
| 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 48system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write 49system.physmem.perBankRdBursts::0 9589 # Per bank write bursts 50system.physmem.perBankRdBursts::1 9263 # Per bank write bursts 51system.physmem.perBankRdBursts::2 9230 # Per bank write bursts 52system.physmem.perBankRdBursts::3 8983 # Per bank write bursts 53system.physmem.perBankRdBursts::4 9781 # Per bank write bursts 54system.physmem.perBankRdBursts::5 9608 # Per bank write bursts 55system.physmem.perBankRdBursts::6 9123 # Per bank write bursts 56system.physmem.perBankRdBursts::7 8333 # Per bank write bursts 57system.physmem.perBankRdBursts::8 8801 # Per bank write bursts 58system.physmem.perBankRdBursts::9 8921 # Per bank write bursts 59system.physmem.perBankRdBursts::10 8939 # Per bank write bursts 60system.physmem.perBankRdBursts::11 9732 # Per bank write bursts 61system.physmem.perBankRdBursts::12 9670 # Per bank write bursts 62system.physmem.perBankRdBursts::13 9771 # Per bank write bursts | 48system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write 49system.physmem.perBankRdBursts::0 9585 # Per bank write bursts 50system.physmem.perBankRdBursts::1 9243 # Per bank write bursts 51system.physmem.perBankRdBursts::2 9257 # Per bank write bursts 52system.physmem.perBankRdBursts::3 8972 # Per bank write bursts 53system.physmem.perBankRdBursts::4 9761 # Per bank write bursts 54system.physmem.perBankRdBursts::5 9639 # Per bank write bursts 55system.physmem.perBankRdBursts::6 9125 # Per bank write bursts 56system.physmem.perBankRdBursts::7 8321 # Per bank write bursts 57system.physmem.perBankRdBursts::8 8799 # Per bank write bursts 58system.physmem.perBankRdBursts::9 8911 # Per bank write bursts 59system.physmem.perBankRdBursts::10 8951 # Per bank write bursts 60system.physmem.perBankRdBursts::11 9736 # Per bank write bursts 61system.physmem.perBankRdBursts::12 9644 # Per bank write bursts 62system.physmem.perBankRdBursts::13 9766 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::14 8945 # Per bank write bursts | 63system.physmem.perBankRdBursts::14 8945 # Per bank write bursts |
| 64system.physmem.perBankRdBursts::15 9431 # Per bank write bursts 65system.physmem.perBankWrBursts::0 6268 # Per bank write bursts 66system.physmem.perBankWrBursts::1 6168 # Per bank write bursts 67system.physmem.perBankWrBursts::2 6085 # Per bank write bursts 68system.physmem.perBankWrBursts::3 5885 # Per bank write bursts 69system.physmem.perBankWrBursts::4 6259 # Per bank write bursts 70system.physmem.perBankWrBursts::5 6263 # Per bank write bursts 71system.physmem.perBankWrBursts::6 6041 # Per bank write bursts 72system.physmem.perBankWrBursts::7 5560 # Per bank write bursts | 64system.physmem.perBankRdBursts::15 9461 # Per bank write bursts 65system.physmem.perBankWrBursts::0 6262 # Per bank write bursts 66system.physmem.perBankWrBursts::1 6160 # Per bank write bursts 67system.physmem.perBankWrBursts::2 6087 # Per bank write bursts 68system.physmem.perBankWrBursts::3 5881 # Per bank write bursts 69system.physmem.perBankWrBursts::4 6253 # Per bank write bursts 70system.physmem.perBankWrBursts::5 6276 # Per bank write bursts 71system.physmem.perBankWrBursts::6 6048 # Per bank write bursts 72system.physmem.perBankWrBursts::7 5555 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::8 5811 # Per bank write bursts | 73system.physmem.perBankWrBursts::8 5811 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::9 5905 # Per bank write bursts 75system.physmem.perBankWrBursts::10 5991 # Per bank write bursts 76system.physmem.perBankWrBursts::11 6522 # Per bank write bursts 77system.physmem.perBankWrBursts::12 6386 # Per bank write bursts 78system.physmem.perBankWrBursts::13 6332 # Per bank write bursts 79system.physmem.perBankWrBursts::14 6056 # Per bank write bursts 80system.physmem.perBankWrBursts::15 6134 # Per bank write bursts | 74system.physmem.perBankWrBursts::9 5907 # Per bank write bursts 75system.physmem.perBankWrBursts::10 5994 # Per bank write bursts 76system.physmem.perBankWrBursts::11 6518 # Per bank write bursts 77system.physmem.perBankWrBursts::12 6370 # Per bank write bursts 78system.physmem.perBankWrBursts::13 6328 # Per bank write bursts 79system.physmem.perBankWrBursts::14 6055 # Per bank write bursts 80system.physmem.perBankWrBursts::15 6145 # Per bank write bursts |
| 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 83system.physmem.totGap 202723740000 # Total gap between requests | 83system.physmem.totGap 202741873000 # Total gap between requests |
| 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) | 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 90system.physmem.readPktSize::6 148203 # Read request sizes (log2) | 90system.physmem.readPktSize::6 148209 # Read request sizes (log2) |
| 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) | 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 97system.physmem.writePktSize::6 97674 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see | 97system.physmem.writePktSize::6 97655 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see |
| 105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 130system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see | 130system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see |
| 133system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see | 133system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see |
| 134system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see | 134system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see |
| 141system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see | 141system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see |
| 142system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 162system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation | 142system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see 162system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation |
| 214system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation | 214system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation |
| 215system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation | 215system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation |
| 222system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation | 222system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation |
| 225system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation | |
| 226system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation | 225system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation |
| 228system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation | 227system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation |
| 234system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation | 233system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation |
| 235system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation | 234system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation |
| 236system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation | 235system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation |
| 239system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation 249system.physmem.totQLat 1733533250 # Total ticks spent queuing 250system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM 251system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers 252system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks 253system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst 254system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst | 238system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation 247system.physmem.totQLat 1735354000 # Total ticks spent queuing 248system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM 249system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers 250system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks 251system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst 252system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst |
| 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 253system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 256system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst | 254system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst |
| 257system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s | 255system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s 256system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s 257system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s |
| 260system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s | 258system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s |
| 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 0.61 # Data bus utilization in percentage 263system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes 265system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing | 259system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 260system.physmem.busUtil 0.61 # Data bus utilization in percentage 261system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads 262system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes 263system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing |
| 266system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing 267system.physmem.readRowHits 118615 # Number of row buffer hits during reads 268system.physmem.writeRowHits 57916 # Number of row buffer hits during writes 269system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads 270system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes 271system.physmem.avgGap 824492.49 # Average gap between requests 272system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined | 264system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing 265system.physmem.readRowHits 118629 # Number of row buffer hits during reads 266system.physmem.writeRowHits 57942 # Number of row buffer hits during writes 267system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads 268system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes 269system.physmem.avgGap 824609.84 # Average gap between requests 270system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined |
| 273system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state | 271system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state |
| 274system.membus.throughput 77623185 # Throughput (bytes/s) 275system.membus.trans_dist::ReadReq 46911 # Transaction distribution 276system.membus.trans_dist::ReadResp 46910 # Transaction distribution 277system.membus.trans_dist::Writeback 97674 # Transaction distribution 278system.membus.trans_dist::UpgradeReq 11 # Transaction distribution 279system.membus.trans_dist::UpgradeResp 11 # Transaction distribution 280system.membus.trans_dist::ReadExReq 101292 # Transaction distribution 281system.membus.trans_dist::ReadExResp 101292 # Transaction distribution 282system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) 283system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) 284system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) 285system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) 286system.membus.data_through_bus 15736064 # Total data (bytes) | 272system.membus.throughput 77612139 # Throughput (bytes/s) 273system.membus.trans_dist::ReadReq 46927 # Transaction distribution 274system.membus.trans_dist::ReadResp 46926 # Transaction distribution 275system.membus.trans_dist::Writeback 97655 # Transaction distribution 276system.membus.trans_dist::UpgradeReq 9 # Transaction distribution 277system.membus.trans_dist::UpgradeResp 9 # Transaction distribution 278system.membus.trans_dist::ReadExReq 101282 # Transaction distribution 279system.membus.trans_dist::ReadExResp 101282 # Transaction distribution 280system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes) 281system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes) 282system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes) 283system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes) 284system.membus.data_through_bus 15735232 # Total data (bytes) |
| 287system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 285system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 288system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) | 286system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks) |
| 289system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) | 287system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 290system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) | 288system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) |
| 291system.membus.respLayer1.utilization 0.7 # Layer utilization (%) | 289system.membus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 292system.cpu.branchPred.lookups 182800422 # Number of BP lookups 293system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted 294system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect 295system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups 296system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits | 290system.cpu.branchPred.lookups 182821881 # Number of BP lookups 291system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted 292system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect 293system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups 294system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits |
| 297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 295system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 298system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage 299system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. 300system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. | 296system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage 297system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target. 298system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions. |
| 301system.cpu.dtb.inst_hits 0 # ITB inst hits 302system.cpu.dtb.inst_misses 0 # ITB inst misses 303system.cpu.dtb.read_hits 0 # DTB read hits 304system.cpu.dtb.read_misses 0 # DTB read misses 305system.cpu.dtb.write_hits 0 # DTB write hits 306system.cpu.dtb.write_misses 0 # DTB write misses 307system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 308system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 336system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.itb.read_accesses 0 # DTB read accesses 338system.cpu.itb.write_accesses 0 # DTB write accesses 339system.cpu.itb.inst_accesses 0 # ITB inst accesses 340system.cpu.itb.hits 0 # DTB hits 341system.cpu.itb.misses 0 # DTB misses 342system.cpu.itb.accesses 0 # DTB accesses 343system.cpu.workload.num_syscalls 548 # Number of system calls | 299system.cpu.dtb.inst_hits 0 # ITB inst hits 300system.cpu.dtb.inst_misses 0 # ITB inst misses 301system.cpu.dtb.read_hits 0 # DTB read hits 302system.cpu.dtb.read_misses 0 # DTB read misses 303system.cpu.dtb.write_hits 0 # DTB write hits 304system.cpu.dtb.write_misses 0 # DTB write misses 305system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 306system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 334system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.inst_accesses 0 # ITB inst accesses 338system.cpu.itb.hits 0 # DTB hits 339system.cpu.itb.misses 0 # DTB misses 340system.cpu.itb.accesses 0 # DTB accesses 341system.cpu.workload.num_syscalls 548 # Number of system calls |
| 344system.cpu.numCycles 405447521 # number of cpu cycles simulated | 342system.cpu.numCycles 405483787 # number of cpu cycles simulated |
| 345system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 347system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss 348system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed 349system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered 350system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken 351system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked 352system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing 353system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked 354system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 355system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps 356system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR 357system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched 358system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed 359system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) | 345system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss 346system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed 347system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered 348system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken 349system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked 350system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing 351system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked 352system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 353system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps 354system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR 355system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched 356system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed 357system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total) |
| 362system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 360system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 363system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) | 361system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total) |
| 372system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 370system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 375system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle 377system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle 378system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle 379system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked 380system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running 381system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking 382system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing 383system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch 384system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction 385system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode 386system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode 387system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing 388system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle 389system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking 390system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst 391system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running 392system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking 393system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename 394system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full 395system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full 396system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full 397system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers 398system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed 399system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made 400system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups 401system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups | 373system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle 375system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle 376system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle 377system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked 378system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running 379system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking 380system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing 381system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch 382system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction 383system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode 384system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode 385system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing 386system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle 387system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking 388system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst 389system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running 390system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking 391system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename 392system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full 393system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full 394system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full 395system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers 396system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed 397system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made 398system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups 399system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups |
| 402system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed | 400system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed |
| 403system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing 404system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed 405system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed 406system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer 407system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. 408system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. 409system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. 410system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. 411system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) 412system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ 413system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued 414system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued 415system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling 416system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph 417system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed 418system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle | 401system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing 402system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed 403system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed 404system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer 405system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit. 406system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit. 407system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads. 408system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores. 409system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec) 410system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ 411system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued 412system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued 413system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling 414system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph 415system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed 416system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle |
| 421system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 419system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 422system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle | 420system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle |
| 431system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 429system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 434system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle | 432system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle |
| 435system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 433system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 436system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available | 434system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available |
| 437system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available 438system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 457system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available | 435system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 455system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available |
| 465system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available 466system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available | 463system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available 464system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available |
| 467system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 468system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 469system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 465system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 466system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 467system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 470system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued 471system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued | 468system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued 469system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued |
| 472system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued | 470system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued |
| 473system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued | 471system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued |
| 474system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 491system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued | 472system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 489system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued |
| 499system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued 500system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued | 497system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued 498system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued |
| 501system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 502system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 499system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 500system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 503system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued 504system.cpu.iq.rate 1.641040 # Inst issue rate 505system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested 506system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) 507system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads 508system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes 509system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses 510system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads | 501system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued 502system.cpu.iq.rate 1.640858 # Inst issue rate 503system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested 504system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) 505system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads 506system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes 507system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses 508system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads |
| 511system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes 512system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 509system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes 510system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 513system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses 514system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses 515system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores | 511system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses 512system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses 513system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores |
| 516system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 514system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 517system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed 518system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed 519system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations 520system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed | 515system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed 516system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed 517system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations 518system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed |
| 521system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 522system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 519system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 520system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 523system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled 524system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked | 521system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled 522system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked |
| 525system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 523system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 526system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing 527system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking 528system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking 529system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ 530system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch 531system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions 532system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions 533system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions 534system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall 535system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall 536system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations 537system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly 538system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly 539system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute 540system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions 541system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed 542system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute | 524system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing 525system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking 526system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking 527system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ 528system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch 529system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions 530system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions 531system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions 532system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall 533system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall 534system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations 535system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly 536system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly 537system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute 538system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions 539system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed 540system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute |
| 543system.cpu.iew.exec_swp 0 # number of swp insts executed | 541system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 544system.cpu.iew.exec_nop 1559155 # number of nop insts executed 545system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed 546system.cpu.iew.exec_branches 138495848 # Number of branches executed 547system.cpu.iew.exec_stores 62487508 # Number of stores executed 548system.cpu.iew.exec_rate 1.617786 # Inst execution rate 549system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit 550system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back 551system.cpu.iew.wb_producers 374730881 # num instructions producing a value 552system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value | 542system.cpu.iew.exec_nop 1558919 # number of nop insts executed 543system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed 544system.cpu.iew.exec_branches 138505177 # Number of branches executed 545system.cpu.iew.exec_stores 62475461 # Number of stores executed 546system.cpu.iew.exec_rate 1.617619 # Inst execution rate 547system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit 548system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back 549system.cpu.iew.wb_producers 374710129 # num instructions producing a value 550system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value |
| 553system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 551system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 554system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle 555system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back | 552system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle 553system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back |
| 556system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 554system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 557system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit | 555system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit |
| 558system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards | 556system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards |
| 559system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted 560system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle | 557system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted 558system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle |
| 563system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 561system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 564system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle | 562system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle |
| 573system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 571system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 576system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle | 574system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle |
| 577system.cpu.commit.committedInsts 506581607 # Number of instructions committed 578system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 579system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 580system.cpu.commit.refs 182890032 # Number of memory references committed 581system.cpu.commit.loads 126029555 # Number of loads committed 582system.cpu.commit.membars 1488542 # Number of memory barriers committed 583system.cpu.commit.branches 121548301 # Number of branches committed 584system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 585system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 586system.cpu.commit.function_calls 9757362 # Number of function calls committed. | 575system.cpu.commit.committedInsts 506581607 # Number of instructions committed 576system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 577system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 578system.cpu.commit.refs 182890032 # Number of memory references committed 579system.cpu.commit.loads 126029555 # Number of loads committed 580system.cpu.commit.membars 1488542 # Number of memory barriers committed 581system.cpu.commit.branches 121548301 # Number of branches committed 582system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 583system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 584system.cpu.commit.function_calls 9757362 # Number of function calls committed. |
| 587system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached | 585system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached |
| 588system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 586system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 589system.cpu.rob.rob_reads 1104768676 # The number of ROB reads 590system.cpu.rob.rob_writes 1548495185 # The number of ROB writes 591system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself 592system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling | 587system.cpu.rob.rob_reads 1104828701 # The number of ROB reads 588system.cpu.rob.rob_writes 1548619548 # The number of ROB writes 589system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself 590system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 593system.cpu.committedInsts 505237723 # Number of Instructions Simulated 594system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 595system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated | 591system.cpu.committedInsts 505237723 # Number of Instructions Simulated 592system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 593system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated |
| 596system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction 597system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads 598system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle 599system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads 600system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads 601system.cpu.int_regfile_writes 752016829 # number of integer regfile writes | 594system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction 595system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads 596system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle 597system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads 598system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads 599system.cpu.int_regfile_writes 752019512 # number of integer regfile writes |
| 602system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 600system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 603system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads | 601system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads |
| 604system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes | 602system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes |
| 605system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) 606system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution 613system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) 614system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) 615system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) 616system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) 617system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) 619system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) 620system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) 621system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) | 603system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s) 604system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution 611system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes) 614system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes) 615system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes) 616system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes) 617system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes) 618system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes) 619system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks) |
| 622system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) | 620system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 623system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) | 621system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks) |
| 624system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 622system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 625system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) | 623system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks) |
| 626system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) | 624system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 627system.cpu.icache.tags.replacements 15073 # number of replacements 628system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use 629system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. 630system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. 631system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. | 625system.cpu.icache.tags.replacements 15017 # number of replacements 626system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use 627system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks. 628system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks. 629system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks. |
| 632system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 630system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 633system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor 634system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy 635system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy 636system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits 637system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits 638system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits 639system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits 640system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits 641system.cpu.icache.overall_hits::total 114510320 # number of overall hits 642system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses 643system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses 644system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses 645system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses 646system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses 647system.cpu.icache.overall_misses::total 21232 # number of overall misses 648system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles 649system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles 650system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles 651system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles 652system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles 653system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles 654system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) 655system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) 656system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses 657system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses 658system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses 659system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses 660system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses 661system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses 662system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses 663system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses 664system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses 665system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses 666system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency 667system.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency 668system.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency 669system.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency 670system.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency 671system.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency 672system.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked | 631system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor 632system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy 633system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy 634system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits 635system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits 636system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits 637system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits 638system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits 639system.cpu.icache.overall_hits::total 114523215 # number of overall hits 640system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses 641system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses 642system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses 643system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses 644system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses 645system.cpu.icache.overall_misses::total 21116 # number of overall misses 646system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles 647system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles 648system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles 649system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles 650system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles 651system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles 652system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses) 653system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses) 654system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses 655system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses 656system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses 657system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses 658system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses 659system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses 660system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses 661system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses 662system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses 663system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses 664system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency 665system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency 666system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency 667system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency 668system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency 669system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency 670system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked |
| 673system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 671system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 674system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked | 672system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked |
| 675system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 673system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 676system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked | 674system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked |
| 677system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 678system.cpu.icache.fast_writes 0 # number of fast writes performed 679system.cpu.icache.cache_copies 0 # number of cache copies performed | 675system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu.icache.fast_writes 0 # number of fast writes performed 677system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 680system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4215 # number of ReadReq MSHR hits 681system.cpu.icache.ReadReq_mshr_hits::total 4215 # number of ReadReq MSHR hits 682system.cpu.icache.demand_mshr_hits::cpu.inst 4215 # number of demand (read+write) MSHR hits 683system.cpu.icache.demand_mshr_hits::total 4215 # number of demand (read+write) MSHR hits 684system.cpu.icache.overall_mshr_hits::cpu.inst 4215 # number of overall MSHR hits 685system.cpu.icache.overall_mshr_hits::total 4215 # number of overall MSHR hits 686system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17017 # number of ReadReq MSHR misses 687system.cpu.icache.ReadReq_mshr_misses::total 17017 # number of ReadReq MSHR misses 688system.cpu.icache.demand_mshr_misses::cpu.inst 17017 # number of demand (read+write) MSHR misses 689system.cpu.icache.demand_mshr_misses::total 17017 # number of demand (read+write) MSHR misses 690system.cpu.icache.overall_mshr_misses::cpu.inst 17017 # number of overall MSHR misses 691system.cpu.icache.overall_mshr_misses::total 17017 # number of overall MSHR misses 692system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 416333765 # number of ReadReq MSHR miss cycles 693system.cpu.icache.ReadReq_mshr_miss_latency::total 416333765 # number of ReadReq MSHR miss cycles 694system.cpu.icache.demand_mshr_miss_latency::cpu.inst 416333765 # number of demand (read+write) MSHR miss cycles 695system.cpu.icache.demand_mshr_miss_latency::total 416333765 # number of demand (read+write) MSHR miss cycles 696system.cpu.icache.overall_mshr_miss_latency::cpu.inst 416333765 # number of overall MSHR miss cycles 697system.cpu.icache.overall_mshr_miss_latency::total 416333765 # number of overall MSHR miss cycles 698system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses 699system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses 700system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses 701system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses 702system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses 703system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24465.755715 # average ReadReq mshr miss latency 705system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24465.755715 # average ReadReq mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency 707system.cpu.icache.demand_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency 709system.cpu.icache.overall_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency | 678system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits 679system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits 680system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits 681system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits 682system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits 683system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits 684system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses 685system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses 686system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses 687system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses 688system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses 689system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses 690system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles 691system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles 692system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles 696system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses 697system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses 698system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses 699system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses 700system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses 701system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses 702system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency 704system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency 706system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency |
| 710system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 708system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 711system.cpu.l2cache.tags.replacements 115458 # number of replacements 712system.cpu.l2cache.tags.tagsinuse 27089.677773 # Cycle average of tags in use 713system.cpu.l2cache.tags.total_refs 1781255 # Total number of references to valid blocks. 714system.cpu.l2cache.tags.sampled_refs 146702 # Sample count of references to valid blocks. 715system.cpu.l2cache.tags.avg_refs 12.141995 # Average number of references to valid blocks. 716system.cpu.l2cache.tags.warmup_cycle 102544951000 # Cycle when the warmup percentage was hit. 717system.cpu.l2cache.tags.occ_blocks::writebacks 23009.492156 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_blocks::cpu.inst 363.276336 # Average occupied blocks per requestor 719system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.909282 # Average occupied blocks per requestor 720system.cpu.l2cache.tags.occ_percent::writebacks 0.702194 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011086 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_percent::cpu.data 0.113431 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_percent::total 0.826711 # Average percentage of cache occupancy 724system.cpu.l2cache.ReadReq_hits::cpu.inst 13516 # number of ReadReq hits 725system.cpu.l2cache.ReadReq_hits::cpu.data 804499 # number of ReadReq hits 726system.cpu.l2cache.ReadReq_hits::total 818015 # number of ReadReq hits 727system.cpu.l2cache.Writeback_hits::writebacks 1111085 # number of Writeback hits 728system.cpu.l2cache.Writeback_hits::total 1111085 # number of Writeback hits 729system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits 730system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits 731system.cpu.l2cache.ReadExReq_hits::cpu.data 247576 # number of ReadExReq hits 732system.cpu.l2cache.ReadExReq_hits::total 247576 # number of ReadExReq hits 733system.cpu.l2cache.demand_hits::cpu.inst 13516 # number of demand (read+write) hits 734system.cpu.l2cache.demand_hits::cpu.data 1052075 # number of demand (read+write) hits 735system.cpu.l2cache.demand_hits::total 1065591 # number of demand (read+write) hits 736system.cpu.l2cache.overall_hits::cpu.inst 13516 # number of overall hits 737system.cpu.l2cache.overall_hits::cpu.data 1052075 # number of overall hits 738system.cpu.l2cache.overall_hits::total 1065591 # number of overall hits 739system.cpu.l2cache.ReadReq_misses::cpu.inst 3400 # number of ReadReq misses 740system.cpu.l2cache.ReadReq_misses::cpu.data 43535 # number of ReadReq misses 741system.cpu.l2cache.ReadReq_misses::total 46935 # number of ReadReq misses 742system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses 743system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses 744system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses 745system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses 746system.cpu.l2cache.demand_misses::cpu.inst 3400 # number of demand (read+write) misses 747system.cpu.l2cache.demand_misses::cpu.data 144828 # number of demand (read+write) misses 748system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses 749system.cpu.l2cache.overall_misses::cpu.inst 3400 # number of overall misses 750system.cpu.l2cache.overall_misses::cpu.data 144828 # number of overall misses 751system.cpu.l2cache.overall_misses::total 148228 # number of overall misses 752system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263796250 # number of ReadReq miss cycles 753system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3483365500 # number of ReadReq miss cycles 754system.cpu.l2cache.ReadReq_miss_latency::total 3747161750 # number of ReadReq miss cycles 755system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles 756system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles 757system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7556144249 # number of ReadExReq miss cycles 758system.cpu.l2cache.ReadExReq_miss_latency::total 7556144249 # number of ReadExReq miss cycles 759system.cpu.l2cache.demand_miss_latency::cpu.inst 263796250 # number of demand (read+write) miss cycles 760system.cpu.l2cache.demand_miss_latency::cpu.data 11039509749 # number of demand (read+write) miss cycles 761system.cpu.l2cache.demand_miss_latency::total 11303305999 # number of demand (read+write) miss cycles 762system.cpu.l2cache.overall_miss_latency::cpu.inst 263796250 # number of overall miss cycles 763system.cpu.l2cache.overall_miss_latency::cpu.data 11039509749 # number of overall miss cycles 764system.cpu.l2cache.overall_miss_latency::total 11303305999 # number of overall miss cycles 765system.cpu.l2cache.ReadReq_accesses::cpu.inst 16916 # number of ReadReq accesses(hits+misses) 766system.cpu.l2cache.ReadReq_accesses::cpu.data 848034 # number of ReadReq accesses(hits+misses) 767system.cpu.l2cache.ReadReq_accesses::total 864950 # number of ReadReq accesses(hits+misses) 768system.cpu.l2cache.Writeback_accesses::writebacks 1111085 # number of Writeback accesses(hits+misses) 769system.cpu.l2cache.Writeback_accesses::total 1111085 # number of Writeback accesses(hits+misses) 770system.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) 771system.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) 772system.cpu.l2cache.ReadExReq_accesses::cpu.data 348869 # number of ReadExReq accesses(hits+misses) 773system.cpu.l2cache.ReadExReq_accesses::total 348869 # number of ReadExReq accesses(hits+misses) 774system.cpu.l2cache.demand_accesses::cpu.inst 16916 # number of demand (read+write) accesses 775system.cpu.l2cache.demand_accesses::cpu.data 1196903 # number of demand (read+write) accesses 776system.cpu.l2cache.demand_accesses::total 1213819 # number of demand (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.inst 16916 # number of overall (read+write) accesses 778system.cpu.l2cache.overall_accesses::cpu.data 1196903 # number of overall (read+write) accesses 779system.cpu.l2cache.overall_accesses::total 1213819 # number of overall (read+write) accesses 780system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200993 # miss rate for ReadReq accesses 781system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051336 # miss rate for ReadReq accesses 782system.cpu.l2cache.ReadReq_miss_rate::total 0.054263 # miss rate for ReadReq accesses 783system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119048 # miss rate for UpgradeReq accesses 784system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119048 # miss rate for UpgradeReq accesses 785system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290347 # miss rate for ReadExReq accesses 786system.cpu.l2cache.ReadExReq_miss_rate::total 0.290347 # miss rate for ReadExReq accesses 787system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200993 # miss rate for demand accesses 788system.cpu.l2cache.demand_miss_rate::cpu.data 0.121002 # miss rate for demand accesses 789system.cpu.l2cache.demand_miss_rate::total 0.122117 # miss rate for demand accesses 790system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200993 # miss rate for overall accesses 791system.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses 792system.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses 793system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency 794system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency 795system.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency 796system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency 797system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency 798system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency 799system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency 802system.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency | 709system.cpu.l2cache.tags.replacements 115463 # number of replacements 710system.cpu.l2cache.tags.tagsinuse 27089.747444 # Cycle average of tags in use 711system.cpu.l2cache.tags.total_refs 1781862 # Total number of references to valid blocks. 712system.cpu.l2cache.tags.sampled_refs 146718 # Sample count of references to valid blocks. 713system.cpu.l2cache.tags.avg_refs 12.144808 # Average number of references to valid blocks. 714system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit. 715system.cpu.l2cache.tags.occ_blocks::writebacks 23009.564484 # Average occupied blocks per requestor 716system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.930795 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.data 3719.252164 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 # Average percentage of cache occupancy 719system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy 722system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits 723system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits 724system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits 725system.cpu.l2cache.Writeback_hits::writebacks 1110997 # number of Writeback hits 726system.cpu.l2cache.Writeback_hits::total 1110997 # number of Writeback hits 727system.cpu.l2cache.UpgradeReq_hits::cpu.data 57 # number of UpgradeReq hits 728system.cpu.l2cache.UpgradeReq_hits::total 57 # number of UpgradeReq hits 729system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits 730system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits 731system.cpu.l2cache.demand_hits::cpu.inst 13491 # number of demand (read+write) hits 732system.cpu.l2cache.demand_hits::cpu.data 1051959 # number of demand (read+write) hits 733system.cpu.l2cache.demand_hits::total 1065450 # number of demand (read+write) hits 734system.cpu.l2cache.overall_hits::cpu.inst 13491 # number of overall hits 735system.cpu.l2cache.overall_hits::cpu.data 1051959 # number of overall hits 736system.cpu.l2cache.overall_hits::total 1065450 # number of overall hits 737system.cpu.l2cache.ReadReq_misses::cpu.inst 3369 # number of ReadReq misses 738system.cpu.l2cache.ReadReq_misses::cpu.data 43584 # number of ReadReq misses 739system.cpu.l2cache.ReadReq_misses::total 46953 # number of ReadReq misses 740system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses 741system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses 742system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses 743system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses 744system.cpu.l2cache.demand_misses::cpu.inst 3369 # number of demand (read+write) misses 745system.cpu.l2cache.demand_misses::cpu.data 144867 # number of demand (read+write) misses 746system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses 747system.cpu.l2cache.overall_misses::cpu.inst 3369 # number of overall misses 748system.cpu.l2cache.overall_misses::cpu.data 144867 # number of overall misses 749system.cpu.l2cache.overall_misses::total 148236 # number of overall misses 750system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260130750 # number of ReadReq miss cycles 751system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3496707000 # number of ReadReq miss cycles 752system.cpu.l2cache.ReadReq_miss_latency::total 3756837750 # number of ReadReq miss cycles 753system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7547454999 # number of ReadExReq miss cycles 754system.cpu.l2cache.ReadExReq_miss_latency::total 7547454999 # number of ReadExReq miss cycles 755system.cpu.l2cache.demand_miss_latency::cpu.inst 260130750 # number of demand (read+write) miss cycles 756system.cpu.l2cache.demand_miss_latency::cpu.data 11044161999 # number of demand (read+write) miss cycles 757system.cpu.l2cache.demand_miss_latency::total 11304292749 # number of demand (read+write) miss cycles 758system.cpu.l2cache.overall_miss_latency::cpu.inst 260130750 # number of overall miss cycles 759system.cpu.l2cache.overall_miss_latency::cpu.data 11044161999 # number of overall miss cycles 760system.cpu.l2cache.overall_miss_latency::total 11304292749 # number of overall miss cycles 761system.cpu.l2cache.ReadReq_accesses::cpu.inst 16860 # number of ReadReq accesses(hits+misses) 762system.cpu.l2cache.ReadReq_accesses::cpu.data 847968 # number of ReadReq accesses(hits+misses) 763system.cpu.l2cache.ReadReq_accesses::total 864828 # number of ReadReq accesses(hits+misses) 764system.cpu.l2cache.Writeback_accesses::writebacks 1110997 # number of Writeback accesses(hits+misses) 765system.cpu.l2cache.Writeback_accesses::total 1110997 # number of Writeback accesses(hits+misses) 766system.cpu.l2cache.UpgradeReq_accesses::cpu.data 65 # number of UpgradeReq accesses(hits+misses) 767system.cpu.l2cache.UpgradeReq_accesses::total 65 # number of UpgradeReq accesses(hits+misses) 768system.cpu.l2cache.ReadExReq_accesses::cpu.data 348858 # number of ReadExReq accesses(hits+misses) 769system.cpu.l2cache.ReadExReq_accesses::total 348858 # number of ReadExReq accesses(hits+misses) 770system.cpu.l2cache.demand_accesses::cpu.inst 16860 # number of demand (read+write) accesses 771system.cpu.l2cache.demand_accesses::cpu.data 1196826 # number of demand (read+write) accesses 772system.cpu.l2cache.demand_accesses::total 1213686 # number of demand (read+write) accesses 773system.cpu.l2cache.overall_accesses::cpu.inst 16860 # number of overall (read+write) accesses 774system.cpu.l2cache.overall_accesses::cpu.data 1196826 # number of overall (read+write) accesses 775system.cpu.l2cache.overall_accesses::total 1213686 # number of overall (read+write) accesses 776system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.199822 # miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051398 # miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_miss_rate::total 0.054292 # miss rate for ReadReq accesses 779system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.123077 # miss rate for UpgradeReq accesses 780system.cpu.l2cache.UpgradeReq_miss_rate::total 0.123077 # miss rate for UpgradeReq accesses 781system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290327 # miss rate for ReadExReq accesses 782system.cpu.l2cache.ReadExReq_miss_rate::total 0.290327 # miss rate for ReadExReq accesses 783system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199822 # miss rate for demand accesses 784system.cpu.l2cache.demand_miss_rate::cpu.data 0.121043 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses 786system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199822 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::cpu.data 0.121043 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses 789system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77213.045414 # average ReadReq miss latency 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80229.143722 # average ReadReq miss latency 791system.cpu.l2cache.ReadReq_avg_miss_latency::total 80012.730816 # average ReadReq miss latency 792system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74518.477918 # average ReadExReq miss latency 793system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74518.477918 # average ReadExReq miss latency 794system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency 796system.cpu.l2cache.demand_avg_miss_latency::total 76258.754614 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency 798system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::total 76258.754614 # average overall miss latency |
| 806system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.l2cache.fast_writes 0 # number of fast writes performed 813system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 800system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 801system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 804system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 806system.cpu.l2cache.fast_writes 0 # number of fast writes performed 807system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 814system.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks 815system.cpu.l2cache.writebacks::total 97674 # number of writebacks | 808system.cpu.l2cache.writebacks::writebacks 97655 # number of writebacks 809system.cpu.l2cache.writebacks::total 97655 # number of writebacks |
| 816system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits | 810system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits |
| 817system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits 818system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits | 811system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 812system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits |
| 819system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits | 813system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits |
| 820system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits 821system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits | 814system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 815system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits |
| 822system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits | 816system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits |
| 823system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits 824system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 825system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses 826system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses 827system.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses 828system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses 829system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses 830system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses 831system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses 832system.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses 833system.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses 834system.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses 835system.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses 836system.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses 837system.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses 838system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles 839system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles 840system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles 841system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles 842system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles 843system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles 844system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles 845system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles 846system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles 847system.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles 849system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles 850system.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles 851system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses 852system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses 853system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses 854system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119048 # mshr miss rate for UpgradeReq accesses 855system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119048 # mshr miss rate for UpgradeReq accesses 856system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290347 # mshr miss rate for ReadExReq accesses 857system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290347 # mshr miss rate for ReadExReq accesses 858system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for demand accesses 859system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses 860system.cpu.l2cache.demand_mshr_miss_rate::total 0.122097 # mshr miss rate for demand accesses 861system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for overall accesses 862system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses 863system.cpu.l2cache.overall_mshr_miss_rate::total 0.122097 # mshr miss rate for overall accesses 864system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency 865system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency 866system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency | 817system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 818system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits 819system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3364 # number of ReadReq MSHR misses 820system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43563 # number of ReadReq MSHR misses 821system.cpu.l2cache.ReadReq_mshr_misses::total 46927 # number of ReadReq MSHR misses 822system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses 823system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses 825system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses 826system.cpu.l2cache.demand_mshr_misses::cpu.inst 3364 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::cpu.data 144846 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.demand_mshr_misses::total 148210 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.inst 3364 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.data 144846 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::total 148210 # number of overall MSHR misses 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 217499500 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2949813250 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3167312750 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262853501 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262853501 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217499500 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9212666751 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::total 9430166251 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217499500 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9212666751 # number of overall MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::total 9430166251 # number of overall MSHR miss cycles 845system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for ReadReq accesses 846system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051373 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054262 # mshr miss rate for ReadReq accesses 848system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.123077 # mshr miss rate for UpgradeReq accesses 849system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.123077 # mshr miss rate for UpgradeReq accesses 850system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290327 # mshr miss rate for ReadExReq accesses 851system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290327 # mshr miss rate for ReadExReq accesses 852system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for demand accesses 853system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for demand accesses 854system.cpu.l2cache.demand_mshr_miss_rate::total 0.122116 # mshr miss rate for demand accesses 855system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for overall accesses 856system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for overall accesses 857system.cpu.l2cache.overall_mshr_miss_rate::total 0.122116 # mshr miss rate for overall accesses 858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64655.023781 # average ReadReq mshr miss latency 859system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67713.730689 # average ReadReq mshr miss latency 860system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67494.464807 # average ReadReq mshr miss latency |
| 867system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 868system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 861system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 862system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 869system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency 870system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency 871system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency 872system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency 873system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency 874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency 875system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency 876system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency | 863system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency 864system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency 865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency 868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency 870system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency |
| 877system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 871system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 878system.cpu.dcache.tags.replacements 1192807 # number of replacements 879system.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use 880system.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks. 881system.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks. 882system.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks. | 872system.cpu.dcache.tags.replacements 1192730 # number of replacements 873system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use 874system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks. 875system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks. 876system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks. |
| 883system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. | 877system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. |
| 884system.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor 885system.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy 886system.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy 887system.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits 888system.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits 889system.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits 890system.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits 891system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits 892system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits | 878system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor 879system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy 880system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy 881system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits 882system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits 883system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits 884system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits 885system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits 886system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits |
| 893system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 894system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits | 887system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 888system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits |
| 895system.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits 896system.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits 897system.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits 898system.cpu.dcache.overall_hits::total 187221113 # number of overall hits 899system.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses 900system.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses 901system.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses 902system.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses 903system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses 904system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses 905system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses 906system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses 907system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses 908system.cpu.dcache.overall_misses::total 4954972 # number of overall misses 909system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles 910system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles 911system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles 912system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles 913system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles 914system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles 915system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles 916system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles 917system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles 918system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles 919system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) 920system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) | 889system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits 890system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits 891system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits 892system.cpu.dcache.overall_hits::total 187223724 # number of overall hits 893system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses 894system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses 895system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses 896system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses 897system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses 898system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses 899system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses 900system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses 901system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses 902system.cpu.dcache.overall_misses::total 4951929 # number of overall misses 903system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles 904system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles 905system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles 906system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles 907system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles 908system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles 909system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles 910system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles 911system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles 912system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles 913system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses) 914system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses) |
| 921system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 922system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) | 915system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 916system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) |
| 923system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) 924system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) | 917system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses) 918system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses) |
| 925system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 926system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) | 919system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 920system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) |
| 927system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses 928system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses 929system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses 930system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses 931system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses 932system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses 933system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses 934system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses 935system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses 936system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses 937system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses 938system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses 939system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses 940system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses 941system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency 942system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency 943system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency 944system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency 945system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency 946system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency 947system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency 948system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency 949system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency 950system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency 951system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked 952system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked 953system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked | 921system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses 922system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses 923system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses 924system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses 925system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses 926system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses 927system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses 928system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses 929system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses 930system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses 931system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses 932system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses 933system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses 934system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses 935system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency 936system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency 937system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency 938system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency 939system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency 940system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency 941system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency 942system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency 943system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency 944system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency 945system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked 946system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked 947system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked |
| 954system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked | 948system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked |
| 955system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked 956system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked | 949system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked 950system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked |
| 957system.cpu.dcache.fast_writes 0 # number of fast writes performed 958system.cpu.dcache.cache_copies 0 # number of cache copies performed | 951system.cpu.dcache.fast_writes 0 # number of fast writes performed 952system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 959system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks 960system.cpu.dcache.writebacks::total 1111085 # number of writebacks 961system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits 962system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits 963system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits 964system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits 965system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits 966system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits 967system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits 968system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits 969system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits 970system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits 971system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses 972system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses 973system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses 974system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses 975system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses 976system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses 977system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses 978system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses 979system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles 980system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles 981system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles 982system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles 983system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles 984system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles 985system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles 986system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles | 953system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks 954system.cpu.dcache.writebacks::total 1110997 # number of writebacks 955system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits 956system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits 957system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits 958system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits 959system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits 960system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits 961system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits 962system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits 963system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits 964system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits 965system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses 966system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses 967system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses 968system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses 969system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses 970system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses 971system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses 972system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses 973system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles 974system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles 975system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles 976system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles 977system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles 978system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles 979system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles 980system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles |
| 987system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses 988system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses | 981system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses 982system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses |
| 989system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses 990system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses 991system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses 992system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses 993system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses 994system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses 995system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency 996system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency 997system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency 998system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency 999system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency 1000system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency 1001system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency 1002system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency | 983system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses 984system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses 985system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses 986system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses 987system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses 988system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses 989system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency 990system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency 991system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency 992system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency 993system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency 994system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency 995system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency 996system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency |
| 1003system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1004 1005---------- End Simulation Statistics ---------- | 997system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 998 999---------- End Simulation Statistics ---------- |