| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.199986 # Number of seconds simulated 4sim_ticks 199986318000 # Number of ticks simulated 5final_tick 199986318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.202265 # Number of seconds simulated 4sim_ticks 202264702500 # Number of ticks simulated 5final_tick 202264702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 53828 # Simulator instruction rate (inst/s) 8host_op_rate 60688 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 21306693 # Simulator tick rate (ticks/s) 10host_mem_usage 292380 # Number of bytes of host memory used 11host_seconds 9386.08 # Real time elapsed on the host | 7host_inst_rate 152154 # Simulator instruction rate (inst/s) 8host_op_rate 171544 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60912686 # Simulator tick rate (ticks/s) 10host_mem_usage 250588 # Number of bytes of host memory used 11host_seconds 3320.57 # Real time elapsed on the host |
| 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 569624283 # Number of ops (including micro ops) simulated | 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 569624283 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 216704 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9268096 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9484800 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 216704 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 216704 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6249408 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6249408 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3386 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 144814 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 148200 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 97647 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 97647 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1083594 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 46343650 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 47427244 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1083594 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1083594 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 31249178 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 31249178 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 31249178 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1083594 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 46343650 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 78676422 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 148200 # Total number of read requests seen 38system.physmem.writeReqs 97647 # Total number of write requests seen 39system.physmem.cpureqs 245864 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 9484800 # Total number of bytes read from memory 41system.physmem.bytesWritten 6249408 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 9484800 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 6249408 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q | 14system.physmem.bytes_read::cpu.inst 216000 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9260928 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9476928 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 216000 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 216000 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6246016 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6246016 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3375 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 144702 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 148077 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 97594 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 97594 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1067908 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 45786180 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 46854087 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1067908 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1067908 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 30880405 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 30880405 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 30880405 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1067908 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 45786180 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 77734493 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 148078 # Total number of read requests seen 38system.physmem.writeReqs 97594 # Total number of write requests seen 39system.physmem.cpureqs 245687 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 9476928 # Total number of bytes read from memory 41system.physmem.bytesWritten 6246016 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 9476928 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 6246016 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q |
| 45system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed | 45system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed |
| 46system.physmem.perBankRdReqs::0 9181 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 9616 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 9533 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 9493 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 9413 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 9073 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 9057 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 9296 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 8842 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 9072 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 9240 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 9010 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 9027 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 9230 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 5960 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 5978 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 6283 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 6480 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 6185 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 6216 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 6227 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 6024 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 6210 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5897 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6108 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 6001 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 5939 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 6059 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 6112 # Track writes on a per bank basis | 46system.physmem.perBankRdReqs::0 9583 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 9207 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 9281 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 8971 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 9774 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 9643 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 9100 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 8322 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 8802 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 8932 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 9735 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 9616 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 9782 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 8932 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 9434 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 6098 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5882 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 6246 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 6280 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 5558 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5810 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5899 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5989 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 6350 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 6340 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 6045 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 6130 # Track writes on a per bank basis |
| 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 79system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry 80system.physmem.totGap 199986294500 # Total gap between requests | 79system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry 80system.physmem.totGap 202264683000 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 148200 # Categorize read packet sizes | 87system.physmem.readPktSize::6 148078 # Categorize read packet sizes |
| 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes | 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 94system.physmem.writePktSize::6 97647 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 138069 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 9399 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see | 94system.physmem.writePktSize::6 97594 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 138541 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 8888 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 127system.physmem.wrQLenPdf::0 4210 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 4229 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 4235 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 4237 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 4237 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 4237 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 4238 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see | 127system.physmem.wrQLenPdf::0 4223 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 4236 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 4236 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 4235 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see |
| 156system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see | 156system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see |
| 157system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 159system.physmem.totQLat 1719312500 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 4989180000 # Sum of mem lat for all requests 161system.physmem.totBusLat 740610000 # Total cycles spent in databus access 162system.physmem.totBankLat 2529257500 # Total cycles spent in bank access 163system.physmem.avgQLat 11607.41 # Average queueing delay per request 164system.physmem.avgBankLat 17075.50 # Average bank access latency per request | 157system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see 159system.physmem.bytesPerActivate::samples 55927 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::mean 281.047508 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::gmean 134.123063 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::stdev 688.589570 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::64-65 27857 49.81% 49.81% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::128-129 10311 18.44% 68.25% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::192-193 4742 8.48% 76.73% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::256-257 2859 5.11% 81.84% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::320-321 1799 3.22% 85.05% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::384-385 1160 2.07% 87.13% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::448-449 842 1.51% 88.63% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::512-513 665 1.19% 89.82% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::576-577 468 0.84% 90.66% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::640-641 376 0.67% 91.33% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::704-705 271 0.48% 91.82% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::768-769 239 0.43% 92.24% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::832-833 201 0.36% 92.60% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::896-897 180 0.32% 92.92% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::960-961 171 0.31% 93.23% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1024-1025 177 0.32% 93.55% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 169 0.30% 93.85% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 170 0.30% 94.15% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 147 0.26% 94.42% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1280-1281 156 0.28% 94.69% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1344-1345 167 0.30% 94.99% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1408-1409 250 0.45% 95.44% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1472-1473 974 1.74% 97.18% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1536-1537 239 0.43% 97.61% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1600-1601 147 0.26% 97.87% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1664-1665 173 0.31% 98.18% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1728-1729 101 0.18% 98.36% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1792-1793 105 0.19% 98.55% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1856-1857 71 0.13% 98.68% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1920-1921 56 0.10% 98.78% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1984-1985 36 0.06% 98.84% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2048-2049 46 0.08% 98.92% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2112-2113 27 0.05% 98.97% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2176-2177 25 0.04% 99.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2240-2241 21 0.04% 99.05% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2304-2305 22 0.04% 99.09% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2368-2369 17 0.03% 99.12% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2432-2433 12 0.02% 99.15% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2496-2497 14 0.03% 99.17% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2560-2561 11 0.02% 99.19% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2624-2625 12 0.02% 99.21% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2688-2689 9 0.02% 99.23% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2752-2753 11 0.02% 99.25% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2816-2817 10 0.02% 99.27% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2880-2881 4 0.01% 99.27% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.28% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3008-3009 8 0.01% 99.30% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3072-3073 7 0.01% 99.31% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3136-3137 3 0.01% 99.31% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3200-3201 5 0.01% 99.32% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3328-3329 7 0.01% 99.34% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.35% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.36% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3584-3585 9 0.02% 99.37% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.38% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3712-3713 4 0.01% 99.39% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.39% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.40% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.40% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.40% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4032-4033 4 0.01% 99.41% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4096-4097 3 0.01% 99.41% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.43% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.44% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.45% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.45% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::5056-5057 4 0.01% 99.46% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.47% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.48% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.48% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.49% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.49% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.49% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.49% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.50% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.51% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.51% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.51% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.52% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.52% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.52% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.52% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.52% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.53% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.53% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.54% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::total 55927 # Bytes accessed per row activation 271system.physmem.totQLat 1510568250 # Total cycles spent in queuing delays 272system.physmem.totMemAccLat 4629837000 # Sum of mem lat for all requests 273system.physmem.totBusLat 740065000 # Total cycles spent in databus access 274system.physmem.totBankLat 2379203750 # Total cycles spent in bank access 275system.physmem.avgQLat 10205.65 # Average queueing delay per request 276system.physmem.avgBankLat 16074.29 # Average bank access latency per request |
| 165system.physmem.avgBusLat 5000.00 # Average bus latency per request | 277system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 166system.physmem.avgMemAccLat 33682.91 # Average memory access latency 167system.physmem.avgRdBW 47.43 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 47.43 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s | 278system.physmem.avgMemAccLat 31279.93 # Average memory access latency 279system.physmem.avgRdBW 46.85 # Average achieved read bandwidth in MB/s 280system.physmem.avgWrBW 30.88 # Average achieved write bandwidth in MB/s 281system.physmem.avgConsumedRdBW 46.85 # Average consumed read bandwidth in MB/s 282system.physmem.avgConsumedWrBW 30.88 # Average consumed write bandwidth in MB/s |
| 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 172system.physmem.busUtil 0.61 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.02 # Average read queue length over time | 283system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 284system.physmem.busUtil 0.61 # Data bus utilization in percentage 285system.physmem.avgRdQLen 0.02 # Average read queue length over time |
| 174system.physmem.avgWrQLen 8.37 # Average write queue length over time 175system.physmem.readRowHits 125428 # Number of row buffer hits during reads 176system.physmem.writeRowHits 52865 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 54.14 # Row buffer hit rate for writes 179system.physmem.avgGap 813458.35 # Average gap between requests 180system.cpu.branchPred.lookups 182823475 # Number of BP lookups 181system.cpu.branchPred.condPredicted 143127293 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 7270205 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 92181207 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 87235258 # Number of BTB hits | 286system.physmem.avgWrQLen 8.55 # Average write queue length over time 287system.physmem.readRowHits 130620 # Number of row buffer hits during reads 288system.physmem.writeRowHits 59055 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 60.51 # Row buffer hit rate for writes 291system.physmem.avgGap 823311.91 # Average gap between requests 292system.membus.throughput 77734493 # Throughput (bytes/s) 293system.membus.trans_dist::ReadReq 46795 # Transaction distribution 294system.membus.trans_dist::ReadResp 46794 # Transaction distribution 295system.membus.trans_dist::Writeback 97594 # Transaction distribution 296system.membus.trans_dist::UpgradeReq 9 # Transaction distribution 297system.membus.trans_dist::UpgradeResp 9 # Transaction distribution 298system.membus.trans_dist::ReadExReq 101283 # Transaction distribution 299system.membus.trans_dist::ReadExResp 101283 # Transaction distribution 300system.membus.pkt_count_system.cpu.l2cache.mem_side 393767 # Packet count per connected master and slave (bytes) 301system.membus.pkt_count 393767 # Packet count per connected master and slave (bytes) 302system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15722944 # Cumulative packet size per connected master and slave (bytes) 303system.membus.tot_pkt_size 15722944 # Cumulative packet size per connected master and slave (bytes) 304system.membus.data_through_bus 15722944 # Total data (bytes) 305system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 306system.membus.reqLayer0.occupancy 1079125750 # Layer occupancy (ticks) 307system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 308system.membus.respLayer1.occupancy 1399666492 # Layer occupancy (ticks) 309system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 310system.cpu.branchPred.lookups 182795351 # Number of BP lookups 311system.cpu.branchPred.condPredicted 143107535 # Number of conditional branches predicted 312system.cpu.branchPred.condIncorrect 7264975 # Number of conditional branches incorrect 313system.cpu.branchPred.BTBLookups 93466227 # Number of BTB lookups 314system.cpu.branchPred.BTBHits 87209092 # Number of BTB hits |
| 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 186system.cpu.branchPred.BTBHitPct 94.634537 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 12683949 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 116293 # Number of incorrect RAS predictions. | 316system.cpu.branchPred.BTBHitPct 93.305459 # BTB Hit Percentage 317system.cpu.branchPred.usedRAS 12678830 # Number of times the RAS was used to get a target. 318system.cpu.branchPred.RASInCorrect 116057 # Number of incorrect RAS predictions. |
| 189system.cpu.dtb.inst_hits 0 # ITB inst hits 190system.cpu.dtb.inst_misses 0 # ITB inst misses 191system.cpu.dtb.read_hits 0 # DTB read hits 192system.cpu.dtb.read_misses 0 # DTB read misses 193system.cpu.dtb.write_hits 0 # DTB write hits 194system.cpu.dtb.write_misses 0 # DTB write misses 195system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 196system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 224system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 225system.cpu.itb.read_accesses 0 # DTB read accesses 226system.cpu.itb.write_accesses 0 # DTB write accesses 227system.cpu.itb.inst_accesses 0 # ITB inst accesses 228system.cpu.itb.hits 0 # DTB hits 229system.cpu.itb.misses 0 # DTB misses 230system.cpu.itb.accesses 0 # DTB accesses 231system.cpu.workload.num_syscalls 548 # Number of system calls | 319system.cpu.dtb.inst_hits 0 # ITB inst hits 320system.cpu.dtb.inst_misses 0 # ITB inst misses 321system.cpu.dtb.read_hits 0 # DTB read hits 322system.cpu.dtb.read_misses 0 # DTB read misses 323system.cpu.dtb.write_hits 0 # DTB write hits 324system.cpu.dtb.write_misses 0 # DTB write misses 325system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 326system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.itb.read_accesses 0 # DTB read accesses 356system.cpu.itb.write_accesses 0 # DTB write accesses 357system.cpu.itb.inst_accesses 0 # ITB inst accesses 358system.cpu.itb.hits 0 # DTB hits 359system.cpu.itb.misses 0 # DTB misses 360system.cpu.itb.accesses 0 # DTB accesses 361system.cpu.workload.num_syscalls 548 # Number of system calls |
| 232system.cpu.numCycles 399972637 # number of cpu cycles simulated | 362system.cpu.numCycles 404529406 # number of cpu cycles simulated |
| 233system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 234system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 235system.cpu.fetch.icacheStallCycles 119392306 # Number of cycles fetch is stalled on an Icache miss 236system.cpu.fetch.Insts 761693904 # Number of instructions fetch has processed 237system.cpu.fetch.Branches 182823475 # Number of branches that fetch encountered 238system.cpu.fetch.predictedBranches 99919207 # Number of branches that fetch has predicted taken 239system.cpu.fetch.Cycles 170173986 # Number of cycles fetch has run and was not squashing or blocked 240system.cpu.fetch.SquashCycles 35705843 # Number of cycles fetch has spent squashing 241system.cpu.fetch.BlockedCycles 75415774 # Number of cycles fetch has spent blocked 242system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 243system.cpu.fetch.PendingTrapStallCycles 554 # Number of stall cycles due to pending traps 244system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR 245system.cpu.fetch.CacheLines 114545284 # Number of cache lines fetched 246system.cpu.fetch.IcacheSquashes 2440918 # Number of outstanding Icache misses that were squashed 247system.cpu.fetch.rateDist::samples 392617380 # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::mean 2.175996 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::stdev 2.990505 # Number of instructions fetched each cycle (Total) | 365system.cpu.fetch.icacheStallCycles 119370904 # Number of cycles fetch is stalled on an Icache miss 366system.cpu.fetch.Insts 761561247 # Number of instructions fetch has processed 367system.cpu.fetch.Branches 182795351 # Number of branches that fetch encountered 368system.cpu.fetch.predictedBranches 99887922 # Number of branches that fetch has predicted taken 369system.cpu.fetch.Cycles 170134463 # Number of cycles fetch has run and was not squashing or blocked 370system.cpu.fetch.SquashCycles 35678521 # Number of cycles fetch has spent squashing 371system.cpu.fetch.BlockedCycles 77150212 # Number of cycles fetch has spent blocked 372system.cpu.fetch.MiscStallCycles 98 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 373system.cpu.fetch.PendingTrapStallCycles 455 # Number of stall cycles due to pending traps 374system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR 375system.cpu.fetch.CacheLines 114522843 # Number of cache lines fetched 376system.cpu.fetch.IcacheSquashes 2439505 # Number of outstanding Icache misses that were squashed 377system.cpu.fetch.rateDist::samples 394266586 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::mean 2.166435 # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::stdev 2.987414 # Number of instructions fetched each cycle (Total) |
| 250system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 380system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 251system.cpu.fetch.rateDist::0 222455990 56.66% 56.66% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::1 14183959 3.61% 60.27% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::2 22907819 5.83% 66.11% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::3 22738821 5.79% 71.90% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::4 20904503 5.32% 77.22% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::5 11594029 2.95% 80.18% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::6 13063211 3.33% 83.50% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::7 12002083 3.06% 86.56% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::8 52766965 13.44% 100.00% # Number of instructions fetched each cycle (Total) | 381system.cpu.fetch.rateDist::0 224144737 56.85% 56.85% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::1 14179887 3.60% 60.45% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::2 22893161 5.81% 66.25% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::3 22745024 5.77% 72.02% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::4 20894474 5.30% 77.32% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::5 11598135 2.94% 80.26% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::6 13057002 3.31% 83.58% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::7 11992402 3.04% 86.62% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::8 52761764 13.38% 100.00% # Number of instructions fetched each cycle (Total) |
| 260system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 390system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 263system.cpu.fetch.rateDist::total 392617380 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.branchRate 0.457090 # Number of branch fetches per cycle 265system.cpu.fetch.rate 1.904365 # Number of inst fetches per cycle 266system.cpu.decode.IdleCycles 129046079 # Number of cycles decode is idle 267system.cpu.decode.BlockedCycles 70945312 # Number of cycles decode is blocked 268system.cpu.decode.RunCycles 158884174 # Number of cycles decode is running 269system.cpu.decode.UnblockCycles 6181299 # Number of cycles decode is unblocking 270system.cpu.decode.SquashCycles 27560516 # Number of cycles decode is squashing 271system.cpu.decode.BranchResolved 26130325 # Number of times decode resolved a branch 272system.cpu.decode.BranchMispred 76946 # Number of times decode detected a branch misprediction 273system.cpu.decode.DecodedInsts 825690179 # Number of instructions handled by decode 274system.cpu.decode.SquashedInsts 295591 # Number of squashed instructions handled by decode 275system.cpu.rename.SquashCycles 27560516 # Number of cycles rename is squashing 276system.cpu.rename.IdleCycles 135633063 # Number of cycles rename is idle 277system.cpu.rename.BlockCycles 9642191 # Number of cycles rename is blocking 278system.cpu.rename.serializeStallCycles 46463188 # count of cycles rename stalled for serializing inst 279system.cpu.rename.RunCycles 158301033 # Number of cycles rename is running 280system.cpu.rename.UnblockCycles 15017389 # Number of cycles rename is unblocking 281system.cpu.rename.RenamedInsts 800753920 # Number of instructions processed by rename 282system.cpu.rename.ROBFullEvents 1207 # Number of times rename has blocked due to ROB full 283system.cpu.rename.IQFullEvents 3038316 # Number of times rename has blocked due to IQ full 284system.cpu.rename.LSQFullEvents 8776785 # Number of times rename has blocked due to LSQ full 285system.cpu.rename.FullRegisterEvents 223 # Number of times there has been no free registers 286system.cpu.rename.RenamedOperands 954449423 # Number of destination operands rename has renamed 287system.cpu.rename.RenameLookups 3501232166 # Number of register rename lookups that rename has made 288system.cpu.rename.int_rename_lookups 3501230756 # Number of integer rename lookups 289system.cpu.rename.fp_rename_lookups 1410 # Number of floating rename lookups | 393system.cpu.fetch.rateDist::total 394266586 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.branchRate 0.451872 # Number of branch fetches per cycle 395system.cpu.fetch.rate 1.882586 # Number of inst fetches per cycle 396system.cpu.decode.IdleCycles 129061208 # Number of cycles decode is idle 397system.cpu.decode.BlockedCycles 72641827 # Number of cycles decode is blocked 398system.cpu.decode.RunCycles 158799298 # Number of cycles decode is running 399system.cpu.decode.UnblockCycles 6227893 # Number of cycles decode is unblocking 400system.cpu.decode.SquashCycles 27536360 # Number of cycles decode is squashing 401system.cpu.decode.BranchResolved 26125699 # Number of times decode resolved a branch 402system.cpu.decode.BranchMispred 76608 # Number of times decode detected a branch misprediction 403system.cpu.decode.DecodedInsts 825532349 # Number of instructions handled by decode 404system.cpu.decode.SquashedInsts 291942 # Number of squashed instructions handled by decode 405system.cpu.rename.SquashCycles 27536360 # Number of cycles rename is squashing 406system.cpu.rename.IdleCycles 135656827 # Number of cycles rename is idle 407system.cpu.rename.BlockCycles 10155018 # Number of cycles rename is blocking 408system.cpu.rename.serializeStallCycles 47441534 # count of cycles rename stalled for serializing inst 409system.cpu.rename.RunCycles 158249633 # Number of cycles rename is running 410system.cpu.rename.UnblockCycles 15227214 # Number of cycles rename is unblocking 411system.cpu.rename.RenamedInsts 800580004 # Number of instructions processed by rename 412system.cpu.rename.ROBFullEvents 1401 # Number of times rename has blocked due to ROB full 413system.cpu.rename.IQFullEvents 3056484 # Number of times rename has blocked due to IQ full 414system.cpu.rename.LSQFullEvents 8970861 # Number of times rename has blocked due to LSQ full 415system.cpu.rename.FullRegisterEvents 208 # Number of times there has been no free registers 416system.cpu.rename.RenamedOperands 954230970 # Number of destination operands rename has renamed 417system.cpu.rename.RenameLookups 3500428728 # Number of register rename lookups that rename has made 418system.cpu.rename.int_rename_lookups 3500427418 # Number of integer rename lookups 419system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups |
| 290system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed | 420system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed |
| 291system.cpu.rename.UndoneMaps 288197132 # Number of HB maps that are undone due to squashing 292system.cpu.rename.serializingInsts 2293078 # count of serializing insts renamed 293system.cpu.rename.tempSerializingInsts 2293075 # count of temporary serializing insts renamed 294system.cpu.rename.skidInsts 41509096 # count of insts added to the skid buffer 295system.cpu.memDep0.insertedLoads 170293066 # Number of loads inserted to the mem dependence unit. 296system.cpu.memDep0.insertedStores 73496638 # Number of stores inserted to the mem dependence unit. 297system.cpu.memDep0.conflictingLoads 28553519 # Number of conflicting loads. 298system.cpu.memDep0.conflictingStores 15543647 # Number of conflicting stores. 299system.cpu.iq.iqInstsAdded 755184516 # Number of instructions added to the IQ (excludes non-spec) 300system.cpu.iq.iqNonSpecInstsAdded 3775403 # Number of non-speculative instructions added to the IQ 301system.cpu.iq.iqInstsIssued 665423791 # Number of instructions issued 302system.cpu.iq.iqSquashedInstsIssued 1392561 # Number of squashed instructions issued 303system.cpu.iq.iqSquashedInstsExamined 187499467 # Number of squashed instructions iterated over during squash; mainly for profiling 304system.cpu.iq.iqSquashedOperandsExamined 480050290 # Number of squashed operands that are examined and possibly removed from graph 305system.cpu.iq.iqSquashedNonSpecRemoved 797771 # Number of squashed non-spec instructions that were removed 306system.cpu.iq.issued_per_cycle::samples 392617380 # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::mean 1.694840 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::stdev 1.736370 # Number of insts issued each cycle | 421system.cpu.rename.UndoneMaps 287978679 # Number of HB maps that are undone due to squashing 422system.cpu.rename.serializingInsts 2292969 # count of serializing insts renamed 423system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed 424system.cpu.rename.skidInsts 41852604 # count of insts added to the skid buffer 425system.cpu.memDep0.insertedLoads 170255884 # Number of loads inserted to the mem dependence unit. 426system.cpu.memDep0.insertedStores 73472812 # Number of stores inserted to the mem dependence unit. 427system.cpu.memDep0.conflictingLoads 28582851 # Number of conflicting loads. 428system.cpu.memDep0.conflictingStores 15746500 # Number of conflicting stores. 429system.cpu.iq.iqInstsAdded 755022174 # Number of instructions added to the IQ (excludes non-spec) 430system.cpu.iq.iqNonSpecInstsAdded 3775311 # Number of non-speculative instructions added to the IQ 431system.cpu.iq.iqInstsIssued 665301102 # Number of instructions issued 432system.cpu.iq.iqSquashedInstsIssued 1380692 # Number of squashed instructions issued 433system.cpu.iq.iqSquashedInstsExamined 187339157 # Number of squashed instructions iterated over during squash; mainly for profiling 434system.cpu.iq.iqSquashedOperandsExamined 479760666 # Number of squashed operands that are examined and possibly removed from graph 435system.cpu.iq.iqSquashedNonSpecRemoved 797679 # Number of squashed non-spec instructions that were removed 436system.cpu.iq.issued_per_cycle::samples 394266586 # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::mean 1.687440 # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::stdev 1.735091 # Number of insts issued each cycle |
| 309system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 439system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 310system.cpu.iq.issued_per_cycle::0 137266683 34.96% 34.96% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::1 69764327 17.77% 52.73% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::2 71469341 18.20% 70.93% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::3 53405229 13.60% 84.54% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::4 31142767 7.93% 92.47% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::5 16033920 4.08% 96.55% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::6 8799646 2.24% 98.79% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::7 2917185 0.74% 99.54% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::8 1818282 0.46% 100.00% # Number of insts issued each cycle | 440system.cpu.iq.issued_per_cycle::0 138747020 35.19% 35.19% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::1 69982581 17.75% 52.94% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::2 71470863 18.13% 71.07% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::3 53423224 13.55% 84.62% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::4 31142023 7.90% 92.52% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::5 16022250 4.06% 96.58% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::6 8747194 2.22% 98.80% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::7 2906831 0.74% 99.54% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::8 1824600 0.46% 100.00% # Number of insts issued each cycle |
| 319system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 449system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 322system.cpu.iq.issued_per_cycle::total 392617380 # Number of insts issued each cycle | 452system.cpu.iq.issued_per_cycle::total 394266586 # Number of insts issued each cycle |
| 323system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 453system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 324system.cpu.iq.fu_full::IntAlu 479464 4.97% 4.97% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available 326system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available 353system.cpu.iq.fu_full::MemRead 6557477 68.01% 72.98% # attempts to use FU when none available 354system.cpu.iq.fu_full::MemWrite 2605087 27.02% 100.00% # attempts to use FU when none available | 454system.cpu.iq.fu_full::IntAlu 480987 5.01% 5.01% # attempts to use FU when none available 455system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available 456system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available 457system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available 458system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available 459system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available 483system.cpu.iq.fu_full::MemRead 6546208 68.16% 73.16% # attempts to use FU when none available 484system.cpu.iq.fu_full::MemWrite 2577471 26.84% 100.00% # attempts to use FU when none available |
| 355system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 356system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 357system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 485system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 486system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 487system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 358system.cpu.iq.FU_type_0::IntAlu 447824113 67.30% 67.30% # Type of FU issued 359system.cpu.iq.FU_type_0::IntMult 383504 0.06% 67.36% # Type of FU issued | 488system.cpu.iq.FU_type_0::IntAlu 447771708 67.30% 67.30% # Type of FU issued 489system.cpu.iq.FU_type_0::IntMult 383310 0.06% 67.36% # Type of FU issued |
| 360system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued | 490system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued |
| 361system.cpu.iq.FU_type_0::FloatAdd 98 0.00% 67.36% # Type of FU issued | 491system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued |
| 362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued | 492system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 493system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 494system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 509system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued |
| 387system.cpu.iq.FU_type_0::MemRead 153397745 23.05% 90.41% # Type of FU issued 388system.cpu.iq.FU_type_0::MemWrite 63818328 9.59% 100.00% # Type of FU issued | 517system.cpu.iq.FU_type_0::MemRead 153352638 23.05% 90.41% # Type of FU issued 518system.cpu.iq.FU_type_0::MemWrite 63793353 9.59% 100.00% # Type of FU issued |
| 389system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 519system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 520system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 391system.cpu.iq.FU_type_0::total 665423791 # Type of FU issued 392system.cpu.iq.rate 1.663673 # Inst issue rate 393system.cpu.iq.fu_busy_cnt 9642028 # FU busy when requested 394system.cpu.iq.fu_busy_rate 0.014490 # FU busy rate (busy events/executed inst) 395system.cpu.iq.int_inst_queue_reads 1734499320 # Number of integer instruction queue reads 396system.cpu.iq.int_inst_queue_writes 947266498 # Number of integer instruction queue writes 397system.cpu.iq.int_inst_queue_wakeup_accesses 646124282 # Number of integer instruction queue wakeup accesses 398system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads 399system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes | 521system.cpu.iq.FU_type_0::total 665301102 # Type of FU issued 522system.cpu.iq.rate 1.644630 # Inst issue rate 523system.cpu.iq.fu_busy_cnt 9604666 # FU busy when requested 524system.cpu.iq.fu_busy_rate 0.014437 # FU busy rate (busy events/executed inst) 525system.cpu.iq.int_inst_queue_reads 1735853933 # Number of integer instruction queue reads 526system.cpu.iq.int_inst_queue_writes 946943275 # Number of integer instruction queue writes 527system.cpu.iq.int_inst_queue_wakeup_accesses 646028886 # Number of integer instruction queue wakeup accesses 528system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads 529system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes |
| 400system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 530system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 401system.cpu.iq.int_alu_accesses 675065702 # Number of integer alu accesses 402system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses 403system.cpu.iew.lsq.thread0.forwLoads 8583068 # Number of loads that had data forwarded from stores | 531system.cpu.iq.int_alu_accesses 674905659 # Number of integer alu accesses 532system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses 533system.cpu.iew.lsq.thread0.forwLoads 8552862 # Number of loads that had data forwarded from stores |
| 404system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 534system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 405system.cpu.iew.lsq.thread0.squashedLoads 44263511 # Number of loads squashed 406system.cpu.iew.lsq.thread0.ignoredResponses 42384 # Number of memory responses ignored because the instruction is squashed 407system.cpu.iew.lsq.thread0.memOrderViolation 811218 # Number of memory ordering violations 408system.cpu.iew.lsq.thread0.squashedStores 16636161 # Number of stores squashed | 535system.cpu.iew.lsq.thread0.squashedLoads 44226329 # Number of loads squashed 536system.cpu.iew.lsq.thread0.ignoredResponses 41059 # Number of memory responses ignored because the instruction is squashed 537system.cpu.iew.lsq.thread0.memOrderViolation 810522 # Number of memory ordering violations 538system.cpu.iew.lsq.thread0.squashedStores 16612335 # Number of stores squashed |
| 409system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 410system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 539system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 540system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 411system.cpu.iew.lsq.thread0.rescheduledLoads 19502 # Number of loads that were rescheduled 412system.cpu.iew.lsq.thread0.cacheBlocked 4251 # Number of times an access to memory failed due to the cache being blocked | 541system.cpu.iew.lsq.thread0.rescheduledLoads 19495 # Number of loads that were rescheduled 542system.cpu.iew.lsq.thread0.cacheBlocked 7104 # Number of times an access to memory failed due to the cache being blocked |
| 413system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 543system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 414system.cpu.iew.iewSquashCycles 27560516 # Number of cycles IEW is squashing 415system.cpu.iew.iewBlockCycles 5033845 # Number of cycles IEW is blocking 416system.cpu.iew.iewUnblockCycles 374098 # Number of cycles IEW is unblocking 417system.cpu.iew.iewDispatchedInsts 760518622 # Number of instructions dispatched to IQ 418system.cpu.iew.iewDispSquashedInsts 1117950 # Number of squashed instructions skipped by dispatch 419system.cpu.iew.iewDispLoadInsts 170293066 # Number of dispatched load instructions 420system.cpu.iew.iewDispStoreInsts 73496638 # Number of dispatched store instructions 421system.cpu.iew.iewDispNonSpecInsts 2286861 # Number of dispatched non-speculative instructions 422system.cpu.iew.iewIQFullEvents 218393 # Number of times the IQ has become full, causing a stall 423system.cpu.iew.iewLSQFullEvents 11953 # Number of times the LSQ has become full, causing a stall 424system.cpu.iew.memOrderViolationEvents 811218 # Number of memory order violations 425system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly 426system.cpu.iew.predictedNotTakenIncorrect 4001637 # Number of branches that were predicted not taken incorrectly 427system.cpu.iew.branchMispredicts 8344571 # Number of branch mispredicts detected at execute 428system.cpu.iew.iewExecutedInsts 655982546 # Number of executed instructions 429system.cpu.iew.iewExecLoadInsts 150110737 # Number of load instructions executed 430system.cpu.iew.iewExecSquashedInsts 9441245 # Number of squashed instructions skipped in execute | 544system.cpu.iew.iewSquashCycles 27536360 # Number of cycles IEW is squashing 545system.cpu.iew.iewBlockCycles 5290664 # Number of cycles IEW is blocking 546system.cpu.iew.iewUnblockCycles 387489 # Number of cycles IEW is unblocking 547system.cpu.iew.iewDispatchedInsts 760356154 # Number of instructions dispatched to IQ 548system.cpu.iew.iewDispSquashedInsts 1118953 # Number of squashed instructions skipped by dispatch 549system.cpu.iew.iewDispLoadInsts 170255884 # Number of dispatched load instructions 550system.cpu.iew.iewDispStoreInsts 73472812 # Number of dispatched store instructions 551system.cpu.iew.iewDispNonSpecInsts 2286769 # Number of dispatched non-speculative instructions 552system.cpu.iew.iewIQFullEvents 219863 # Number of times the IQ has become full, causing a stall 553system.cpu.iew.iewLSQFullEvents 12400 # Number of times the LSQ has become full, causing a stall 554system.cpu.iew.memOrderViolationEvents 810522 # Number of memory order violations 555system.cpu.iew.predictedTakenIncorrect 4337912 # Number of branches that were predicted taken incorrectly 556system.cpu.iew.predictedNotTakenIncorrect 4002750 # Number of branches that were predicted not taken incorrectly 557system.cpu.iew.branchMispredicts 8340662 # Number of branch mispredicts detected at execute 558system.cpu.iew.iewExecutedInsts 655875003 # Number of executed instructions 559system.cpu.iew.iewExecLoadInsts 150077564 # Number of load instructions executed 560system.cpu.iew.iewExecSquashedInsts 9426099 # Number of squashed instructions skipped in execute |
| 431system.cpu.iew.exec_swp 0 # number of swp insts executed | 561system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 432system.cpu.iew.exec_nop 1558703 # number of nop insts executed 433system.cpu.iew.exec_refs 212627196 # number of memory reference insts executed 434system.cpu.iew.exec_branches 138502657 # Number of branches executed 435system.cpu.iew.exec_stores 62516459 # Number of stores executed 436system.cpu.iew.exec_rate 1.640069 # Inst execution rate 437system.cpu.iew.wb_sent 651101010 # cumulative count of insts sent to commit 438system.cpu.iew.wb_count 646124298 # cumulative count of insts written-back 439system.cpu.iew.wb_producers 374793054 # num instructions producing a value 440system.cpu.iew.wb_consumers 646490687 # num instructions consuming a value | 562system.cpu.iew.exec_nop 1558669 # number of nop insts executed 563system.cpu.iew.exec_refs 212570616 # number of memory reference insts executed 564system.cpu.iew.exec_branches 138493352 # Number of branches executed 565system.cpu.iew.exec_stores 62493052 # Number of stores executed 566system.cpu.iew.exec_rate 1.621328 # Inst execution rate 567system.cpu.iew.wb_sent 650999754 # cumulative count of insts sent to commit 568system.cpu.iew.wb_count 646028902 # cumulative count of insts written-back 569system.cpu.iew.wb_producers 374692861 # num instructions producing a value 570system.cpu.iew.wb_consumers 646290036 # num instructions consuming a value |
| 441system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 571system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 442system.cpu.iew.wb_rate 1.615421 # insts written-back per cycle 443system.cpu.iew.wb_fanout 0.579735 # average fanout of values written-back | 572system.cpu.iew.wb_rate 1.596989 # insts written-back per cycle 573system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back |
| 444system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 574system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 445system.cpu.commit.commitSquashedInsts 189577075 # The number of squashed insts skipped by commit | 575system.cpu.commit.commitSquashedInsts 189414626 # The number of squashed insts skipped by commit |
| 446system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards | 576system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards |
| 447system.cpu.commit.branchMispredicts 7196029 # The number of times a branch was mispredicted 448system.cpu.commit.committed_per_cycle::samples 365056864 # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::mean 1.564053 # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::stdev 2.233130 # Number of insts commited each cycle | 577system.cpu.commit.branchMispredicts 7190929 # The number of times a branch was mispredicted 578system.cpu.commit.committed_per_cycle::samples 366730226 # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::mean 1.556916 # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::stdev 2.230567 # Number of insts commited each cycle |
| 451system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 581system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 452system.cpu.commit.committed_per_cycle::0 157408999 43.12% 43.12% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::1 98427012 26.96% 70.08% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::2 33819592 9.26% 79.35% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::3 18764553 5.14% 84.49% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::4 16211195 4.44% 88.93% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::5 7486266 2.05% 90.98% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::6 7003829 1.92% 92.90% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::7 3174116 0.87% 93.76% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::8 22761302 6.24% 100.00% # Number of insts commited each cycle | 582system.cpu.commit.committed_per_cycle::0 159030510 43.36% 43.36% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::1 98471088 26.85% 70.22% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::2 33850160 9.23% 79.45% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::3 18801710 5.13% 84.57% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::4 16194042 4.42% 88.99% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::5 7449344 2.03% 91.02% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::6 6951093 1.90% 92.92% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::7 3196049 0.87% 93.79% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::8 22786230 6.21% 100.00% # Number of insts commited each cycle |
| 461system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 591system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 464system.cpu.commit.committed_per_cycle::total 365056864 # Number of insts commited each cycle | 594system.cpu.commit.committed_per_cycle::total 366730226 # Number of insts commited each cycle |
| 465system.cpu.commit.committedInsts 506581607 # Number of instructions committed 466system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 467system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 468system.cpu.commit.refs 182890032 # Number of memory references committed 469system.cpu.commit.loads 126029555 # Number of loads committed 470system.cpu.commit.membars 1488542 # Number of memory barriers committed 471system.cpu.commit.branches 121548301 # Number of branches committed 472system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 473system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 474system.cpu.commit.function_calls 9757362 # Number of function calls committed. | 595system.cpu.commit.committedInsts 506581607 # Number of instructions committed 596system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 597system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 598system.cpu.commit.refs 182890032 # Number of memory references committed 599system.cpu.commit.loads 126029555 # Number of loads committed 600system.cpu.commit.membars 1488542 # Number of memory barriers committed 601system.cpu.commit.branches 121548301 # Number of branches committed 602system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 603system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 604system.cpu.commit.function_calls 9757362 # Number of function calls committed. |
| 475system.cpu.commit.bw_lim_events 22761302 # number cycles where commit BW limit reached | 605system.cpu.commit.bw_lim_events 22786230 # number cycles where commit BW limit reached |
| 476system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 606system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 477system.cpu.rob.rob_reads 1102833666 # The number of ROB reads 478system.cpu.rob.rob_writes 1548772691 # The number of ROB writes 479system.cpu.timesIdled 308172 # Number of times that the entire CPU went into an idle state and unscheduled itself 480system.cpu.idleCycles 7355257 # Total number of cycles that the CPU has spent unscheduled due to idling | 607system.cpu.rob.rob_reads 1104319651 # The number of ROB reads 608system.cpu.rob.rob_writes 1548423446 # The number of ROB writes 609system.cpu.timesIdled 327931 # Number of times that the entire CPU went into an idle state and unscheduled itself 610system.cpu.idleCycles 10262820 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 481system.cpu.committedInsts 505237723 # Number of Instructions Simulated 482system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 483system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated | 611system.cpu.committedInsts 505237723 # Number of Instructions Simulated 612system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 613system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated |
| 484system.cpu.cpi 0.791652 # CPI: Cycles Per Instruction 485system.cpu.cpi_total 0.791652 # CPI: Total CPI of All Threads 486system.cpu.ipc 1.263181 # IPC: Instructions Per Cycle 487system.cpu.ipc_total 1.263181 # IPC: Total IPC of All Threads 488system.cpu.int_regfile_reads 3059089015 # number of integer regfile reads 489system.cpu.int_regfile_writes 752056601 # number of integer regfile writes | 614system.cpu.cpi 0.800671 # CPI: Cycles Per Instruction 615system.cpu.cpi_total 0.800671 # CPI: Total CPI of All Threads 616system.cpu.ipc 1.248952 # IPC: Instructions Per Cycle 617system.cpu.ipc_total 1.248952 # IPC: Total IPC of All Threads 618system.cpu.int_regfile_reads 3058568749 # number of integer regfile reads 619system.cpu.int_regfile_writes 751946172 # number of integer regfile writes |
| 490system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 620system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 491system.cpu.misc_regfile_reads 210873671 # number of misc regfile reads | 621system.cpu.misc_regfile_reads 210826056 # number of misc regfile reads |
| 492system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes | 622system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes |
| 493system.cpu.icache.replacements 14975 # number of replacements 494system.cpu.icache.tagsinuse 1101.758220 # Cycle average of tags in use 495system.cpu.icache.total_refs 114524199 # Total number of references to valid blocks. 496system.cpu.icache.sampled_refs 16829 # Sample count of references to valid blocks. 497system.cpu.icache.avg_refs 6805.169588 # Average number of references to valid blocks. | 623system.cpu.toL2Bus.throughput 735267470 # Throughput (bytes/s) 624system.cpu.toL2Bus.trans_dist::ReadReq 864400 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::ReadResp 864399 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::Writeback 1110556 # Transaction distribution 627system.cpu.toL2Bus.trans_dist::UpgradeReq 92 # Transaction distribution 628system.cpu.toL2Bus.trans_dist::UpgradeResp 92 # Transaction distribution 629system.cpu.toL2Bus.trans_dist::ReadExReq 348774 # Transaction distribution 630system.cpu.toL2Bus.trans_dist::ReadExResp 348774 # Transaction distribution 631system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33891 # Packet count per connected master and slave (bytes) 632system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503090 # Packet count per connected master and slave (bytes) 633system.cpu.toL2Bus.pkt_count 3536981 # Packet count per connected master and slave (bytes) 634system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1081088 # Cumulative packet size per connected master and slave (bytes) 635system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147630784 # Cumulative packet size per connected master and slave (bytes) 636system.cpu.toL2Bus.tot_pkt_size 148711872 # Cumulative packet size per connected master and slave (bytes) 637system.cpu.toL2Bus.data_through_bus 148711872 # Total data (bytes) 638system.cpu.toL2Bus.snoop_data_through_bus 6784 # Total snoop data (bytes) 639system.cpu.toL2Bus.reqLayer0.occupancy 2272470744 # Layer occupancy (ticks) 640system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 641system.cpu.toL2Bus.respLayer0.occupancy 25507479 # Layer occupancy (ticks) 642system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 643system.cpu.toL2Bus.respLayer1.occupancy 1794320975 # Layer occupancy (ticks) 644system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 645system.cpu.icache.replacements 15058 # number of replacements 646system.cpu.icache.tagsinuse 1102.051233 # Cycle average of tags in use 647system.cpu.icache.total_refs 114501571 # Total number of references to valid blocks. 648system.cpu.icache.sampled_refs 16910 # Sample count of references to valid blocks. 649system.cpu.icache.avg_refs 6771.234240 # Average number of references to valid blocks. |
| 498system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 650system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 499system.cpu.icache.occ_blocks::cpu.inst 1101.758220 # Average occupied blocks per requestor 500system.cpu.icache.occ_percent::cpu.inst 0.537968 # Average percentage of cache occupancy 501system.cpu.icache.occ_percent::total 0.537968 # Average percentage of cache occupancy 502system.cpu.icache.ReadReq_hits::cpu.inst 114524201 # number of ReadReq hits 503system.cpu.icache.ReadReq_hits::total 114524201 # number of ReadReq hits 504system.cpu.icache.demand_hits::cpu.inst 114524201 # number of demand (read+write) hits 505system.cpu.icache.demand_hits::total 114524201 # number of demand (read+write) hits 506system.cpu.icache.overall_hits::cpu.inst 114524201 # number of overall hits 507system.cpu.icache.overall_hits::total 114524201 # number of overall hits 508system.cpu.icache.ReadReq_misses::cpu.inst 21083 # number of ReadReq misses 509system.cpu.icache.ReadReq_misses::total 21083 # number of ReadReq misses 510system.cpu.icache.demand_misses::cpu.inst 21083 # number of demand (read+write) misses 511system.cpu.icache.demand_misses::total 21083 # number of demand (read+write) misses 512system.cpu.icache.overall_misses::cpu.inst 21083 # number of overall misses 513system.cpu.icache.overall_misses::total 21083 # number of overall misses 514system.cpu.icache.ReadReq_miss_latency::cpu.inst 513115000 # number of ReadReq miss cycles 515system.cpu.icache.ReadReq_miss_latency::total 513115000 # number of ReadReq miss cycles 516system.cpu.icache.demand_miss_latency::cpu.inst 513115000 # number of demand (read+write) miss cycles 517system.cpu.icache.demand_miss_latency::total 513115000 # number of demand (read+write) miss cycles 518system.cpu.icache.overall_miss_latency::cpu.inst 513115000 # number of overall miss cycles 519system.cpu.icache.overall_miss_latency::total 513115000 # number of overall miss cycles 520system.cpu.icache.ReadReq_accesses::cpu.inst 114545284 # number of ReadReq accesses(hits+misses) 521system.cpu.icache.ReadReq_accesses::total 114545284 # number of ReadReq accesses(hits+misses) 522system.cpu.icache.demand_accesses::cpu.inst 114545284 # number of demand (read+write) accesses 523system.cpu.icache.demand_accesses::total 114545284 # number of demand (read+write) accesses 524system.cpu.icache.overall_accesses::cpu.inst 114545284 # number of overall (read+write) accesses 525system.cpu.icache.overall_accesses::total 114545284 # number of overall (read+write) accesses 526system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses 527system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses 528system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses 529system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses 530system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses 531system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses 532system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24337.855144 # average ReadReq miss latency 533system.cpu.icache.ReadReq_avg_miss_latency::total 24337.855144 # average ReadReq miss latency 534system.cpu.icache.demand_avg_miss_latency::cpu.inst 24337.855144 # average overall miss latency 535system.cpu.icache.demand_avg_miss_latency::total 24337.855144 # average overall miss latency 536system.cpu.icache.overall_avg_miss_latency::cpu.inst 24337.855144 # average overall miss latency 537system.cpu.icache.overall_avg_miss_latency::total 24337.855144 # average overall miss latency 538system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked | 651system.cpu.icache.occ_blocks::cpu.inst 1102.051233 # Average occupied blocks per requestor 652system.cpu.icache.occ_percent::cpu.inst 0.538111 # Average percentage of cache occupancy 653system.cpu.icache.occ_percent::total 0.538111 # Average percentage of cache occupancy 654system.cpu.icache.ReadReq_hits::cpu.inst 114501582 # number of ReadReq hits 655system.cpu.icache.ReadReq_hits::total 114501582 # number of ReadReq hits 656system.cpu.icache.demand_hits::cpu.inst 114501582 # number of demand (read+write) hits 657system.cpu.icache.demand_hits::total 114501582 # number of demand (read+write) hits 658system.cpu.icache.overall_hits::cpu.inst 114501582 # number of overall hits 659system.cpu.icache.overall_hits::total 114501582 # number of overall hits 660system.cpu.icache.ReadReq_misses::cpu.inst 21259 # number of ReadReq misses 661system.cpu.icache.ReadReq_misses::total 21259 # number of ReadReq misses 662system.cpu.icache.demand_misses::cpu.inst 21259 # number of demand (read+write) misses 663system.cpu.icache.demand_misses::total 21259 # number of demand (read+write) misses 664system.cpu.icache.overall_misses::cpu.inst 21259 # number of overall misses 665system.cpu.icache.overall_misses::total 21259 # number of overall misses 666system.cpu.icache.ReadReq_miss_latency::cpu.inst 595415500 # number of ReadReq miss cycles 667system.cpu.icache.ReadReq_miss_latency::total 595415500 # number of ReadReq miss cycles 668system.cpu.icache.demand_miss_latency::cpu.inst 595415500 # number of demand (read+write) miss cycles 669system.cpu.icache.demand_miss_latency::total 595415500 # number of demand (read+write) miss cycles 670system.cpu.icache.overall_miss_latency::cpu.inst 595415500 # number of overall miss cycles 671system.cpu.icache.overall_miss_latency::total 595415500 # number of overall miss cycles 672system.cpu.icache.ReadReq_accesses::cpu.inst 114522841 # number of ReadReq accesses(hits+misses) 673system.cpu.icache.ReadReq_accesses::total 114522841 # number of ReadReq accesses(hits+misses) 674system.cpu.icache.demand_accesses::cpu.inst 114522841 # number of demand (read+write) accesses 675system.cpu.icache.demand_accesses::total 114522841 # number of demand (read+write) accesses 676system.cpu.icache.overall_accesses::cpu.inst 114522841 # number of overall (read+write) accesses 677system.cpu.icache.overall_accesses::total 114522841 # number of overall (read+write) accesses 678system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses 680system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses 681system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses 682system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses 683system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28007.690860 # average ReadReq miss latency 685system.cpu.icache.ReadReq_avg_miss_latency::total 28007.690860 # average ReadReq miss latency 686system.cpu.icache.demand_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency 687system.cpu.icache.demand_avg_miss_latency::total 28007.690860 # average overall miss latency 688system.cpu.icache.overall_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency 689system.cpu.icache.overall_avg_miss_latency::total 28007.690860 # average overall miss latency 690system.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked |
| 539system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 691system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 540system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked | 692system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked |
| 541system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 693system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 542system.cpu.icache.avg_blocked_cycles::no_mshrs 46.090909 # average number of cycles each access was blocked | 694system.cpu.icache.avg_blocked_cycles::no_mshrs 181.923077 # average number of cycles each access was blocked |
| 543system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.icache.fast_writes 0 # number of fast writes performed 545system.cpu.icache.cache_copies 0 # number of cache copies performed | 695system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu.icache.fast_writes 0 # number of fast writes performed 697system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 546system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4176 # number of ReadReq MSHR hits 547system.cpu.icache.ReadReq_mshr_hits::total 4176 # number of ReadReq MSHR hits 548system.cpu.icache.demand_mshr_hits::cpu.inst 4176 # number of demand (read+write) MSHR hits 549system.cpu.icache.demand_mshr_hits::total 4176 # number of demand (read+write) MSHR hits 550system.cpu.icache.overall_mshr_hits::cpu.inst 4176 # number of overall MSHR hits 551system.cpu.icache.overall_mshr_hits::total 4176 # number of overall MSHR hits 552system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16907 # number of ReadReq MSHR misses 553system.cpu.icache.ReadReq_mshr_misses::total 16907 # number of ReadReq MSHR misses 554system.cpu.icache.demand_mshr_misses::cpu.inst 16907 # number of demand (read+write) MSHR misses 555system.cpu.icache.demand_mshr_misses::total 16907 # number of demand (read+write) MSHR misses 556system.cpu.icache.overall_mshr_misses::cpu.inst 16907 # number of overall MSHR misses 557system.cpu.icache.overall_mshr_misses::total 16907 # number of overall MSHR misses 558system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 373240000 # number of ReadReq MSHR miss cycles 559system.cpu.icache.ReadReq_mshr_miss_latency::total 373240000 # number of ReadReq MSHR miss cycles 560system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373240000 # number of demand (read+write) MSHR miss cycles 561system.cpu.icache.demand_mshr_miss_latency::total 373240000 # number of demand (read+write) MSHR miss cycles 562system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373240000 # number of overall MSHR miss cycles 563system.cpu.icache.overall_mshr_miss_latency::total 373240000 # number of overall MSHR miss cycles | 698system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4260 # number of ReadReq MSHR hits 699system.cpu.icache.ReadReq_mshr_hits::total 4260 # number of ReadReq MSHR hits 700system.cpu.icache.demand_mshr_hits::cpu.inst 4260 # number of demand (read+write) MSHR hits 701system.cpu.icache.demand_mshr_hits::total 4260 # number of demand (read+write) MSHR hits 702system.cpu.icache.overall_mshr_hits::cpu.inst 4260 # number of overall MSHR hits 703system.cpu.icache.overall_mshr_hits::total 4260 # number of overall MSHR hits 704system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16999 # number of ReadReq MSHR misses 705system.cpu.icache.ReadReq_mshr_misses::total 16999 # number of ReadReq MSHR misses 706system.cpu.icache.demand_mshr_misses::cpu.inst 16999 # number of demand (read+write) MSHR misses 707system.cpu.icache.demand_mshr_misses::total 16999 # number of demand (read+write) MSHR misses 708system.cpu.icache.overall_mshr_misses::cpu.inst 16999 # number of overall MSHR misses 709system.cpu.icache.overall_mshr_misses::total 16999 # number of overall MSHR misses 710system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426747521 # number of ReadReq MSHR miss cycles 711system.cpu.icache.ReadReq_mshr_miss_latency::total 426747521 # number of ReadReq MSHR miss cycles 712system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426747521 # number of demand (read+write) MSHR miss cycles 713system.cpu.icache.demand_mshr_miss_latency::total 426747521 # number of demand (read+write) MSHR miss cycles 714system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426747521 # number of overall MSHR miss cycles 715system.cpu.icache.overall_mshr_miss_latency::total 426747521 # number of overall MSHR miss cycles |
| 564system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses 565system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses 566system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses 567system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses 568system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses 569system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses | 716system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses 717system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses 718system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses 719system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses 720system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses 721system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses |
| 570system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22076.063169 # average ReadReq mshr miss latency 571system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22076.063169 # average ReadReq mshr miss latency 572system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22076.063169 # average overall mshr miss latency 573system.cpu.icache.demand_avg_mshr_miss_latency::total 22076.063169 # average overall mshr miss latency 574system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22076.063169 # average overall mshr miss latency 575system.cpu.icache.overall_avg_mshr_miss_latency::total 22076.063169 # average overall mshr miss latency | 722system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25104.272075 # average ReadReq mshr miss latency 723system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25104.272075 # average ReadReq mshr miss latency 724system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25104.272075 # average overall mshr miss latency 725system.cpu.icache.demand_avg_mshr_miss_latency::total 25104.272075 # average overall mshr miss latency 726system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25104.272075 # average overall mshr miss latency 727system.cpu.icache.overall_avg_mshr_miss_latency::total 25104.272075 # average overall mshr miss latency |
| 576system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 728system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 577system.cpu.l2cache.replacements 115457 # number of replacements 578system.cpu.l2cache.tagsinuse 27104.679408 # Cycle average of tags in use 579system.cpu.l2cache.total_refs 1780490 # Total number of references to valid blocks. 580system.cpu.l2cache.sampled_refs 146704 # Sample count of references to valid blocks. 581system.cpu.l2cache.avg_refs 12.136615 # Average number of references to valid blocks. 582system.cpu.l2cache.warmup_cycle 100708204000 # Cycle when the warmup percentage was hit. 583system.cpu.l2cache.occ_blocks::writebacks 23028.766881 # Average occupied blocks per requestor 584system.cpu.l2cache.occ_blocks::cpu.inst 362.570846 # Average occupied blocks per requestor 585system.cpu.l2cache.occ_blocks::cpu.data 3713.341681 # Average occupied blocks per requestor 586system.cpu.l2cache.occ_percent::writebacks 0.702782 # Average percentage of cache occupancy 587system.cpu.l2cache.occ_percent::cpu.inst 0.011065 # Average percentage of cache occupancy 588system.cpu.l2cache.occ_percent::cpu.data 0.113322 # Average percentage of cache occupancy 589system.cpu.l2cache.occ_percent::total 0.827169 # Average percentage of cache occupancy 590system.cpu.l2cache.ReadReq_hits::cpu.inst 13430 # number of ReadReq hits 591system.cpu.l2cache.ReadReq_hits::cpu.data 804137 # number of ReadReq hits 592system.cpu.l2cache.ReadReq_hits::total 817567 # number of ReadReq hits 593system.cpu.l2cache.Writeback_hits::writebacks 1110717 # number of Writeback hits 594system.cpu.l2cache.Writeback_hits::total 1110717 # number of Writeback hits 595system.cpu.l2cache.UpgradeReq_hits::cpu.data 70 # number of UpgradeReq hits 596system.cpu.l2cache.UpgradeReq_hits::total 70 # number of UpgradeReq hits 597system.cpu.l2cache.ReadExReq_hits::cpu.data 247495 # number of ReadExReq hits 598system.cpu.l2cache.ReadExReq_hits::total 247495 # number of ReadExReq hits 599system.cpu.l2cache.demand_hits::cpu.inst 13430 # number of demand (read+write) hits 600system.cpu.l2cache.demand_hits::cpu.data 1051632 # number of demand (read+write) hits 601system.cpu.l2cache.demand_hits::total 1065062 # number of demand (read+write) hits 602system.cpu.l2cache.overall_hits::cpu.inst 13430 # number of overall hits 603system.cpu.l2cache.overall_hits::cpu.data 1051632 # number of overall hits 604system.cpu.l2cache.overall_hits::total 1065062 # number of overall hits 605system.cpu.l2cache.ReadReq_misses::cpu.inst 3391 # number of ReadReq misses 606system.cpu.l2cache.ReadReq_misses::cpu.data 43534 # number of ReadReq misses 607system.cpu.l2cache.ReadReq_misses::total 46925 # number of ReadReq misses | 729system.cpu.l2cache.replacements 115327 # number of replacements 730system.cpu.l2cache.tagsinuse 27103.990610 # Cycle average of tags in use 731system.cpu.l2cache.total_refs 1780423 # Total number of references to valid blocks. 732system.cpu.l2cache.sampled_refs 146587 # Sample count of references to valid blocks. 733system.cpu.l2cache.avg_refs 12.145845 # Average number of references to valid blocks. 734system.cpu.l2cache.warmup_cycle 89762160000 # Cycle when the warmup percentage was hit. 735system.cpu.l2cache.occ_blocks::writebacks 23023.222015 # Average occupied blocks per requestor 736system.cpu.l2cache.occ_blocks::cpu.inst 362.369972 # Average occupied blocks per requestor 737system.cpu.l2cache.occ_blocks::cpu.data 3718.398623 # Average occupied blocks per requestor 738system.cpu.l2cache.occ_percent::writebacks 0.702613 # Average percentage of cache occupancy 739system.cpu.l2cache.occ_percent::cpu.inst 0.011059 # Average percentage of cache occupancy 740system.cpu.l2cache.occ_percent::cpu.data 0.113477 # Average percentage of cache occupancy 741system.cpu.l2cache.occ_percent::total 0.827148 # Average percentage of cache occupancy 742system.cpu.l2cache.ReadReq_hits::cpu.inst 13513 # number of ReadReq hits 743system.cpu.l2cache.ReadReq_hits::cpu.data 803960 # number of ReadReq hits 744system.cpu.l2cache.ReadReq_hits::total 817473 # number of ReadReq hits 745system.cpu.l2cache.Writeback_hits::writebacks 1110556 # number of Writeback hits 746system.cpu.l2cache.Writeback_hits::total 1110556 # number of Writeback hits 747system.cpu.l2cache.UpgradeReq_hits::cpu.data 83 # number of UpgradeReq hits 748system.cpu.l2cache.UpgradeReq_hits::total 83 # number of UpgradeReq hits 749system.cpu.l2cache.ReadExReq_hits::cpu.data 247491 # number of ReadExReq hits 750system.cpu.l2cache.ReadExReq_hits::total 247491 # number of ReadExReq hits 751system.cpu.l2cache.demand_hits::cpu.inst 13513 # number of demand (read+write) hits 752system.cpu.l2cache.demand_hits::cpu.data 1051451 # number of demand (read+write) hits 753system.cpu.l2cache.demand_hits::total 1064964 # number of demand (read+write) hits 754system.cpu.l2cache.overall_hits::cpu.inst 13513 # number of overall hits 755system.cpu.l2cache.overall_hits::cpu.data 1051451 # number of overall hits 756system.cpu.l2cache.overall_hits::total 1064964 # number of overall hits 757system.cpu.l2cache.ReadReq_misses::cpu.inst 3380 # number of ReadReq misses 758system.cpu.l2cache.ReadReq_misses::cpu.data 43441 # number of ReadReq misses 759system.cpu.l2cache.ReadReq_misses::total 46821 # number of ReadReq misses |
| 608system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 609system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses | 760system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 761system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses |
| 610system.cpu.l2cache.ReadExReq_misses::cpu.data 101303 # number of ReadExReq misses 611system.cpu.l2cache.ReadExReq_misses::total 101303 # number of ReadExReq misses 612system.cpu.l2cache.demand_misses::cpu.inst 3391 # number of demand (read+write) misses 613system.cpu.l2cache.demand_misses::cpu.data 144837 # number of demand (read+write) misses 614system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses 615system.cpu.l2cache.overall_misses::cpu.inst 3391 # number of overall misses 616system.cpu.l2cache.overall_misses::cpu.data 144837 # number of overall misses 617system.cpu.l2cache.overall_misses::total 148228 # number of overall misses 618system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 221462500 # number of ReadReq miss cycles 619system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2924340500 # number of ReadReq miss cycles 620system.cpu.l2cache.ReadReq_miss_latency::total 3145803000 # number of ReadReq miss cycles 621system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5221084500 # number of ReadExReq miss cycles 622system.cpu.l2cache.ReadExReq_miss_latency::total 5221084500 # number of ReadExReq miss cycles 623system.cpu.l2cache.demand_miss_latency::cpu.inst 221462500 # number of demand (read+write) miss cycles 624system.cpu.l2cache.demand_miss_latency::cpu.data 8145425000 # number of demand (read+write) miss cycles 625system.cpu.l2cache.demand_miss_latency::total 8366887500 # number of demand (read+write) miss cycles 626system.cpu.l2cache.overall_miss_latency::cpu.inst 221462500 # number of overall miss cycles 627system.cpu.l2cache.overall_miss_latency::cpu.data 8145425000 # number of overall miss cycles 628system.cpu.l2cache.overall_miss_latency::total 8366887500 # number of overall miss cycles 629system.cpu.l2cache.ReadReq_accesses::cpu.inst 16821 # number of ReadReq accesses(hits+misses) 630system.cpu.l2cache.ReadReq_accesses::cpu.data 847671 # number of ReadReq accesses(hits+misses) 631system.cpu.l2cache.ReadReq_accesses::total 864492 # number of ReadReq accesses(hits+misses) 632system.cpu.l2cache.Writeback_accesses::writebacks 1110717 # number of Writeback accesses(hits+misses) 633system.cpu.l2cache.Writeback_accesses::total 1110717 # number of Writeback accesses(hits+misses) 634system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) 635system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 636system.cpu.l2cache.ReadExReq_accesses::cpu.data 348798 # number of ReadExReq accesses(hits+misses) 637system.cpu.l2cache.ReadExReq_accesses::total 348798 # number of ReadExReq accesses(hits+misses) 638system.cpu.l2cache.demand_accesses::cpu.inst 16821 # number of demand (read+write) accesses 639system.cpu.l2cache.demand_accesses::cpu.data 1196469 # number of demand (read+write) accesses 640system.cpu.l2cache.demand_accesses::total 1213290 # number of demand (read+write) accesses 641system.cpu.l2cache.overall_accesses::cpu.inst 16821 # number of overall (read+write) accesses 642system.cpu.l2cache.overall_accesses::cpu.data 1196469 # number of overall (read+write) accesses 643system.cpu.l2cache.overall_accesses::total 1213290 # number of overall (read+write) accesses 644system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201593 # miss rate for ReadReq accesses 645system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051357 # miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_miss_rate::total 0.054280 # miss rate for ReadReq accesses 647system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.113924 # miss rate for UpgradeReq accesses 648system.cpu.l2cache.UpgradeReq_miss_rate::total 0.113924 # miss rate for UpgradeReq accesses 649system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290435 # miss rate for ReadExReq accesses 650system.cpu.l2cache.ReadExReq_miss_rate::total 0.290435 # miss rate for ReadExReq accesses 651system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201593 # miss rate for demand accesses 652system.cpu.l2cache.demand_miss_rate::cpu.data 0.121054 # miss rate for demand accesses 653system.cpu.l2cache.demand_miss_rate::total 0.122170 # miss rate for demand accesses 654system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201593 # miss rate for overall accesses 655system.cpu.l2cache.overall_miss_rate::cpu.data 0.121054 # miss rate for overall accesses 656system.cpu.l2cache.overall_miss_rate::total 0.122170 # miss rate for overall accesses 657system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65308.905927 # average ReadReq miss latency 658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67173.714798 # average ReadReq miss latency 659system.cpu.l2cache.ReadReq_avg_miss_latency::total 67038.955781 # average ReadReq miss latency 660system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51539.288076 # average ReadExReq miss latency 661system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51539.288076 # average ReadExReq miss latency 662system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65308.905927 # average overall miss latency 663system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56238.564731 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::total 56446.066195 # average overall miss latency 665system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65308.905927 # average overall miss latency 666system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56238.564731 # average overall miss latency 667system.cpu.l2cache.overall_avg_miss_latency::total 56446.066195 # average overall miss latency | 762system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses 763system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses 764system.cpu.l2cache.demand_misses::cpu.inst 3380 # number of demand (read+write) misses 765system.cpu.l2cache.demand_misses::cpu.data 144724 # number of demand (read+write) misses 766system.cpu.l2cache.demand_misses::total 148104 # number of demand (read+write) misses 767system.cpu.l2cache.overall_misses::cpu.inst 3380 # number of overall misses 768system.cpu.l2cache.overall_misses::cpu.data 144724 # number of overall misses 769system.cpu.l2cache.overall_misses::total 148104 # number of overall misses 770system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 274234000 # number of ReadReq miss cycles 771system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3645115500 # number of ReadReq miss cycles 772system.cpu.l2cache.ReadReq_miss_latency::total 3919349500 # number of ReadReq miss cycles 773system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles 774system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles 775system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7042551500 # number of ReadExReq miss cycles 776system.cpu.l2cache.ReadExReq_miss_latency::total 7042551500 # number of ReadExReq miss cycles 777system.cpu.l2cache.demand_miss_latency::cpu.inst 274234000 # number of demand (read+write) miss cycles 778system.cpu.l2cache.demand_miss_latency::cpu.data 10687667000 # number of demand (read+write) miss cycles 779system.cpu.l2cache.demand_miss_latency::total 10961901000 # number of demand (read+write) miss cycles 780system.cpu.l2cache.overall_miss_latency::cpu.inst 274234000 # number of overall miss cycles 781system.cpu.l2cache.overall_miss_latency::cpu.data 10687667000 # number of overall miss cycles 782system.cpu.l2cache.overall_miss_latency::total 10961901000 # number of overall miss cycles 783system.cpu.l2cache.ReadReq_accesses::cpu.inst 16893 # number of ReadReq accesses(hits+misses) 784system.cpu.l2cache.ReadReq_accesses::cpu.data 847401 # number of ReadReq accesses(hits+misses) 785system.cpu.l2cache.ReadReq_accesses::total 864294 # number of ReadReq accesses(hits+misses) 786system.cpu.l2cache.Writeback_accesses::writebacks 1110556 # number of Writeback accesses(hits+misses) 787system.cpu.l2cache.Writeback_accesses::total 1110556 # number of Writeback accesses(hits+misses) 788system.cpu.l2cache.UpgradeReq_accesses::cpu.data 92 # number of UpgradeReq accesses(hits+misses) 789system.cpu.l2cache.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) 790system.cpu.l2cache.ReadExReq_accesses::cpu.data 348774 # number of ReadExReq accesses(hits+misses) 791system.cpu.l2cache.ReadExReq_accesses::total 348774 # number of ReadExReq accesses(hits+misses) 792system.cpu.l2cache.demand_accesses::cpu.inst 16893 # number of demand (read+write) accesses 793system.cpu.l2cache.demand_accesses::cpu.data 1196175 # number of demand (read+write) accesses 794system.cpu.l2cache.demand_accesses::total 1213068 # number of demand (read+write) accesses 795system.cpu.l2cache.overall_accesses::cpu.inst 16893 # number of overall (read+write) accesses 796system.cpu.l2cache.overall_accesses::cpu.data 1196175 # number of overall (read+write) accesses 797system.cpu.l2cache.overall_accesses::total 1213068 # number of overall (read+write) accesses 798system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200083 # miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051264 # miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_miss_rate::total 0.054173 # miss rate for ReadReq accesses 801system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.097826 # miss rate for UpgradeReq accesses 802system.cpu.l2cache.UpgradeReq_miss_rate::total 0.097826 # miss rate for UpgradeReq accesses 803system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290397 # miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadExReq_miss_rate::total 0.290397 # miss rate for ReadExReq accesses 805system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200083 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::cpu.data 0.120989 # miss rate for demand accesses 807system.cpu.l2cache.demand_miss_rate::total 0.122090 # miss rate for demand accesses 808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200083 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.data 0.120989 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::total 0.122090 # miss rate for overall accesses 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81134.319527 # average ReadReq miss latency 812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83909.566999 # average ReadReq miss latency 813system.cpu.l2cache.ReadReq_avg_miss_latency::total 83709.222357 # average ReadReq miss latency 814system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2500 # average UpgradeReq miss latency 815system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2500 # average UpgradeReq miss latency 816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69533.401459 # average ReadExReq miss latency 817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69533.401459 # average ReadExReq miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81134.319527 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73848.615295 # average overall miss latency 820system.cpu.l2cache.demand_avg_miss_latency::total 74014.888187 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81134.319527 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73848.615295 # average overall miss latency 823system.cpu.l2cache.overall_avg_miss_latency::total 74014.888187 # average overall miss latency |
| 668system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu.l2cache.fast_writes 0 # number of fast writes performed 675system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 830system.cpu.l2cache.fast_writes 0 # number of fast writes performed 831system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 676system.cpu.l2cache.writebacks::writebacks 97647 # number of writebacks 677system.cpu.l2cache.writebacks::total 97647 # number of writebacks 678system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 679system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits 680system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits 681system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 682system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits 683system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits 684system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 685system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits 686system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits 687system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3386 # number of ReadReq MSHR misses 688system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43511 # number of ReadReq MSHR misses 689system.cpu.l2cache.ReadReq_mshr_misses::total 46897 # number of ReadReq MSHR misses | 832system.cpu.l2cache.writebacks::writebacks 97594 # number of writebacks 833system.cpu.l2cache.writebacks::total 97594 # number of writebacks 834system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 835system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits 836system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits 837system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 838system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits 839system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits 840system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 841system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 842system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits 843system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3376 # number of ReadReq MSHR misses 844system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43419 # number of ReadReq MSHR misses 845system.cpu.l2cache.ReadReq_mshr_misses::total 46795 # number of ReadReq MSHR misses |
| 690system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses 691system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses | 846system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses 847system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses |
| 692system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101303 # number of ReadExReq MSHR misses 693system.cpu.l2cache.ReadExReq_mshr_misses::total 101303 # number of ReadExReq MSHR misses 694system.cpu.l2cache.demand_mshr_misses::cpu.inst 3386 # number of demand (read+write) MSHR misses 695system.cpu.l2cache.demand_mshr_misses::cpu.data 144814 # number of demand (read+write) MSHR misses 696system.cpu.l2cache.demand_mshr_misses::total 148200 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.overall_mshr_misses::cpu.inst 3386 # number of overall MSHR misses 698system.cpu.l2cache.overall_mshr_misses::cpu.data 144814 # number of overall MSHR misses 699system.cpu.l2cache.overall_mshr_misses::total 148200 # number of overall MSHR misses 700system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 179125175 # number of ReadReq MSHR miss cycles 701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2382731950 # number of ReadReq MSHR miss cycles 702system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2561857125 # number of ReadReq MSHR miss cycles 703system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles 704system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles 705system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3956091381 # number of ReadExReq MSHR miss cycles 706system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3956091381 # number of ReadExReq MSHR miss cycles 707system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179125175 # number of demand (read+write) MSHR miss cycles 708system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6338823331 # number of demand (read+write) MSHR miss cycles 709system.cpu.l2cache.demand_mshr_miss_latency::total 6517948506 # number of demand (read+write) MSHR miss cycles 710system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179125175 # number of overall MSHR miss cycles 711system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6338823331 # number of overall MSHR miss cycles 712system.cpu.l2cache.overall_mshr_miss_latency::total 6517948506 # number of overall MSHR miss cycles 713system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051330 # mshr miss rate for ReadReq accesses 715system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054248 # mshr miss rate for ReadReq accesses 716system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.113924 # mshr miss rate for UpgradeReq accesses 717system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.113924 # mshr miss rate for UpgradeReq accesses 718system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290435 # mshr miss rate for ReadExReq accesses 719system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290435 # mshr miss rate for ReadExReq accesses 720system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for demand accesses 721system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121034 # mshr miss rate for demand accesses 722system.cpu.l2cache.demand_mshr_miss_rate::total 0.122147 # mshr miss rate for demand accesses 723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for overall accesses 724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121034 # mshr miss rate for overall accesses 725system.cpu.l2cache.overall_mshr_miss_rate::total 0.122147 # mshr miss rate for overall accesses 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52901.705552 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54761.599366 # average ReadReq mshr miss latency 728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54627.313581 # average ReadReq mshr miss latency 729system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 730system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 731system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39052.065398 # average ReadExReq mshr miss latency 732system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39052.065398 # average ReadExReq mshr miss latency 733system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52901.705552 # average overall mshr miss latency 734system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43772.172104 # average overall mshr miss latency 735system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43980.759150 # average overall mshr miss latency 736system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52901.705552 # average overall mshr miss latency 737system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43772.172104 # average overall mshr miss latency 738system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43980.759150 # average overall mshr miss latency | 848system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses 849system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses 850system.cpu.l2cache.demand_mshr_misses::cpu.inst 3376 # number of demand (read+write) MSHR misses 851system.cpu.l2cache.demand_mshr_misses::cpu.data 144702 # number of demand (read+write) MSHR misses 852system.cpu.l2cache.demand_mshr_misses::total 148078 # number of demand (read+write) MSHR misses 853system.cpu.l2cache.overall_mshr_misses::cpu.inst 3376 # number of overall MSHR misses 854system.cpu.l2cache.overall_mshr_misses::cpu.data 144702 # number of overall MSHR misses 855system.cpu.l2cache.overall_mshr_misses::total 148078 # number of overall MSHR misses 856system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231774000 # number of ReadReq MSHR miss cycles 857system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3104828000 # number of ReadReq MSHR miss cycles 858system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3336602000 # number of ReadReq MSHR miss cycles 859system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 94508 # number of UpgradeReq MSHR miss cycles 860system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 94508 # number of UpgradeReq MSHR miss cycles 861system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5779215000 # number of ReadExReq MSHR miss cycles 862system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5779215000 # number of ReadExReq MSHR miss cycles 863system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231774000 # number of demand (read+write) MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8884043000 # number of demand (read+write) MSHR miss cycles 865system.cpu.l2cache.demand_mshr_miss_latency::total 9115817000 # number of demand (read+write) MSHR miss cycles 866system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231774000 # number of overall MSHR miss cycles 867system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8884043000 # number of overall MSHR miss cycles 868system.cpu.l2cache.overall_mshr_miss_latency::total 9115817000 # number of overall MSHR miss cycles 869system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051238 # mshr miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054142 # mshr miss rate for ReadReq accesses 872system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097826 # mshr miss rate for UpgradeReq accesses 873system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097826 # mshr miss rate for UpgradeReq accesses 874system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290397 # mshr miss rate for ReadExReq accesses 875system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290397 # mshr miss rate for ReadExReq accesses 876system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for demand accesses 877system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses 878system.cpu.l2cache.demand_mshr_miss_rate::total 0.122069 # mshr miss rate for demand accesses 879system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for overall accesses 880system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses 881system.cpu.l2cache.overall_mshr_miss_rate::total 0.122069 # mshr miss rate for overall accesses 882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68653.436019 # average ReadReq mshr miss latency 883system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71508.510099 # average ReadReq mshr miss latency 884system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71302.532322 # average ReadReq mshr miss latency 885system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.888889 # average UpgradeReq mshr miss latency 886system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.888889 # average UpgradeReq mshr miss latency 887system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57060.069311 # average ReadExReq mshr miss latency 888system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57060.069311 # average ReadExReq mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency |
| 739system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 895system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 740system.cpu.dcache.replacements 1192373 # number of replacements 741system.cpu.dcache.tagsinuse 4058.219651 # Cycle average of tags in use 742system.cpu.dcache.total_refs 190179591 # Total number of references to valid blocks. 743system.cpu.dcache.sampled_refs 1196469 # Sample count of references to valid blocks. 744system.cpu.dcache.avg_refs 158.950705 # Average number of references to valid blocks. 745system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. 746system.cpu.dcache.occ_blocks::cpu.data 4058.219651 # Average occupied blocks per requestor 747system.cpu.dcache.occ_percent::cpu.data 0.990776 # Average percentage of cache occupancy 748system.cpu.dcache.occ_percent::total 0.990776 # Average percentage of cache occupancy 749system.cpu.dcache.ReadReq_hits::cpu.data 136210299 # number of ReadReq hits 750system.cpu.dcache.ReadReq_hits::total 136210299 # number of ReadReq hits 751system.cpu.dcache.WriteReq_hits::cpu.data 50991632 # number of WriteReq hits 752system.cpu.dcache.WriteReq_hits::total 50991632 # number of WriteReq hits 753system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits 754system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits | 896system.cpu.dcache.replacements 1192079 # number of replacements 897system.cpu.dcache.tagsinuse 4057.787384 # Cycle average of tags in use 898system.cpu.dcache.total_refs 190170418 # Total number of references to valid blocks. 899system.cpu.dcache.sampled_refs 1196175 # Sample count of references to valid blocks. 900system.cpu.dcache.avg_refs 158.982104 # Average number of references to valid blocks. 901system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit. 902system.cpu.dcache.occ_blocks::cpu.data 4057.787384 # Average occupied blocks per requestor 903system.cpu.dcache.occ_percent::cpu.data 0.990671 # Average percentage of cache occupancy 904system.cpu.dcache.occ_percent::total 0.990671 # Average percentage of cache occupancy 905system.cpu.dcache.ReadReq_hits::cpu.data 136204469 # number of ReadReq hits 906system.cpu.dcache.ReadReq_hits::total 136204469 # number of ReadReq hits 907system.cpu.dcache.WriteReq_hits::cpu.data 50988281 # number of WriteReq hits 908system.cpu.dcache.WriteReq_hits::total 50988281 # number of WriteReq hits 909system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488831 # number of LoadLockedReq hits 910system.cpu.dcache.LoadLockedReq_hits::total 1488831 # number of LoadLockedReq hits |
| 755system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 756system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits | 911system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 912system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits |
| 757system.cpu.dcache.demand_hits::cpu.data 187201931 # number of demand (read+write) hits 758system.cpu.dcache.demand_hits::total 187201931 # number of demand (read+write) hits 759system.cpu.dcache.overall_hits::cpu.data 187201931 # number of overall hits 760system.cpu.dcache.overall_hits::total 187201931 # number of overall hits 761system.cpu.dcache.ReadReq_misses::cpu.data 1698949 # number of ReadReq misses 762system.cpu.dcache.ReadReq_misses::total 1698949 # number of ReadReq misses 763system.cpu.dcache.WriteReq_misses::cpu.data 3247674 # number of WriteReq misses 764system.cpu.dcache.WriteReq_misses::total 3247674 # number of WriteReq misses 765system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 766system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses 767system.cpu.dcache.demand_misses::cpu.data 4946623 # number of demand (read+write) misses 768system.cpu.dcache.demand_misses::total 4946623 # number of demand (read+write) misses 769system.cpu.dcache.overall_misses::cpu.data 4946623 # number of overall misses 770system.cpu.dcache.overall_misses::total 4946623 # number of overall misses 771system.cpu.dcache.ReadReq_miss_latency::cpu.data 26713032500 # number of ReadReq miss cycles 772system.cpu.dcache.ReadReq_miss_latency::total 26713032500 # number of ReadReq miss cycles 773system.cpu.dcache.WriteReq_miss_latency::cpu.data 57280936446 # number of WriteReq miss cycles 774system.cpu.dcache.WriteReq_miss_latency::total 57280936446 # number of WriteReq miss cycles 775system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 664500 # number of LoadLockedReq miss cycles 776system.cpu.dcache.LoadLockedReq_miss_latency::total 664500 # number of LoadLockedReq miss cycles 777system.cpu.dcache.demand_miss_latency::cpu.data 83993968946 # number of demand (read+write) miss cycles 778system.cpu.dcache.demand_miss_latency::total 83993968946 # number of demand (read+write) miss cycles 779system.cpu.dcache.overall_miss_latency::cpu.data 83993968946 # number of overall miss cycles 780system.cpu.dcache.overall_miss_latency::total 83993968946 # number of overall miss cycles 781system.cpu.dcache.ReadReq_accesses::cpu.data 137909248 # number of ReadReq accesses(hits+misses) 782system.cpu.dcache.ReadReq_accesses::total 137909248 # number of ReadReq accesses(hits+misses) | 913system.cpu.dcache.demand_hits::cpu.data 187192750 # number of demand (read+write) hits 914system.cpu.dcache.demand_hits::total 187192750 # number of demand (read+write) hits 915system.cpu.dcache.overall_hits::cpu.data 187192750 # number of overall hits 916system.cpu.dcache.overall_hits::total 187192750 # number of overall hits 917system.cpu.dcache.ReadReq_misses::cpu.data 1701442 # number of ReadReq misses 918system.cpu.dcache.ReadReq_misses::total 1701442 # number of ReadReq misses 919system.cpu.dcache.WriteReq_misses::cpu.data 3251025 # number of WriteReq misses 920system.cpu.dcache.WriteReq_misses::total 3251025 # number of WriteReq misses 921system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses 922system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses 923system.cpu.dcache.demand_misses::cpu.data 4952467 # number of demand (read+write) misses 924system.cpu.dcache.demand_misses::total 4952467 # number of demand (read+write) misses 925system.cpu.dcache.overall_misses::cpu.data 4952467 # number of overall misses 926system.cpu.dcache.overall_misses::total 4952467 # number of overall misses 927system.cpu.dcache.ReadReq_miss_latency::cpu.data 29643398500 # number of ReadReq miss cycles 928system.cpu.dcache.ReadReq_miss_latency::total 29643398500 # number of ReadReq miss cycles 929system.cpu.dcache.WriteReq_miss_latency::cpu.data 68982804444 # number of WriteReq miss cycles 930system.cpu.dcache.WriteReq_miss_latency::total 68982804444 # number of WriteReq miss cycles 931system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 639500 # number of LoadLockedReq miss cycles 932system.cpu.dcache.LoadLockedReq_miss_latency::total 639500 # number of LoadLockedReq miss cycles 933system.cpu.dcache.demand_miss_latency::cpu.data 98626202944 # number of demand (read+write) miss cycles 934system.cpu.dcache.demand_miss_latency::total 98626202944 # number of demand (read+write) miss cycles 935system.cpu.dcache.overall_miss_latency::cpu.data 98626202944 # number of overall miss cycles 936system.cpu.dcache.overall_miss_latency::total 98626202944 # number of overall miss cycles 937system.cpu.dcache.ReadReq_accesses::cpu.data 137905911 # number of ReadReq accesses(hits+misses) 938system.cpu.dcache.ReadReq_accesses::total 137905911 # number of ReadReq accesses(hits+misses) |
| 783system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 784system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) | 939system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 940system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) |
| 785system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488864 # number of LoadLockedReq accesses(hits+misses) 786system.cpu.dcache.LoadLockedReq_accesses::total 1488864 # number of LoadLockedReq accesses(hits+misses) | 941system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488869 # number of LoadLockedReq accesses(hits+misses) 942system.cpu.dcache.LoadLockedReq_accesses::total 1488869 # number of LoadLockedReq accesses(hits+misses) |
| 787system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 788system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) | 943system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 944system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) |
| 789system.cpu.dcache.demand_accesses::cpu.data 192148554 # number of demand (read+write) accesses 790system.cpu.dcache.demand_accesses::total 192148554 # number of demand (read+write) accesses 791system.cpu.dcache.overall_accesses::cpu.data 192148554 # number of overall (read+write) accesses 792system.cpu.dcache.overall_accesses::total 192148554 # number of overall (read+write) accesses 793system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012319 # miss rate for ReadReq accesses 794system.cpu.dcache.ReadReq_miss_rate::total 0.012319 # miss rate for ReadReq accesses 795system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses 796system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses 797system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses 798system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses 799system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses 800system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses 801system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses 802system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses 803system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15723.269209 # average ReadReq miss latency 804system.cpu.dcache.ReadReq_avg_miss_latency::total 15723.269209 # average ReadReq miss latency 805system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17637.526564 # average WriteReq miss latency 806system.cpu.dcache.WriteReq_avg_miss_latency::total 17637.526564 # average WriteReq miss latency 807system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16207.317073 # average LoadLockedReq miss latency 808system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16207.317073 # average LoadLockedReq miss latency 809system.cpu.dcache.demand_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency 810system.cpu.dcache.demand_avg_miss_latency::total 16980.062751 # average overall miss latency 811system.cpu.dcache.overall_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency 812system.cpu.dcache.overall_avg_miss_latency::total 16980.062751 # average overall miss latency 813system.cpu.dcache.blocked_cycles::no_mshrs 15427 # number of cycles access was blocked 814system.cpu.dcache.blocked_cycles::no_targets 16116 # number of cycles access was blocked 815system.cpu.dcache.blocked::no_mshrs 1677 # number of cycles access was blocked 816system.cpu.dcache.blocked::no_targets 607 # number of cycles access was blocked 817system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.199165 # average number of cycles each access was blocked 818system.cpu.dcache.avg_blocked_cycles::no_targets 26.550247 # average number of cycles each access was blocked | 945system.cpu.dcache.demand_accesses::cpu.data 192145217 # number of demand (read+write) accesses 946system.cpu.dcache.demand_accesses::total 192145217 # number of demand (read+write) accesses 947system.cpu.dcache.overall_accesses::cpu.data 192145217 # number of overall (read+write) accesses 948system.cpu.dcache.overall_accesses::total 192145217 # number of overall (read+write) accesses 949system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012338 # miss rate for ReadReq accesses 950system.cpu.dcache.ReadReq_miss_rate::total 0.012338 # miss rate for ReadReq accesses 951system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses 952system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses 953system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000026 # miss rate for LoadLockedReq accesses 954system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000026 # miss rate for LoadLockedReq accesses 955system.cpu.dcache.demand_miss_rate::cpu.data 0.025775 # miss rate for demand accesses 956system.cpu.dcache.demand_miss_rate::total 0.025775 # miss rate for demand accesses 957system.cpu.dcache.overall_miss_rate::cpu.data 0.025775 # miss rate for overall accesses 958system.cpu.dcache.overall_miss_rate::total 0.025775 # miss rate for overall accesses 959system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17422.514843 # average ReadReq miss latency 960system.cpu.dcache.ReadReq_avg_miss_latency::total 17422.514843 # average ReadReq miss latency 961system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21218.786212 # average WriteReq miss latency 962system.cpu.dcache.WriteReq_avg_miss_latency::total 21218.786212 # average WriteReq miss latency 963system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16828.947368 # average LoadLockedReq miss latency 964system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16828.947368 # average LoadLockedReq miss latency 965system.cpu.dcache.demand_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency 966system.cpu.dcache.demand_avg_miss_latency::total 19914.560348 # average overall miss latency 967system.cpu.dcache.overall_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::total 19914.560348 # average overall miss latency 969system.cpu.dcache.blocked_cycles::no_mshrs 17857 # number of cycles access was blocked 970system.cpu.dcache.blocked_cycles::no_targets 40598 # number of cycles access was blocked 971system.cpu.dcache.blocked::no_mshrs 1694 # number of cycles access was blocked 972system.cpu.dcache.blocked::no_targets 662 # number of cycles access was blocked 973system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.541322 # average number of cycles each access was blocked 974system.cpu.dcache.avg_blocked_cycles::no_targets 61.326284 # average number of cycles each access was blocked |
| 819system.cpu.dcache.fast_writes 0 # number of fast writes performed 820system.cpu.dcache.cache_copies 0 # number of cache copies performed | 975system.cpu.dcache.fast_writes 0 # number of fast writes performed 976system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 821system.cpu.dcache.writebacks::writebacks 1110717 # number of writebacks 822system.cpu.dcache.writebacks::total 1110717 # number of writebacks 823system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850753 # number of ReadReq MSHR hits 824system.cpu.dcache.ReadReq_mshr_hits::total 850753 # number of ReadReq MSHR hits 825system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899322 # number of WriteReq MSHR hits 826system.cpu.dcache.WriteReq_mshr_hits::total 2899322 # number of WriteReq MSHR hits 827system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits 828system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits 829system.cpu.dcache.demand_mshr_hits::cpu.data 3750075 # number of demand (read+write) MSHR hits 830system.cpu.dcache.demand_mshr_hits::total 3750075 # number of demand (read+write) MSHR hits 831system.cpu.dcache.overall_mshr_hits::cpu.data 3750075 # number of overall MSHR hits 832system.cpu.dcache.overall_mshr_hits::total 3750075 # number of overall MSHR hits 833system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848196 # number of ReadReq MSHR misses 834system.cpu.dcache.ReadReq_mshr_misses::total 848196 # number of ReadReq MSHR misses 835system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348352 # number of WriteReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::total 348352 # number of WriteReq MSHR misses 837system.cpu.dcache.demand_mshr_misses::cpu.data 1196548 # number of demand (read+write) MSHR misses 838system.cpu.dcache.demand_mshr_misses::total 1196548 # number of demand (read+write) MSHR misses 839system.cpu.dcache.overall_mshr_misses::cpu.data 1196548 # number of overall MSHR misses 840system.cpu.dcache.overall_mshr_misses::total 1196548 # number of overall MSHR misses 841system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11853689000 # number of ReadReq MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_latency::total 11853689000 # number of ReadReq MSHR miss cycles 843system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8094107996 # number of WriteReq MSHR miss cycles 844system.cpu.dcache.WriteReq_mshr_miss_latency::total 8094107996 # number of WriteReq MSHR miss cycles 845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19947796996 # number of demand (read+write) MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::total 19947796996 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19947796996 # number of overall MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::total 19947796996 # number of overall MSHR miss cycles 849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses 850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses 854system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses 855system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses 856system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses 857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13975.176728 # average ReadReq mshr miss latency 858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13975.176728 # average ReadReq mshr miss latency 859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23235.428521 # average WriteReq mshr miss latency 860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23235.428521 # average WriteReq mshr miss latency 861system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency 863system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency | 977system.cpu.dcache.writebacks::writebacks 1110556 # number of writebacks 978system.cpu.dcache.writebacks::total 1110556 # number of writebacks 979system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853509 # number of ReadReq MSHR hits 980system.cpu.dcache.ReadReq_mshr_hits::total 853509 # number of ReadReq MSHR hits 981system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902691 # number of WriteReq MSHR hits 982system.cpu.dcache.WriteReq_mshr_hits::total 2902691 # number of WriteReq MSHR hits 983system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits 984system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits 985system.cpu.dcache.demand_mshr_hits::cpu.data 3756200 # number of demand (read+write) MSHR hits 986system.cpu.dcache.demand_mshr_hits::total 3756200 # number of demand (read+write) MSHR hits 987system.cpu.dcache.overall_mshr_hits::cpu.data 3756200 # number of overall MSHR hits 988system.cpu.dcache.overall_mshr_hits::total 3756200 # number of overall MSHR hits 989system.cpu.dcache.ReadReq_mshr_misses::cpu.data 847933 # number of ReadReq MSHR misses 990system.cpu.dcache.ReadReq_mshr_misses::total 847933 # number of ReadReq MSHR misses 991system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348334 # number of WriteReq MSHR misses 992system.cpu.dcache.WriteReq_mshr_misses::total 348334 # number of WriteReq MSHR misses 993system.cpu.dcache.demand_mshr_misses::cpu.data 1196267 # number of demand (read+write) MSHR misses 994system.cpu.dcache.demand_mshr_misses::total 1196267 # number of demand (read+write) MSHR misses 995system.cpu.dcache.overall_mshr_misses::cpu.data 1196267 # number of overall MSHR misses 996system.cpu.dcache.overall_mshr_misses::total 1196267 # number of overall MSHR misses 997system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12570935024 # number of ReadReq MSHR miss cycles 998system.cpu.dcache.ReadReq_mshr_miss_latency::total 12570935024 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9915738995 # number of WriteReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::total 9915738995 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22486674019 # number of demand (read+write) MSHR miss cycles 1002system.cpu.dcache.demand_mshr_miss_latency::total 22486674019 # number of demand (read+write) MSHR miss cycles 1003system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22486674019 # number of overall MSHR miss cycles 1004system.cpu.dcache.overall_mshr_miss_latency::total 22486674019 # number of overall MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006149 # mshr miss rate for ReadReq accesses 1006system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006149 # mshr miss rate for ReadReq accesses 1007system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses 1008system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses 1009system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses 1010system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses 1011system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses 1012system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses 1013system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14825.387176 # average ReadReq mshr miss latency 1014system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14825.387176 # average ReadReq mshr miss latency 1015system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28466.181869 # average WriteReq mshr miss latency 1016system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28466.181869 # average WriteReq mshr miss latency 1017system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency 1018system.cpu.dcache.demand_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency 1019system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency 1020system.cpu.dcache.overall_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency |
| 865system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 866 867---------- End Simulation Statistics ---------- | 1021system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1022 1023---------- End Simulation Statistics ---------- |