| stats.txt (9285:9901180cd573) | stats.txt (9289:a31a1243a3ed) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.201852 # Number of seconds simulated 4sim_ticks 201852280500 # Number of ticks simulated 5final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.201852 # Number of seconds simulated 4sim_ticks 201852280500 # Number of ticks simulated 5final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 114620 # Simulator instruction rate (inst/s) 8host_op_rate 129121 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45458575 # Simulator tick rate (ticks/s) 10host_mem_usage 239092 # Number of bytes of host memory used 11host_seconds 4440.36 # Real time elapsed on the host | 7host_inst_rate 135871 # Simulator instruction rate (inst/s) 8host_op_rate 153059 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53886430 # Simulator tick rate (ticks/s) 10host_mem_usage 232836 # Number of bytes of host memory used 11host_seconds 3745.88 # Real time elapsed on the host |
| 12sim_insts 508955133 # Number of instructions simulated 13sim_ops 573341693 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10015872 # Number of bytes read from this memory 16system.physmem.bytes_read::total 10234688 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 218816 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 218816 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6679360 # Number of bytes written to this memory --- 137 unchanged lines hidden (view full) --- 157system.cpu.iq.iqSquashedInstsIssued 1597303 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 191893802 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 493277148 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 746286 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 402291353 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 12sim_insts 508955133 # Number of instructions simulated 13sim_ops 573341693 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10015872 # Number of bytes read from this memory 16system.physmem.bytes_read::total 10234688 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 218816 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 218816 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6679360 # Number of bytes written to this memory --- 137 unchanged lines hidden (view full) --- 157system.cpu.iq.iqSquashedInstsIssued 1597303 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 191893802 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 493277148 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 746286 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 402291353 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 165system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle | 165system.cpu.iq.issued_per_cycle::0 143645798 35.71% 35.71% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 74204622 18.45% 54.15% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 68520864 17.03% 71.19% # Number of insts issued each cycle |
| 168system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 9421817 2.34% 98.82% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 3434032 0.85% 99.68% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 1296489 0.32% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle --- 322 unchanged lines hidden (view full) --- 498system.cpu.dcache.WriteReq_avg_miss_latency::total 17162.181168 # average WriteReq miss latency 499system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8776.595745 # average LoadLockedReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8776.595745 # average LoadLockedReq miss latency 501system.cpu.dcache.demand_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency 502system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 # average overall miss latency 503system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency 505system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 168system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 9421817 2.34% 98.82% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 3434032 0.85% 99.68% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 1296489 0.32% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle --- 322 unchanged lines hidden (view full) --- 498system.cpu.dcache.WriteReq_avg_miss_latency::total 17162.181168 # average WriteReq miss latency 499system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8776.595745 # average LoadLockedReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8776.595745 # average LoadLockedReq miss latency 501system.cpu.dcache.demand_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency 502system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 # average overall miss latency 503system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency 505system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 506system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked | 506system.cpu.dcache.blocked_cycles::no_targets 6644 # number of cycles access was blocked |
| 507system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked 509system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 507system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked 509system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 510system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked | 510system.cpu.dcache.avg_blocked_cycles::no_targets 11.928187 # average number of cycles each access was blocked |
| 511system.cpu.dcache.fast_writes 0 # number of fast writes performed 512system.cpu.dcache.cache_copies 0 # number of cache copies performed 513system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks 514system.cpu.dcache.writebacks::total 1101507 # number of writebacks 515system.cpu.dcache.ReadReq_mshr_hits::cpu.data 378352 # number of ReadReq MSHR hits 516system.cpu.dcache.ReadReq_mshr_hits::total 378352 # number of ReadReq MSHR hits 517system.cpu.dcache.WriteReq_mshr_hits::cpu.data 999317 # number of WriteReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::total 999317 # number of WriteReq MSHR hits --- 204 unchanged lines hidden --- | 511system.cpu.dcache.fast_writes 0 # number of fast writes performed 512system.cpu.dcache.cache_copies 0 # number of cache copies performed 513system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks 514system.cpu.dcache.writebacks::total 1101507 # number of writebacks 515system.cpu.dcache.ReadReq_mshr_hits::cpu.data 378352 # number of ReadReq MSHR hits 516system.cpu.dcache.ReadReq_mshr_hits::total 378352 # number of ReadReq MSHR hits 517system.cpu.dcache.WriteReq_mshr_hits::cpu.data 999317 # number of WriteReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::total 999317 # number of WriteReq MSHR hits --- 204 unchanged lines hidden --- |