| stats.txt (8983:8800b05e1cb3) | stats.txt (9035:1e783db0f3af) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.233090 # Number of seconds simulated 4sim_ticks 233090215000 # Number of ticks simulated 5final_tick 233090215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.233058 # Number of seconds simulated 4sim_ticks 233057542500 # Number of ticks simulated 5final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 75004 # Simulator instruction rate (inst/s) 8host_op_rate 84493 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34350324 # Simulator tick rate (ticks/s) 10host_mem_usage 237136 # Number of bytes of host memory used 11host_seconds 6785.68 # Real time elapsed on the host 12sim_insts 508954971 # Number of instructions simulated 13sim_ops 573341532 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 15203328 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 248448 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10942400 # Number of bytes written to this memory 17system.physmem.num_reads 237552 # Number of read requests responded to by this memory 18system.physmem.num_writes 170975 # Number of write requests responded to by this memory | 7host_inst_rate 104599 # Simulator instruction rate (inst/s) 8host_op_rate 117832 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47897344 # Simulator tick rate (ticks/s) 10host_mem_usage 237516 # Number of bytes of host memory used 11host_seconds 4865.77 # Real time elapsed on the host 12sim_insts 508954936 # Number of instructions simulated 13sim_ops 573341497 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 15214144 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10947904 # Number of bytes written to this memory 17system.physmem.num_reads 237721 # Number of read requests responded to by this memory 18system.physmem.num_writes 171061 # Number of write requests responded to by this memory |
| 19system.physmem.num_other 0 # Number of other requests responded to by this memory | 19system.physmem.num_other 0 # Number of other requests responded to by this memory |
| 20system.physmem.bw_read 65225080 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1065888 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 46944914 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 112169994 # Total bandwidth to/from this memory (bytes/s) | 20system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s) |
| 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.itb.read_accesses 0 # DTB read accesses 61system.cpu.itb.write_accesses 0 # DTB write accesses 62system.cpu.itb.inst_accesses 0 # ITB inst accesses 63system.cpu.itb.hits 0 # DTB hits 64system.cpu.itb.misses 0 # DTB misses 65system.cpu.itb.accesses 0 # DTB accesses 66system.cpu.workload.num_syscalls 548 # Number of system calls | 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.itb.read_accesses 0 # DTB read accesses 61system.cpu.itb.write_accesses 0 # DTB write accesses 62system.cpu.itb.inst_accesses 0 # ITB inst accesses 63system.cpu.itb.hits 0 # DTB hits 64system.cpu.itb.misses 0 # DTB misses 65system.cpu.itb.accesses 0 # DTB accesses 66system.cpu.workload.num_syscalls 548 # Number of system calls |
| 67system.cpu.numCycles 466180431 # number of cpu cycles simulated | 67system.cpu.numCycles 466115086 # number of cpu cycles simulated |
| 68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 70system.cpu.BPredUnit.lookups 200556895 # Number of BP lookups 71system.cpu.BPredUnit.condPredicted 157701783 # Number of conditional branches predicted 72system.cpu.BPredUnit.condIncorrect 13206687 # Number of conditional branches incorrect 73system.cpu.BPredUnit.BTBLookups 107805920 # Number of BTB lookups 74system.cpu.BPredUnit.BTBHits 98841530 # Number of BTB hits | 70system.cpu.BPredUnit.lookups 200399400 # Number of BP lookups 71system.cpu.BPredUnit.condPredicted 157559949 # Number of conditional branches predicted 72system.cpu.BPredUnit.condIncorrect 13227368 # Number of conditional branches incorrect 73system.cpu.BPredUnit.BTBLookups 107557824 # Number of BTB lookups 74system.cpu.BPredUnit.BTBHits 98829929 # Number of BTB hits |
| 75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 76system.cpu.BPredUnit.usedRAS 10112840 # Number of times the RAS was used to get a target. 77system.cpu.BPredUnit.RASInCorrect 2450569 # Number of incorrect RAS predictions. 78system.cpu.fetch.icacheStallCycles 137282908 # Number of cycles fetch is stalled on an Icache miss 79system.cpu.fetch.Insts 897241370 # Number of instructions fetch has processed 80system.cpu.fetch.Branches 200556895 # Number of branches that fetch encountered 81system.cpu.fetch.predictedBranches 108954370 # Number of branches that fetch has predicted taken 82system.cpu.fetch.Cycles 197651477 # Number of cycles fetch has run and was not squashing or blocked 83system.cpu.fetch.SquashCycles 54011479 # Number of cycles fetch has spent squashing 84system.cpu.fetch.BlockedCycles 89011796 # Number of cycles fetch has spent blocked 85system.cpu.fetch.MiscStallCycles 101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 86system.cpu.fetch.PendingTrapStallCycles 1558 # Number of stall cycles due to pending traps 87system.cpu.fetch.CacheLines 126941311 # Number of cache lines fetched 88system.cpu.fetch.IcacheSquashes 3919273 # Number of outstanding Icache misses that were squashed 89system.cpu.fetch.rateDist::samples 462356637 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::mean 2.264737 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::stdev 3.102062 # Number of instructions fetched each cycle (Total) | 76system.cpu.BPredUnit.usedRAS 10084316 # Number of times the RAS was used to get a target. 77system.cpu.BPredUnit.RASInCorrect 2451057 # Number of incorrect RAS predictions. 78system.cpu.fetch.icacheStallCycles 137234241 # Number of cycles fetch is stalled on an Icache miss 79system.cpu.fetch.Insts 896616118 # Number of instructions fetch has processed 80system.cpu.fetch.Branches 200399400 # Number of branches that fetch encountered 81system.cpu.fetch.predictedBranches 108914245 # Number of branches that fetch has predicted taken 82system.cpu.fetch.Cycles 197636410 # Number of cycles fetch has run and was not squashing or blocked 83system.cpu.fetch.SquashCycles 54052361 # Number of cycles fetch has spent squashing 84system.cpu.fetch.BlockedCycles 88992455 # Number of cycles fetch has spent blocked 85system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 86system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps 87system.cpu.fetch.CacheLines 126860220 # Number of cache lines fetched 88system.cpu.fetch.IcacheSquashes 3882835 # Number of outstanding Icache misses that were squashed 89system.cpu.fetch.rateDist::samples 462293499 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::mean 2.263975 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::stdev 3.101557 # Number of instructions fetched each cycle (Total) |
| 92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 93system.cpu.fetch.rateDist::0 264718484 57.25% 57.25% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::1 16102215 3.48% 60.74% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::2 21528039 4.66% 65.39% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::3 22972257 4.97% 70.36% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::4 24519479 5.30% 75.66% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::5 13176471 2.85% 78.51% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::6 13363017 2.89% 81.40% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::7 12910820 2.79% 84.20% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::8 73065855 15.80% 100.00% # Number of instructions fetched each cycle (Total) | 93system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% # Number of instructions fetched each cycle (Total) |
| 102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 105system.cpu.fetch.rateDist::total 462356637 # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.branchRate 0.430213 # Number of branch fetches per cycle 107system.cpu.fetch.rate 1.924665 # Number of inst fetches per cycle 108system.cpu.decode.IdleCycles 152349400 # Number of cycles decode is idle 109system.cpu.decode.BlockedCycles 84610781 # Number of cycles decode is blocked 110system.cpu.decode.RunCycles 182515551 # Number of cycles decode is running 111system.cpu.decode.UnblockCycles 4600527 # Number of cycles decode is unblocking 112system.cpu.decode.SquashCycles 38280378 # Number of cycles decode is squashing 113system.cpu.decode.BranchResolved 32264539 # Number of times decode resolved a branch 114system.cpu.decode.BranchMispred 131208 # Number of times decode detected a branch misprediction 115system.cpu.decode.DecodedInsts 977458438 # Number of instructions handled by decode 116system.cpu.decode.SquashedInsts 310007 # Number of squashed instructions handled by decode 117system.cpu.rename.SquashCycles 38280378 # Number of cycles rename is squashing 118system.cpu.rename.IdleCycles 165802120 # Number of cycles rename is idle 119system.cpu.rename.BlockCycles 6702227 # Number of cycles rename is blocking 120system.cpu.rename.serializeStallCycles 64599197 # count of cycles rename stalled for serializing inst 121system.cpu.rename.RunCycles 173513863 # Number of cycles rename is running 122system.cpu.rename.UnblockCycles 13458852 # Number of cycles rename is unblocking 123system.cpu.rename.RenamedInsts 899149269 # Number of instructions processed by rename 124system.cpu.rename.ROBFullEvents 1570 # Number of times rename has blocked due to ROB full 125system.cpu.rename.IQFullEvents 2810073 # Number of times rename has blocked due to IQ full 126system.cpu.rename.LSQFullEvents 7803626 # Number of times rename has blocked due to LSQ full 127system.cpu.rename.FullRegisterEvents 65 # Number of times there has been no free registers 128system.cpu.rename.RenamedOperands 1049469958 # Number of destination operands rename has renamed 129system.cpu.rename.RenameLookups 3916326628 # Number of register rename lookups that rename has made 130system.cpu.rename.int_rename_lookups 3916321968 # Number of integer rename lookups 131system.cpu.rename.fp_rename_lookups 4660 # Number of floating rename lookups 132system.cpu.rename.CommittedMaps 672199888 # Number of HB maps that are committed 133system.cpu.rename.UndoneMaps 377270070 # Number of HB maps that are undone due to squashing 134system.cpu.rename.serializingInsts 5958245 # count of serializing insts renamed 135system.cpu.rename.tempSerializingInsts 5953011 # count of temporary serializing insts renamed 136system.cpu.rename.skidInsts 72720727 # count of insts added to the skid buffer 137system.cpu.memDep0.insertedLoads 187283500 # Number of loads inserted to the mem dependence unit. 138system.cpu.memDep0.insertedStores 75086036 # Number of stores inserted to the mem dependence unit. 139system.cpu.memDep0.conflictingLoads 17235466 # Number of conflicting loads. 140system.cpu.memDep0.conflictingStores 11153184 # Number of conflicting stores. 141system.cpu.iq.iqInstsAdded 806543834 # Number of instructions added to the IQ (excludes non-spec) 142system.cpu.iq.iqNonSpecInstsAdded 6798395 # Number of non-speculative instructions added to the IQ 143system.cpu.iq.iqInstsIssued 700450406 # Number of instructions issued 144system.cpu.iq.iqSquashedInstsIssued 1593652 # Number of squashed instructions issued 145system.cpu.iq.iqSquashedInstsExamined 237057994 # Number of squashed instructions iterated over during squash; mainly for profiling 146system.cpu.iq.iqSquashedOperandsExamined 599635413 # Number of squashed operands that are examined and possibly removed from graph 147system.cpu.iq.iqSquashedNonSpecRemoved 3077315 # Number of squashed non-spec instructions that were removed 148system.cpu.iq.issued_per_cycle::samples 462356637 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::mean 1.514957 # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::stdev 1.708817 # Number of insts issued each cycle | 105system.cpu.fetch.rateDist::total 462293499 # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.branchRate 0.429935 # Number of branch fetches per cycle 107system.cpu.fetch.rate 1.923594 # Number of inst fetches per cycle 108system.cpu.decode.IdleCycles 152295850 # Number of cycles decode is idle 109system.cpu.decode.BlockedCycles 84600682 # Number of cycles decode is blocked 110system.cpu.decode.RunCycles 182545472 # Number of cycles decode is running 111system.cpu.decode.UnblockCycles 4580461 # Number of cycles decode is unblocking 112system.cpu.decode.SquashCycles 38271034 # Number of cycles decode is squashing 113system.cpu.decode.BranchResolved 32275508 # Number of times decode resolved a branch 114system.cpu.decode.BranchMispred 160463 # Number of times decode detected a branch misprediction 115system.cpu.decode.DecodedInsts 977106792 # Number of instructions handled by decode 116system.cpu.decode.SquashedInsts 311018 # Number of squashed instructions handled by decode 117system.cpu.rename.SquashCycles 38271034 # Number of cycles rename is squashing 118system.cpu.rename.IdleCycles 165689191 # Number of cycles rename is idle 119system.cpu.rename.BlockCycles 6700759 # Number of cycles rename is blocking 120system.cpu.rename.serializeStallCycles 64642468 # count of cycles rename stalled for serializing inst 121system.cpu.rename.RunCycles 173582675 # Number of cycles rename is running 122system.cpu.rename.UnblockCycles 13407372 # Number of cycles rename is unblocking 123system.cpu.rename.RenamedInsts 899108485 # Number of instructions processed by rename 124system.cpu.rename.ROBFullEvents 1442 # Number of times rename has blocked due to ROB full 125system.cpu.rename.IQFullEvents 2810546 # Number of times rename has blocked due to IQ full 126system.cpu.rename.LSQFullEvents 7739563 # Number of times rename has blocked due to LSQ full 127system.cpu.rename.FullRegisterEvents 106 # Number of times there has been no free registers 128system.cpu.rename.RenamedOperands 1049429059 # Number of destination operands rename has renamed 129system.cpu.rename.RenameLookups 3915911188 # Number of register rename lookups that rename has made 130system.cpu.rename.int_rename_lookups 3915906253 # Number of integer rename lookups 131system.cpu.rename.fp_rename_lookups 4935 # Number of floating rename lookups 132system.cpu.rename.CommittedMaps 672199832 # Number of HB maps that are committed 133system.cpu.rename.UndoneMaps 377229227 # Number of HB maps that are undone due to squashing 134system.cpu.rename.serializingInsts 5987863 # count of serializing insts renamed 135system.cpu.rename.tempSerializingInsts 5982547 # count of temporary serializing insts renamed 136system.cpu.rename.skidInsts 72814411 # count of insts added to the skid buffer 137system.cpu.memDep0.insertedLoads 187298810 # Number of loads inserted to the mem dependence unit. 138system.cpu.memDep0.insertedStores 75062120 # Number of stores inserted to the mem dependence unit. 139system.cpu.memDep0.conflictingLoads 17028922 # Number of conflicting loads. 140system.cpu.memDep0.conflictingStores 10874751 # Number of conflicting stores. 141system.cpu.iq.iqInstsAdded 806565254 # Number of instructions added to the IQ (excludes non-spec) 142system.cpu.iq.iqNonSpecInstsAdded 6815793 # Number of non-speculative instructions added to the IQ 143system.cpu.iq.iqInstsIssued 700720615 # Number of instructions issued 144system.cpu.iq.iqSquashedInstsIssued 1613210 # Number of squashed instructions issued 145system.cpu.iq.iqSquashedInstsExamined 237113606 # Number of squashed instructions iterated over during squash; mainly for profiling 146system.cpu.iq.iqSquashedOperandsExamined 598814504 # Number of squashed operands that are examined and possibly removed from graph 147system.cpu.iq.iqSquashedNonSpecRemoved 3094720 # Number of squashed non-spec instructions that were removed 148system.cpu.iq.issued_per_cycle::samples 462293499 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::mean 1.515748 # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::stdev 1.710183 # Number of insts issued each cycle |
| 151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 152system.cpu.iq.issued_per_cycle::0 192897981 41.72% 41.72% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::1 75235662 16.27% 57.99% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::2 69361266 15.00% 72.99% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::3 61039846 13.20% 86.20% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::4 35358169 7.65% 93.84% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::5 15549191 3.36% 97.21% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::6 7530638 1.63% 98.84% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::7 4060857 0.88% 99.71% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::8 1323027 0.29% 100.00% # Number of insts issued each cycle | 152system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% # Number of insts issued each cycle |
| 161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 164system.cpu.iq.issued_per_cycle::total 462356637 # Number of insts issued each cycle | 164system.cpu.iq.issued_per_cycle::total 462293499 # Number of insts issued each cycle |
| 165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 166system.cpu.iq.fu_full::IntAlu 463542 4.68% 4.68% # attempts to use FU when none available 167system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available 168system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available 174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available 195system.cpu.iq.fu_full::MemRead 6723177 67.88% 72.56% # attempts to use FU when none available 196system.cpu.iq.fu_full::MemWrite 2717455 27.44% 100.00% # attempts to use FU when none available | 166system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% # attempts to use FU when none available 167system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% # attempts to use FU when none available 168system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% # attempts to use FU when none available 174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% # attempts to use FU when none available 195system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% # attempts to use FU when none available 196system.cpu.iq.fu_full::MemWrite 2738977 27.51% 100.00% # attempts to use FU when none available |
| 197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 200system.cpu.iq.FU_type_0::IntAlu 472173393 67.41% 67.41% # Type of FU issued 201system.cpu.iq.FU_type_0::IntMult 385744 0.06% 67.47% # Type of FU issued 202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.47% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatAdd 178 0.00% 67.47% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.47% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.47% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.47% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.47% # Type of FU issued 208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.47% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.47% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.47% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.47% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.47% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.47% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.47% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.47% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.47% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.47% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.47% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.47% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.47% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.47% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.47% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.47% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.47% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.47% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued 229system.cpu.iq.FU_type_0::MemRead 162454570 23.19% 90.66% # Type of FU issued 230system.cpu.iq.FU_type_0::MemWrite 65436518 9.34% 100.00% # Type of FU issued | 200system.cpu.iq.FU_type_0::IntAlu 472287152 67.40% 67.40% # Type of FU issued 201system.cpu.iq.FU_type_0::IntMult 386091 0.06% 67.46% # Type of FU issued 202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatAdd 198 0.00% 67.46% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued 208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued 229system.cpu.iq.FU_type_0::MemRead 162565842 23.20% 90.66% # Type of FU issued 230system.cpu.iq.FU_type_0::MemWrite 65481329 9.34% 100.00% # Type of FU issued |
| 231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 233system.cpu.iq.FU_type_0::total 700450406 # Type of FU issued 234system.cpu.iq.rate 1.502531 # Inst issue rate 235system.cpu.iq.fu_busy_cnt 9904174 # FU busy when requested 236system.cpu.iq.fu_busy_rate 0.014140 # FU busy rate (busy events/executed inst) 237system.cpu.iq.int_inst_queue_reads 1874754883 # Number of integer instruction queue reads 238system.cpu.iq.int_inst_queue_writes 1050459229 # Number of integer instruction queue writes 239system.cpu.iq.int_inst_queue_wakeup_accesses 668042045 # Number of integer instruction queue wakeup accesses 240system.cpu.iq.fp_inst_queue_reads 392 # Number of floating instruction queue reads 241system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes | 233system.cpu.iq.FU_type_0::total 700720615 # Type of FU issued 234system.cpu.iq.rate 1.503321 # Inst issue rate 235system.cpu.iq.fu_busy_cnt 9955350 # FU busy when requested 236system.cpu.iq.fu_busy_rate 0.014207 # FU busy rate (busy events/executed inst) 237system.cpu.iq.int_inst_queue_reads 1875302857 # Number of integer instruction queue reads 238system.cpu.iq.int_inst_queue_writes 1050553482 # Number of integer instruction queue writes 239system.cpu.iq.int_inst_queue_wakeup_accesses 668216510 # Number of integer instruction queue wakeup accesses 240system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads 241system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes |
| 242system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 242system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 243system.cpu.iq.int_alu_accesses 710354382 # Number of integer alu accesses 244system.cpu.iq.fp_alu_accesses 198 # Number of floating point alu accesses 245system.cpu.iew.lsq.thread0.forwLoads 9116513 # Number of loads that had data forwarded from stores | 243system.cpu.iq.int_alu_accesses 710675747 # Number of integer alu accesses 244system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses 245system.cpu.iew.lsq.thread0.forwLoads 9109880 # Number of loads that had data forwarded from stores |
| 246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 247system.cpu.iew.lsq.thread0.squashedLoads 60510496 # Number of loads squashed 248system.cpu.iew.lsq.thread0.ignoredResponses 49356 # Number of memory responses ignored because the instruction is squashed 249system.cpu.iew.lsq.thread0.memOrderViolation 63473 # Number of memory ordering violations 250system.cpu.iew.lsq.thread0.squashedStores 17482111 # Number of stores squashed | 247system.cpu.iew.lsq.thread0.squashedLoads 60525813 # Number of loads squashed 248system.cpu.iew.lsq.thread0.ignoredResponses 50692 # Number of memory responses ignored because the instruction is squashed 249system.cpu.iew.lsq.thread0.memOrderViolation 63405 # Number of memory ordering violations 250system.cpu.iew.lsq.thread0.squashedStores 17458202 # Number of stores squashed |
| 251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 253system.cpu.iew.lsq.thread0.rescheduledLoads 20858 # Number of loads that were rescheduled 254system.cpu.iew.lsq.thread0.cacheBlocked 384 # Number of times an access to memory failed due to the cache being blocked | 253system.cpu.iew.lsq.thread0.rescheduledLoads 20818 # Number of loads that were rescheduled 254system.cpu.iew.lsq.thread0.cacheBlocked 376 # Number of times an access to memory failed due to the cache being blocked |
| 255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 256system.cpu.iew.iewSquashCycles 38280378 # Number of cycles IEW is squashing 257system.cpu.iew.iewBlockCycles 2896329 # Number of cycles IEW is blocking 258system.cpu.iew.iewUnblockCycles 176068 # Number of cycles IEW is unblocking 259system.cpu.iew.iewDispatchedInsts 822095360 # Number of instructions dispatched to IQ 260system.cpu.iew.iewDispSquashedInsts 8083425 # Number of squashed instructions skipped by dispatch 261system.cpu.iew.iewDispLoadInsts 187283500 # Number of dispatched load instructions 262system.cpu.iew.iewDispStoreInsts 75086036 # Number of dispatched store instructions 263system.cpu.iew.iewDispNonSpecInsts 5309620 # Number of dispatched non-speculative instructions 264system.cpu.iew.iewIQFullEvents 85965 # Number of times the IQ has become full, causing a stall 265system.cpu.iew.iewLSQFullEvents 9347 # Number of times the LSQ has become full, causing a stall 266system.cpu.iew.memOrderViolationEvents 63473 # Number of memory order violations 267system.cpu.iew.predictedTakenIncorrect 10562567 # Number of branches that were predicted taken incorrectly 268system.cpu.iew.predictedNotTakenIncorrect 7713138 # Number of branches that were predicted not taken incorrectly 269system.cpu.iew.branchMispredicts 18275705 # Number of branch mispredicts detected at execute 270system.cpu.iew.iewExecutedInsts 681639675 # Number of executed instructions 271system.cpu.iew.iewExecLoadInsts 155144326 # Number of load instructions executed 272system.cpu.iew.iewExecSquashedInsts 18810731 # Number of squashed instructions skipped in execute | 256system.cpu.iew.iewSquashCycles 38271034 # Number of cycles IEW is squashing 257system.cpu.iew.iewBlockCycles 2890868 # Number of cycles IEW is blocking 258system.cpu.iew.iewUnblockCycles 175492 # Number of cycles IEW is unblocking 259system.cpu.iew.iewDispatchedInsts 822161545 # Number of instructions dispatched to IQ 260system.cpu.iew.iewDispSquashedInsts 8144996 # Number of squashed instructions skipped by dispatch 261system.cpu.iew.iewDispLoadInsts 187298810 # Number of dispatched load instructions 262system.cpu.iew.iewDispStoreInsts 75062120 # Number of dispatched store instructions 263system.cpu.iew.iewDispNonSpecInsts 5327019 # Number of dispatched non-speculative instructions 264system.cpu.iew.iewIQFullEvents 85808 # Number of times the IQ has become full, causing a stall 265system.cpu.iew.iewLSQFullEvents 8514 # Number of times the LSQ has become full, causing a stall 266system.cpu.iew.memOrderViolationEvents 63405 # Number of memory order violations 267system.cpu.iew.predictedTakenIncorrect 10568276 # Number of branches that were predicted taken incorrectly 268system.cpu.iew.predictedNotTakenIncorrect 7702731 # Number of branches that were predicted not taken incorrectly 269system.cpu.iew.branchMispredicts 18271007 # Number of branch mispredicts detected at execute 270system.cpu.iew.iewExecutedInsts 681861282 # Number of executed instructions 271system.cpu.iew.iewExecLoadInsts 155223597 # Number of load instructions executed 272system.cpu.iew.iewExecSquashedInsts 18859333 # Number of squashed instructions skipped in execute |
| 273system.cpu.iew.exec_swp 0 # number of swp insts executed | 273system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 274system.cpu.iew.exec_nop 8753131 # number of nop insts executed 275system.cpu.iew.exec_refs 219063000 # number of memory reference insts executed 276system.cpu.iew.exec_branches 141943727 # Number of branches executed 277system.cpu.iew.exec_stores 63918674 # Number of stores executed 278system.cpu.iew.exec_rate 1.462180 # Inst execution rate 279system.cpu.iew.wb_sent 672829860 # cumulative count of insts sent to commit 280system.cpu.iew.wb_count 668042061 # cumulative count of insts written-back 281system.cpu.iew.wb_producers 381675027 # num instructions producing a value 282system.cpu.iew.wb_consumers 656276447 # num instructions consuming a value | 274system.cpu.iew.exec_nop 8780498 # number of nop insts executed 275system.cpu.iew.exec_refs 219185272 # number of memory reference insts executed 276system.cpu.iew.exec_branches 141958281 # Number of branches executed 277system.cpu.iew.exec_stores 63961675 # Number of stores executed 278system.cpu.iew.exec_rate 1.462860 # Inst execution rate 279system.cpu.iew.wb_sent 673014173 # cumulative count of insts sent to commit 280system.cpu.iew.wb_count 668216526 # cumulative count of insts written-back 281system.cpu.iew.wb_producers 381765084 # num instructions producing a value 282system.cpu.iew.wb_consumers 656387982 # num instructions consuming a value |
| 283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 284system.cpu.iew.wb_rate 1.433012 # insts written-back per cycle 285system.cpu.iew.wb_fanout 0.581577 # average fanout of values written-back | 284system.cpu.iew.wb_rate 1.433587 # insts written-back per cycle 285system.cpu.iew.wb_fanout 0.581615 # average fanout of values written-back |
| 286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 287system.cpu.commit.commitCommittedInsts 510298855 # The number of committed instructions 288system.cpu.commit.commitCommittedOps 574685416 # The number of committed instructions 289system.cpu.commit.commitSquashedInsts 247426936 # The number of squashed insts skipped by commit 290system.cpu.commit.commitNonSpecStalls 3721080 # The number of times commit has been forced to stall to communicate backwards 291system.cpu.commit.branchMispredicts 15423001 # The number of times a branch was mispredicted 292system.cpu.commit.committed_per_cycle::samples 424076260 # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::mean 1.355146 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::stdev 2.070427 # Number of insts commited each cycle | 287system.cpu.commit.commitCommittedInsts 510298820 # The number of committed instructions 288system.cpu.commit.commitCommittedOps 574685381 # The number of committed instructions 289system.cpu.commit.commitSquashedInsts 247493136 # The number of squashed insts skipped by commit 290system.cpu.commit.commitNonSpecStalls 3721073 # The number of times commit has been forced to stall to communicate backwards 291system.cpu.commit.branchMispredicts 15415046 # The number of times a branch was mispredicted 292system.cpu.commit.committed_per_cycle::samples 424022466 # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::mean 1.355318 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::stdev 2.071268 # Number of insts commited each cycle |
| 295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 296system.cpu.commit.committed_per_cycle::0 206251262 48.64% 48.64% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::1 102654685 24.21% 72.84% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::2 40133314 9.46% 82.31% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::3 19523005 4.60% 86.91% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::4 17475751 4.12% 91.03% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::5 7238789 1.71% 92.74% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::6 7738360 1.82% 94.56% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::7 3820773 0.90% 95.46% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::8 19240321 4.54% 100.00% # Number of insts commited each cycle | 296system.cpu.commit.committed_per_cycle::0 206316988 48.66% 48.66% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::1 102533575 24.18% 72.84% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::2 40145036 9.47% 82.31% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::3 19513900 4.60% 86.91% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::4 17437160 4.11% 91.02% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::5 7239208 1.71% 92.73% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::6 7753458 1.83% 94.56% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::7 3810522 0.90% 95.45% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::8 19272619 4.55% 100.00% # Number of insts commited each cycle |
| 305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 308system.cpu.commit.committed_per_cycle::total 424076260 # Number of insts commited each cycle 309system.cpu.commit.committedInsts 510298855 # Number of instructions committed 310system.cpu.commit.committedOps 574685416 # Number of ops (including micro ops) committed | 308system.cpu.commit.committed_per_cycle::total 424022466 # Number of insts commited each cycle 309system.cpu.commit.committedInsts 510298820 # Number of instructions committed 310system.cpu.commit.committedOps 574685381 # Number of ops (including micro ops) committed |
| 311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 312system.cpu.commit.refs 184376929 # Number of memory references committed 313system.cpu.commit.loads 126773004 # Number of loads committed | 312system.cpu.commit.refs 184376915 # Number of memory references committed 313system.cpu.commit.loads 126772997 # Number of loads committed |
| 314system.cpu.commit.membars 1488542 # Number of memory barriers committed | 314system.cpu.commit.membars 1488542 # Number of memory barriers committed |
| 315system.cpu.commit.branches 120192189 # Number of branches committed | 315system.cpu.commit.branches 120192182 # Number of branches committed |
| 316system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. | 316system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. |
| 317system.cpu.commit.int_insts 473701493 # Number of committed integer instructions. | 317system.cpu.commit.int_insts 473701465 # Number of committed integer instructions. |
| 318system.cpu.commit.function_calls 9757362 # Number of function calls committed. | 318system.cpu.commit.function_calls 9757362 # Number of function calls committed. |
| 319system.cpu.commit.bw_lim_events 19240321 # number cycles where commit BW limit reached | 319system.cpu.commit.bw_lim_events 19272619 # number cycles where commit BW limit reached |
| 320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 321system.cpu.rob.rob_reads 1226941153 # The number of ROB reads 322system.cpu.rob.rob_writes 1682652305 # The number of ROB writes 323system.cpu.timesIdled 99109 # Number of times that the entire CPU went into an idle state and unscheduled itself 324system.cpu.idleCycles 3823794 # Total number of cycles that the CPU has spent unscheduled due to idling 325system.cpu.committedInsts 508954971 # Number of Instructions Simulated 326system.cpu.committedOps 573341532 # Number of Ops (including micro ops) Simulated 327system.cpu.committedInsts_total 508954971 # Number of Instructions Simulated 328system.cpu.cpi 0.915956 # CPI: Cycles Per Instruction 329system.cpu.cpi_total 0.915956 # CPI: Total CPI of All Threads 330system.cpu.ipc 1.091755 # IPC: Instructions Per Cycle 331system.cpu.ipc_total 1.091755 # IPC: Total IPC of All Threads 332system.cpu.int_regfile_reads 3162535433 # number of integer regfile reads 333system.cpu.int_regfile_writes 777163195 # number of integer regfile writes | 321system.cpu.rob.rob_reads 1226921226 # The number of ROB reads 322system.cpu.rob.rob_writes 1682775882 # The number of ROB writes 323system.cpu.timesIdled 98525 # Number of times that the entire CPU went into an idle state and unscheduled itself 324system.cpu.idleCycles 3821587 # Total number of cycles that the CPU has spent unscheduled due to idling 325system.cpu.committedInsts 508954936 # Number of Instructions Simulated 326system.cpu.committedOps 573341497 # Number of Ops (including micro ops) Simulated 327system.cpu.committedInsts_total 508954936 # Number of Instructions Simulated 328system.cpu.cpi 0.915828 # CPI: Cycles Per Instruction 329system.cpu.cpi_total 0.915828 # CPI: Total CPI of All Threads 330system.cpu.ipc 1.091908 # IPC: Instructions Per Cycle 331system.cpu.ipc_total 1.091908 # IPC: Total IPC of All Threads 332system.cpu.int_regfile_reads 3163594515 # number of integer regfile reads 333system.cpu.int_regfile_writes 777373809 # number of integer regfile writes |
| 334system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 334system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 335system.cpu.misc_regfile_reads 1130648260 # number of misc regfile reads 336system.cpu.misc_regfile_writes 4463980 # number of misc regfile writes 337system.cpu.icache.replacements 16198 # number of replacements 338system.cpu.icache.tagsinuse 1123.010204 # Cycle average of tags in use 339system.cpu.icache.total_refs 126921132 # Total number of references to valid blocks. 340system.cpu.icache.sampled_refs 18053 # Sample count of references to valid blocks. 341system.cpu.icache.avg_refs 7030.473162 # Average number of references to valid blocks. | 335system.cpu.misc_regfile_reads 1130092901 # number of misc regfile reads 336system.cpu.misc_regfile_writes 4463966 # number of misc regfile writes 337system.cpu.icache.replacements 16105 # number of replacements 338system.cpu.icache.tagsinuse 1117.727093 # Cycle average of tags in use 339system.cpu.icache.total_refs 126840323 # Total number of references to valid blocks. 340system.cpu.icache.sampled_refs 17981 # Sample count of references to valid blocks. 341system.cpu.icache.avg_refs 7054.130638 # Average number of references to valid blocks. |
| 342system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 342system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 343system.cpu.icache.occ_blocks::cpu.inst 1123.010204 # Average occupied blocks per requestor 344system.cpu.icache.occ_percent::cpu.inst 0.548345 # Average percentage of cache occupancy 345system.cpu.icache.occ_percent::total 0.548345 # Average percentage of cache occupancy 346system.cpu.icache.ReadReq_hits::cpu.inst 126921167 # number of ReadReq hits 347system.cpu.icache.ReadReq_hits::total 126921167 # number of ReadReq hits 348system.cpu.icache.demand_hits::cpu.inst 126921167 # number of demand (read+write) hits 349system.cpu.icache.demand_hits::total 126921167 # number of demand (read+write) hits 350system.cpu.icache.overall_hits::cpu.inst 126921167 # number of overall hits 351system.cpu.icache.overall_hits::total 126921167 # number of overall hits 352system.cpu.icache.ReadReq_misses::cpu.inst 20144 # number of ReadReq misses 353system.cpu.icache.ReadReq_misses::total 20144 # number of ReadReq misses 354system.cpu.icache.demand_misses::cpu.inst 20144 # number of demand (read+write) misses 355system.cpu.icache.demand_misses::total 20144 # number of demand (read+write) misses 356system.cpu.icache.overall_misses::cpu.inst 20144 # number of overall misses 357system.cpu.icache.overall_misses::total 20144 # number of overall misses 358system.cpu.icache.ReadReq_miss_latency::cpu.inst 271671500 # number of ReadReq miss cycles 359system.cpu.icache.ReadReq_miss_latency::total 271671500 # number of ReadReq miss cycles 360system.cpu.icache.demand_miss_latency::cpu.inst 271671500 # number of demand (read+write) miss cycles 361system.cpu.icache.demand_miss_latency::total 271671500 # number of demand (read+write) miss cycles 362system.cpu.icache.overall_miss_latency::cpu.inst 271671500 # number of overall miss cycles 363system.cpu.icache.overall_miss_latency::total 271671500 # number of overall miss cycles 364system.cpu.icache.ReadReq_accesses::cpu.inst 126941311 # number of ReadReq accesses(hits+misses) 365system.cpu.icache.ReadReq_accesses::total 126941311 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.demand_accesses::cpu.inst 126941311 # number of demand (read+write) accesses 367system.cpu.icache.demand_accesses::total 126941311 # number of demand (read+write) accesses 368system.cpu.icache.overall_accesses::cpu.inst 126941311 # number of overall (read+write) accesses 369system.cpu.icache.overall_accesses::total 126941311 # number of overall (read+write) accesses 370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000159 # miss rate for ReadReq accesses 371system.cpu.icache.demand_miss_rate::cpu.inst 0.000159 # miss rate for demand accesses 372system.cpu.icache.overall_miss_rate::cpu.inst 0.000159 # miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13486.472399 # average ReadReq miss latency 374system.cpu.icache.demand_avg_miss_latency::cpu.inst 13486.472399 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::cpu.inst 13486.472399 # average overall miss latency | 343system.cpu.icache.occ_blocks::cpu.inst 1117.727093 # Average occupied blocks per requestor 344system.cpu.icache.occ_percent::cpu.inst 0.545765 # Average percentage of cache occupancy 345system.cpu.icache.occ_percent::total 0.545765 # Average percentage of cache occupancy 346system.cpu.icache.ReadReq_hits::cpu.inst 126840329 # number of ReadReq hits 347system.cpu.icache.ReadReq_hits::total 126840329 # number of ReadReq hits 348system.cpu.icache.demand_hits::cpu.inst 126840329 # number of demand (read+write) hits 349system.cpu.icache.demand_hits::total 126840329 # number of demand (read+write) hits 350system.cpu.icache.overall_hits::cpu.inst 126840329 # number of overall hits 351system.cpu.icache.overall_hits::total 126840329 # number of overall hits 352system.cpu.icache.ReadReq_misses::cpu.inst 19891 # number of ReadReq misses 353system.cpu.icache.ReadReq_misses::total 19891 # number of ReadReq misses 354system.cpu.icache.demand_misses::cpu.inst 19891 # number of demand (read+write) misses 355system.cpu.icache.demand_misses::total 19891 # number of demand (read+write) misses 356system.cpu.icache.overall_misses::cpu.inst 19891 # number of overall misses 357system.cpu.icache.overall_misses::total 19891 # number of overall misses 358system.cpu.icache.ReadReq_miss_latency::cpu.inst 267894500 # number of ReadReq miss cycles 359system.cpu.icache.ReadReq_miss_latency::total 267894500 # number of ReadReq miss cycles 360system.cpu.icache.demand_miss_latency::cpu.inst 267894500 # number of demand (read+write) miss cycles 361system.cpu.icache.demand_miss_latency::total 267894500 # number of demand (read+write) miss cycles 362system.cpu.icache.overall_miss_latency::cpu.inst 267894500 # number of overall miss cycles 363system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles 364system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses) 365system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses 367system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses 368system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses 369system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses 370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses 371system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses 372system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency 374system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency |
| 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed | 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 384system.cpu.icache.writebacks::writebacks 8 # number of writebacks 385system.cpu.icache.writebacks::total 8 # number of writebacks 386system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1838 # number of ReadReq MSHR hits 387system.cpu.icache.ReadReq_mshr_hits::total 1838 # number of ReadReq MSHR hits 388system.cpu.icache.demand_mshr_hits::cpu.inst 1838 # number of demand (read+write) MSHR hits 389system.cpu.icache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits 390system.cpu.icache.overall_mshr_hits::cpu.inst 1838 # number of overall MSHR hits 391system.cpu.icache.overall_mshr_hits::total 1838 # number of overall MSHR hits 392system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18306 # number of ReadReq MSHR misses 393system.cpu.icache.ReadReq_mshr_misses::total 18306 # number of ReadReq MSHR misses 394system.cpu.icache.demand_mshr_misses::cpu.inst 18306 # number of demand (read+write) MSHR misses 395system.cpu.icache.demand_mshr_misses::total 18306 # number of demand (read+write) MSHR misses 396system.cpu.icache.overall_mshr_misses::cpu.inst 18306 # number of overall MSHR misses 397system.cpu.icache.overall_mshr_misses::total 18306 # number of overall MSHR misses 398system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173356500 # number of ReadReq MSHR miss cycles 399system.cpu.icache.ReadReq_mshr_miss_latency::total 173356500 # number of ReadReq MSHR miss cycles 400system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173356500 # number of demand (read+write) MSHR miss cycles 401system.cpu.icache.demand_mshr_miss_latency::total 173356500 # number of demand (read+write) MSHR miss cycles 402system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173356500 # number of overall MSHR miss cycles 403system.cpu.icache.overall_mshr_miss_latency::total 173356500 # number of overall MSHR miss cycles 404system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000144 # mshr miss rate for ReadReq accesses 405system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000144 # mshr miss rate for demand accesses 406system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000144 # mshr miss rate for overall accesses 407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9469.927892 # average ReadReq mshr miss latency 408system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9469.927892 # average overall mshr miss latency 409system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9469.927892 # average overall mshr miss latency | 384system.cpu.icache.writebacks::writebacks 1 # number of writebacks 385system.cpu.icache.writebacks::total 1 # number of writebacks 386system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1759 # number of ReadReq MSHR hits 387system.cpu.icache.ReadReq_mshr_hits::total 1759 # number of ReadReq MSHR hits 388system.cpu.icache.demand_mshr_hits::cpu.inst 1759 # number of demand (read+write) MSHR hits 389system.cpu.icache.demand_mshr_hits::total 1759 # number of demand (read+write) MSHR hits 390system.cpu.icache.overall_mshr_hits::cpu.inst 1759 # number of overall MSHR hits 391system.cpu.icache.overall_mshr_hits::total 1759 # number of overall MSHR hits 392system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18132 # number of ReadReq MSHR misses 393system.cpu.icache.ReadReq_mshr_misses::total 18132 # number of ReadReq MSHR misses 394system.cpu.icache.demand_mshr_misses::cpu.inst 18132 # number of demand (read+write) MSHR misses 395system.cpu.icache.demand_mshr_misses::total 18132 # number of demand (read+write) MSHR misses 396system.cpu.icache.overall_mshr_misses::cpu.inst 18132 # number of overall MSHR misses 397system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses 398system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles 399system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles 400system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles 401system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles 402system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles 403system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles 404system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses 405system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses 406system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses 407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency 408system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency 409system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency |
| 410system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 410system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 411system.cpu.dcache.replacements 1204660 # number of replacements 412system.cpu.dcache.tagsinuse 4052.912718 # Cycle average of tags in use 413system.cpu.dcache.total_refs 197226176 # Total number of references to valid blocks. 414system.cpu.dcache.sampled_refs 1208756 # Sample count of references to valid blocks. 415system.cpu.dcache.avg_refs 163.164589 # Average number of references to valid blocks. | 411system.cpu.dcache.replacements 1204809 # number of replacements 412system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use 413system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks. 414system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks. 415system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks. |
| 416system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit. | 416system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit. |
| 417system.cpu.dcache.occ_blocks::cpu.data 4052.912718 # Average occupied blocks per requestor 418system.cpu.dcache.occ_percent::cpu.data 0.989481 # Average percentage of cache occupancy 419system.cpu.dcache.occ_percent::total 0.989481 # Average percentage of cache occupancy 420system.cpu.dcache.ReadReq_hits::cpu.data 139976270 # number of ReadReq hits 421system.cpu.dcache.ReadReq_hits::total 139976270 # number of ReadReq hits 422system.cpu.dcache.WriteReq_hits::cpu.data 52778956 # number of WriteReq hits 423system.cpu.dcache.WriteReq_hits::total 52778956 # number of WriteReq hits 424system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238371 # number of LoadLockedReq hits 425system.cpu.dcache.LoadLockedReq_hits::total 2238371 # number of LoadLockedReq hits 426system.cpu.dcache.StoreCondReq_hits::cpu.data 2231989 # number of StoreCondReq hits 427system.cpu.dcache.StoreCondReq_hits::total 2231989 # number of StoreCondReq hits 428system.cpu.dcache.demand_hits::cpu.data 192755226 # number of demand (read+write) hits 429system.cpu.dcache.demand_hits::total 192755226 # number of demand (read+write) hits 430system.cpu.dcache.overall_hits::cpu.data 192755226 # number of overall hits 431system.cpu.dcache.overall_hits::total 192755226 # number of overall hits 432system.cpu.dcache.ReadReq_misses::cpu.data 1318997 # number of ReadReq misses 433system.cpu.dcache.ReadReq_misses::total 1318997 # number of ReadReq misses 434system.cpu.dcache.WriteReq_misses::cpu.data 1460350 # number of WriteReq misses 435system.cpu.dcache.WriteReq_misses::total 1460350 # number of WriteReq misses 436system.cpu.dcache.LoadLockedReq_misses::cpu.data 74 # number of LoadLockedReq misses 437system.cpu.dcache.LoadLockedReq_misses::total 74 # number of LoadLockedReq misses 438system.cpu.dcache.demand_misses::cpu.data 2779347 # number of demand (read+write) misses 439system.cpu.dcache.demand_misses::total 2779347 # number of demand (read+write) misses 440system.cpu.dcache.overall_misses::cpu.data 2779347 # number of overall misses 441system.cpu.dcache.overall_misses::total 2779347 # number of overall misses 442system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287634500 # number of ReadReq miss cycles 443system.cpu.dcache.ReadReq_miss_latency::total 15287634500 # number of ReadReq miss cycles 444system.cpu.dcache.WriteReq_miss_latency::cpu.data 25192123491 # number of WriteReq miss cycles 445system.cpu.dcache.WriteReq_miss_latency::total 25192123491 # number of WriteReq miss cycles 446system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 676500 # number of LoadLockedReq miss cycles 447system.cpu.dcache.LoadLockedReq_miss_latency::total 676500 # number of LoadLockedReq miss cycles 448system.cpu.dcache.demand_miss_latency::cpu.data 40479757991 # number of demand (read+write) miss cycles 449system.cpu.dcache.demand_miss_latency::total 40479757991 # number of demand (read+write) miss cycles 450system.cpu.dcache.overall_miss_latency::cpu.data 40479757991 # number of overall miss cycles 451system.cpu.dcache.overall_miss_latency::total 40479757991 # number of overall miss cycles 452system.cpu.dcache.ReadReq_accesses::cpu.data 141295267 # number of ReadReq accesses(hits+misses) 453system.cpu.dcache.ReadReq_accesses::total 141295267 # number of ReadReq accesses(hits+misses) | 417system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor 418system.cpu.dcache.occ_percent::cpu.data 0.989479 # Average percentage of cache occupancy 419system.cpu.dcache.occ_percent::total 0.989479 # Average percentage of cache occupancy 420system.cpu.dcache.ReadReq_hits::cpu.data 140063979 # number of ReadReq hits 421system.cpu.dcache.ReadReq_hits::total 140063979 # number of ReadReq hits 422system.cpu.dcache.WriteReq_hits::cpu.data 52782968 # number of WriteReq hits 423system.cpu.dcache.WriteReq_hits::total 52782968 # number of WriteReq hits 424system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238489 # number of LoadLockedReq hits 425system.cpu.dcache.LoadLockedReq_hits::total 2238489 # number of LoadLockedReq hits 426system.cpu.dcache.StoreCondReq_hits::cpu.data 2231982 # number of StoreCondReq hits 427system.cpu.dcache.StoreCondReq_hits::total 2231982 # number of StoreCondReq hits 428system.cpu.dcache.demand_hits::cpu.data 192846947 # number of demand (read+write) hits 429system.cpu.dcache.demand_hits::total 192846947 # number of demand (read+write) hits 430system.cpu.dcache.overall_hits::cpu.data 192846947 # number of overall hits 431system.cpu.dcache.overall_hits::total 192846947 # number of overall hits 432system.cpu.dcache.ReadReq_misses::cpu.data 1318830 # number of ReadReq misses 433system.cpu.dcache.ReadReq_misses::total 1318830 # number of ReadReq misses 434system.cpu.dcache.WriteReq_misses::cpu.data 1456338 # number of WriteReq misses 435system.cpu.dcache.WriteReq_misses::total 1456338 # number of WriteReq misses 436system.cpu.dcache.LoadLockedReq_misses::cpu.data 78 # number of LoadLockedReq misses 437system.cpu.dcache.LoadLockedReq_misses::total 78 # number of LoadLockedReq misses 438system.cpu.dcache.demand_misses::cpu.data 2775168 # number of demand (read+write) misses 439system.cpu.dcache.demand_misses::total 2775168 # number of demand (read+write) misses 440system.cpu.dcache.overall_misses::cpu.data 2775168 # number of overall misses 441system.cpu.dcache.overall_misses::total 2775168 # number of overall misses 442system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287682000 # number of ReadReq miss cycles 443system.cpu.dcache.ReadReq_miss_latency::total 15287682000 # number of ReadReq miss cycles 444system.cpu.dcache.WriteReq_miss_latency::cpu.data 25164058992 # number of WriteReq miss cycles 445system.cpu.dcache.WriteReq_miss_latency::total 25164058992 # number of WriteReq miss cycles 446system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 845500 # number of LoadLockedReq miss cycles 447system.cpu.dcache.LoadLockedReq_miss_latency::total 845500 # number of LoadLockedReq miss cycles 448system.cpu.dcache.demand_miss_latency::cpu.data 40451740992 # number of demand (read+write) miss cycles 449system.cpu.dcache.demand_miss_latency::total 40451740992 # number of demand (read+write) miss cycles 450system.cpu.dcache.overall_miss_latency::cpu.data 40451740992 # number of overall miss cycles 451system.cpu.dcache.overall_miss_latency::total 40451740992 # number of overall miss cycles 452system.cpu.dcache.ReadReq_accesses::cpu.data 141382809 # number of ReadReq accesses(hits+misses) 453system.cpu.dcache.ReadReq_accesses::total 141382809 # number of ReadReq accesses(hits+misses) |
| 454system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 455system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) | 454system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 455system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) |
| 456system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238445 # number of LoadLockedReq accesses(hits+misses) 457system.cpu.dcache.LoadLockedReq_accesses::total 2238445 # number of LoadLockedReq accesses(hits+misses) 458system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231989 # number of StoreCondReq accesses(hits+misses) 459system.cpu.dcache.StoreCondReq_accesses::total 2231989 # number of StoreCondReq accesses(hits+misses) 460system.cpu.dcache.demand_accesses::cpu.data 195534573 # number of demand (read+write) accesses 461system.cpu.dcache.demand_accesses::total 195534573 # number of demand (read+write) accesses 462system.cpu.dcache.overall_accesses::cpu.data 195534573 # number of overall (read+write) accesses 463system.cpu.dcache.overall_accesses::total 195534573 # number of overall (read+write) accesses 464system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009335 # miss rate for ReadReq accesses 465system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026924 # miss rate for WriteReq accesses 466system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000033 # miss rate for LoadLockedReq accesses 467system.cpu.dcache.demand_miss_rate::cpu.data 0.014214 # miss rate for demand accesses 468system.cpu.dcache.overall_miss_rate::cpu.data 0.014214 # miss rate for overall accesses 469system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11590.348196 # average ReadReq miss latency 470system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17250.743651 # average WriteReq miss latency 471system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9141.891892 # average LoadLockedReq miss latency 472system.cpu.dcache.demand_avg_miss_latency::cpu.data 14564.485108 # average overall miss latency 473system.cpu.dcache.overall_avg_miss_latency::cpu.data 14564.485108 # average overall miss latency | 456system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238567 # number of LoadLockedReq accesses(hits+misses) 457system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses) 458system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses) 459system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses) 460system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses 461system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses 462system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses 463system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses 464system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses 465system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses 466system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses 467system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses 468system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses 469system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency 470system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency 471system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency 472system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency 473system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency |
| 474system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 474system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 475system.cpu.dcache.blocked_cycles::no_targets 560500 # number of cycles access was blocked | 475system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked |
| 476system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 476system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 477system.cpu.dcache.blocked::no_targets 94 # number of cycles access was blocked | 477system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked |
| 478system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 478system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 479system.cpu.dcache.avg_blocked_cycles::no_targets 5962.765957 # average number of cycles each access was blocked | 479system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked |
| 480system.cpu.dcache.fast_writes 0 # number of fast writes performed 481system.cpu.dcache.cache_copies 0 # number of cache copies performed | 480system.cpu.dcache.fast_writes 0 # number of fast writes performed 481system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 482system.cpu.dcache.writebacks::writebacks 1073398 # number of writebacks 483system.cpu.dcache.writebacks::total 1073398 # number of writebacks 484system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451124 # number of ReadReq MSHR hits 485system.cpu.dcache.ReadReq_mshr_hits::total 451124 # number of ReadReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1119210 # number of WriteReq MSHR hits 487system.cpu.dcache.WriteReq_mshr_hits::total 1119210 # number of WriteReq MSHR hits 488system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 74 # number of LoadLockedReq MSHR hits 489system.cpu.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits 490system.cpu.dcache.demand_mshr_hits::cpu.data 1570334 # number of demand (read+write) MSHR hits 491system.cpu.dcache.demand_mshr_hits::total 1570334 # number of demand (read+write) MSHR hits 492system.cpu.dcache.overall_mshr_hits::cpu.data 1570334 # number of overall MSHR hits 493system.cpu.dcache.overall_mshr_hits::total 1570334 # number of overall MSHR hits 494system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867873 # number of ReadReq MSHR misses 495system.cpu.dcache.ReadReq_mshr_misses::total 867873 # number of ReadReq MSHR misses 496system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341140 # number of WriteReq MSHR misses 497system.cpu.dcache.WriteReq_mshr_misses::total 341140 # number of WriteReq MSHR misses 498system.cpu.dcache.demand_mshr_misses::cpu.data 1209013 # number of demand (read+write) MSHR misses 499system.cpu.dcache.demand_mshr_misses::total 1209013 # number of demand (read+write) MSHR misses 500system.cpu.dcache.overall_mshr_misses::cpu.data 1209013 # number of overall MSHR misses 501system.cpu.dcache.overall_mshr_misses::total 1209013 # number of overall MSHR misses 502system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6213938000 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.ReadReq_mshr_miss_latency::total 6213938000 # number of ReadReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4372891497 # number of WriteReq MSHR miss cycles 505system.cpu.dcache.WriteReq_mshr_miss_latency::total 4372891497 # number of WriteReq MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10586829497 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.demand_mshr_miss_latency::total 10586829497 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10586829497 # number of overall MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::total 10586829497 # number of overall MSHR miss cycles 510system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006142 # mshr miss rate for ReadReq accesses 511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006290 # mshr miss rate for WriteReq accesses 512system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006183 # mshr miss rate for demand accesses 513system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006183 # mshr miss rate for overall accesses 514system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7159.962345 # average ReadReq mshr miss latency 515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12818.466017 # average WriteReq mshr miss latency 516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8756.588636 # average overall mshr miss latency 517system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8756.588636 # average overall mshr miss latency | 482system.cpu.dcache.writebacks::writebacks 1073322 # number of writebacks 483system.cpu.dcache.writebacks::total 1073322 # number of writebacks 484system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451055 # number of ReadReq MSHR hits 485system.cpu.dcache.ReadReq_mshr_hits::total 451055 # number of ReadReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1115056 # number of WriteReq MSHR hits 487system.cpu.dcache.WriteReq_mshr_hits::total 1115056 # number of WriteReq MSHR hits 488system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 78 # number of LoadLockedReq MSHR hits 489system.cpu.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits 490system.cpu.dcache.demand_mshr_hits::cpu.data 1566111 # number of demand (read+write) MSHR hits 491system.cpu.dcache.demand_mshr_hits::total 1566111 # number of demand (read+write) MSHR hits 492system.cpu.dcache.overall_mshr_hits::cpu.data 1566111 # number of overall MSHR hits 493system.cpu.dcache.overall_mshr_hits::total 1566111 # number of overall MSHR hits 494system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867775 # number of ReadReq MSHR misses 495system.cpu.dcache.ReadReq_mshr_misses::total 867775 # number of ReadReq MSHR misses 496system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341282 # number of WriteReq MSHR misses 497system.cpu.dcache.WriteReq_mshr_misses::total 341282 # number of WriteReq MSHR misses 498system.cpu.dcache.demand_mshr_misses::cpu.data 1209057 # number of demand (read+write) MSHR misses 499system.cpu.dcache.demand_mshr_misses::total 1209057 # number of demand (read+write) MSHR misses 500system.cpu.dcache.overall_mshr_misses::cpu.data 1209057 # number of overall MSHR misses 501system.cpu.dcache.overall_mshr_misses::total 1209057 # number of overall MSHR misses 502system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6208585000 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles 505system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles 510system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses 511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses 512system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses 513system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses 514system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency 515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency 516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency 517system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency |
| 518system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 518system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 519system.cpu.l2cache.replacements 218347 # number of replacements 520system.cpu.l2cache.tagsinuse 20950.026820 # Cycle average of tags in use 521system.cpu.l2cache.total_refs 1558196 # Total number of references to valid blocks. 522system.cpu.l2cache.sampled_refs 238767 # Sample count of references to valid blocks. 523system.cpu.l2cache.avg_refs 6.526011 # Average number of references to valid blocks. 524system.cpu.l2cache.warmup_cycle 170531011000 # Cycle when the warmup percentage was hit. 525system.cpu.l2cache.occ_blocks::writebacks 13687.762920 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_blocks::cpu.inst 201.638936 # Average occupied blocks per requestor 527system.cpu.l2cache.occ_blocks::cpu.data 7060.624965 # Average occupied blocks per requestor 528system.cpu.l2cache.occ_percent::writebacks 0.417717 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.inst 0.006154 # Average percentage of cache occupancy 530system.cpu.l2cache.occ_percent::cpu.data 0.215473 # Average percentage of cache occupancy 531system.cpu.l2cache.occ_percent::total 0.639344 # Average percentage of cache occupancy 532system.cpu.l2cache.ReadReq_hits::cpu.inst 14281 # number of ReadReq hits 533system.cpu.l2cache.ReadReq_hits::cpu.data 742482 # number of ReadReq hits 534system.cpu.l2cache.ReadReq_hits::total 756763 # number of ReadReq hits 535system.cpu.l2cache.Writeback_hits::writebacks 1073406 # number of Writeback hits 536system.cpu.l2cache.Writeback_hits::total 1073406 # number of Writeback hits 537system.cpu.l2cache.UpgradeReq_hits::cpu.data 203 # number of UpgradeReq hits 538system.cpu.l2cache.UpgradeReq_hits::total 203 # number of UpgradeReq hits 539system.cpu.l2cache.ReadExReq_hits::cpu.data 232563 # number of ReadExReq hits 540system.cpu.l2cache.ReadExReq_hits::total 232563 # number of ReadExReq hits 541system.cpu.l2cache.demand_hits::cpu.inst 14281 # number of demand (read+write) hits 542system.cpu.l2cache.demand_hits::cpu.data 975045 # number of demand (read+write) hits 543system.cpu.l2cache.demand_hits::total 989326 # number of demand (read+write) hits 544system.cpu.l2cache.overall_hits::cpu.inst 14281 # number of overall hits 545system.cpu.l2cache.overall_hits::cpu.data 975045 # number of overall hits 546system.cpu.l2cache.overall_hits::total 989326 # number of overall hits 547system.cpu.l2cache.ReadReq_misses::cpu.inst 3887 # number of ReadReq misses 548system.cpu.l2cache.ReadReq_misses::cpu.data 124728 # number of ReadReq misses 549system.cpu.l2cache.ReadReq_misses::total 128615 # number of ReadReq misses 550system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses 551system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses 552system.cpu.l2cache.ReadExReq_misses::cpu.data 108968 # number of ReadExReq misses 553system.cpu.l2cache.ReadExReq_misses::total 108968 # number of ReadExReq misses 554system.cpu.l2cache.demand_misses::cpu.inst 3887 # number of demand (read+write) misses 555system.cpu.l2cache.demand_misses::cpu.data 233696 # number of demand (read+write) misses 556system.cpu.l2cache.demand_misses::total 237583 # number of demand (read+write) misses 557system.cpu.l2cache.overall_misses::cpu.inst 3887 # number of overall misses 558system.cpu.l2cache.overall_misses::cpu.data 233696 # number of overall misses 559system.cpu.l2cache.overall_misses::total 237583 # number of overall misses 560system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133254500 # number of ReadReq miss cycles 561system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4265335000 # number of ReadReq miss cycles 562system.cpu.l2cache.ReadReq_miss_latency::total 4398589500 # number of ReadReq miss cycles 563system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 411500 # number of UpgradeReq miss cycles 564system.cpu.l2cache.UpgradeReq_miss_latency::total 411500 # number of UpgradeReq miss cycles 565system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3731222000 # number of ReadExReq miss cycles 566system.cpu.l2cache.ReadExReq_miss_latency::total 3731222000 # number of ReadExReq miss cycles 567system.cpu.l2cache.demand_miss_latency::cpu.inst 133254500 # number of demand (read+write) miss cycles 568system.cpu.l2cache.demand_miss_latency::cpu.data 7996557000 # number of demand (read+write) miss cycles 569system.cpu.l2cache.demand_miss_latency::total 8129811500 # number of demand (read+write) miss cycles 570system.cpu.l2cache.overall_miss_latency::cpu.inst 133254500 # number of overall miss cycles 571system.cpu.l2cache.overall_miss_latency::cpu.data 7996557000 # number of overall miss cycles 572system.cpu.l2cache.overall_miss_latency::total 8129811500 # number of overall miss cycles 573system.cpu.l2cache.ReadReq_accesses::cpu.inst 18168 # number of ReadReq accesses(hits+misses) 574system.cpu.l2cache.ReadReq_accesses::cpu.data 867210 # number of ReadReq accesses(hits+misses) 575system.cpu.l2cache.ReadReq_accesses::total 885378 # number of ReadReq accesses(hits+misses) 576system.cpu.l2cache.Writeback_accesses::writebacks 1073406 # number of Writeback accesses(hits+misses) 577system.cpu.l2cache.Writeback_accesses::total 1073406 # number of Writeback accesses(hits+misses) 578system.cpu.l2cache.UpgradeReq_accesses::cpu.data 251 # number of UpgradeReq accesses(hits+misses) 579system.cpu.l2cache.UpgradeReq_accesses::total 251 # number of UpgradeReq accesses(hits+misses) 580system.cpu.l2cache.ReadExReq_accesses::cpu.data 341531 # number of ReadExReq accesses(hits+misses) 581system.cpu.l2cache.ReadExReq_accesses::total 341531 # number of ReadExReq accesses(hits+misses) 582system.cpu.l2cache.demand_accesses::cpu.inst 18168 # number of demand (read+write) accesses 583system.cpu.l2cache.demand_accesses::cpu.data 1208741 # number of demand (read+write) accesses 584system.cpu.l2cache.demand_accesses::total 1226909 # number of demand (read+write) accesses 585system.cpu.l2cache.overall_accesses::cpu.inst 18168 # number of overall (read+write) accesses 586system.cpu.l2cache.overall_accesses::cpu.data 1208741 # number of overall (read+write) accesses 587system.cpu.l2cache.overall_accesses::total 1226909 # number of overall (read+write) accesses 588system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213948 # miss rate for ReadReq accesses 589system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143827 # miss rate for ReadReq accesses 590system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.191235 # miss rate for UpgradeReq accesses 591system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319057 # miss rate for ReadExReq accesses 592system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213948 # miss rate for demand accesses 593system.cpu.l2cache.demand_miss_rate::cpu.data 0.193338 # miss rate for demand accesses 594system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213948 # miss rate for overall accesses 595system.cpu.l2cache.overall_miss_rate::cpu.data 0.193338 # miss rate for overall accesses 596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34282.094160 # average ReadReq miss latency 597system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34197.092874 # average ReadReq miss latency 598system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8572.916667 # average UpgradeReq miss latency 599system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34241.447030 # average ReadExReq miss latency 600system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34282.094160 # average overall miss latency 601system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.774374 # average overall miss latency 602system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34282.094160 # average overall miss latency 603system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.774374 # average overall miss latency | 519system.cpu.l2cache.replacements 218501 # number of replacements 520system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use 521system.cpu.l2cache.total_refs 1557466 # Total number of references to valid blocks. 522system.cpu.l2cache.sampled_refs 238907 # Sample count of references to valid blocks. 523system.cpu.l2cache.avg_refs 6.519131 # Average number of references to valid blocks. 524system.cpu.l2cache.warmup_cycle 170551572000 # Cycle when the warmup percentage was hit. 525system.cpu.l2cache.occ_blocks::writebacks 13694.941090 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_blocks::cpu.inst 198.526640 # Average occupied blocks per requestor 527system.cpu.l2cache.occ_blocks::cpu.data 7036.927606 # Average occupied blocks per requestor 528system.cpu.l2cache.occ_percent::writebacks 0.417936 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.inst 0.006059 # Average percentage of cache occupancy 530system.cpu.l2cache.occ_percent::cpu.data 0.214750 # Average percentage of cache occupancy 531system.cpu.l2cache.occ_percent::total 0.638745 # Average percentage of cache occupancy 532system.cpu.l2cache.ReadReq_hits::cpu.inst 14165 # number of ReadReq hits 533system.cpu.l2cache.ReadReq_hits::cpu.data 742446 # number of ReadReq hits 534system.cpu.l2cache.ReadReq_hits::total 756611 # number of ReadReq hits 535system.cpu.l2cache.Writeback_hits::writebacks 1073323 # number of Writeback hits 536system.cpu.l2cache.Writeback_hits::total 1073323 # number of Writeback hits 537system.cpu.l2cache.UpgradeReq_hits::cpu.data 110 # number of UpgradeReq hits 538system.cpu.l2cache.UpgradeReq_hits::total 110 # number of UpgradeReq hits 539system.cpu.l2cache.ReadExReq_hits::cpu.data 232553 # number of ReadExReq hits 540system.cpu.l2cache.ReadExReq_hits::total 232553 # number of ReadExReq hits 541system.cpu.l2cache.demand_hits::cpu.inst 14165 # number of demand (read+write) hits 542system.cpu.l2cache.demand_hits::cpu.data 974999 # number of demand (read+write) hits 543system.cpu.l2cache.demand_hits::total 989164 # number of demand (read+write) hits 544system.cpu.l2cache.overall_hits::cpu.inst 14165 # number of overall hits 545system.cpu.l2cache.overall_hits::cpu.data 974999 # number of overall hits 546system.cpu.l2cache.overall_hits::total 989164 # number of overall hits 547system.cpu.l2cache.ReadReq_misses::cpu.inst 3852 # number of ReadReq misses 548system.cpu.l2cache.ReadReq_misses::cpu.data 124612 # number of ReadReq misses 549system.cpu.l2cache.ReadReq_misses::total 128464 # number of ReadReq misses 550system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses 551system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses 552system.cpu.l2cache.ReadExReq_misses::cpu.data 109285 # number of ReadExReq misses 553system.cpu.l2cache.ReadExReq_misses::total 109285 # number of ReadExReq misses 554system.cpu.l2cache.demand_misses::cpu.inst 3852 # number of demand (read+write) misses 555system.cpu.l2cache.demand_misses::cpu.data 233897 # number of demand (read+write) misses 556system.cpu.l2cache.demand_misses::total 237749 # number of demand (read+write) misses 557system.cpu.l2cache.overall_misses::cpu.inst 3852 # number of overall misses 558system.cpu.l2cache.overall_misses::cpu.data 233897 # number of overall misses 559system.cpu.l2cache.overall_misses::total 237749 # number of overall misses 560system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132071500 # number of ReadReq miss cycles 561system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4261496000 # number of ReadReq miss cycles 562system.cpu.l2cache.ReadReq_miss_latency::total 4393567500 # number of ReadReq miss cycles 563system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 205000 # number of UpgradeReq miss cycles 564system.cpu.l2cache.UpgradeReq_miss_latency::total 205000 # number of UpgradeReq miss cycles 565system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3742208000 # number of ReadExReq miss cycles 566system.cpu.l2cache.ReadExReq_miss_latency::total 3742208000 # number of ReadExReq miss cycles 567system.cpu.l2cache.demand_miss_latency::cpu.inst 132071500 # number of demand (read+write) miss cycles 568system.cpu.l2cache.demand_miss_latency::cpu.data 8003704000 # number of demand (read+write) miss cycles 569system.cpu.l2cache.demand_miss_latency::total 8135775500 # number of demand (read+write) miss cycles 570system.cpu.l2cache.overall_miss_latency::cpu.inst 132071500 # number of overall miss cycles 571system.cpu.l2cache.overall_miss_latency::cpu.data 8003704000 # number of overall miss cycles 572system.cpu.l2cache.overall_miss_latency::total 8135775500 # number of overall miss cycles 573system.cpu.l2cache.ReadReq_accesses::cpu.inst 18017 # number of ReadReq accesses(hits+misses) 574system.cpu.l2cache.ReadReq_accesses::cpu.data 867058 # number of ReadReq accesses(hits+misses) 575system.cpu.l2cache.ReadReq_accesses::total 885075 # number of ReadReq accesses(hits+misses) 576system.cpu.l2cache.Writeback_accesses::writebacks 1073323 # number of Writeback accesses(hits+misses) 577system.cpu.l2cache.Writeback_accesses::total 1073323 # number of Writeback accesses(hits+misses) 578system.cpu.l2cache.UpgradeReq_accesses::cpu.data 143 # number of UpgradeReq accesses(hits+misses) 579system.cpu.l2cache.UpgradeReq_accesses::total 143 # number of UpgradeReq accesses(hits+misses) 580system.cpu.l2cache.ReadExReq_accesses::cpu.data 341838 # number of ReadExReq accesses(hits+misses) 581system.cpu.l2cache.ReadExReq_accesses::total 341838 # number of ReadExReq accesses(hits+misses) 582system.cpu.l2cache.demand_accesses::cpu.inst 18017 # number of demand (read+write) accesses 583system.cpu.l2cache.demand_accesses::cpu.data 1208896 # number of demand (read+write) accesses 584system.cpu.l2cache.demand_accesses::total 1226913 # number of demand (read+write) accesses 585system.cpu.l2cache.overall_accesses::cpu.inst 18017 # number of overall (read+write) accesses 586system.cpu.l2cache.overall_accesses::cpu.data 1208896 # number of overall (read+write) accesses 587system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses 588system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses 589system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses 590system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses 591system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses 592system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses 593system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses 594system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses 595system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses 596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency 597system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency 598system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency 599system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency 600system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency 601system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency 602system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency 603system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency |
| 604system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 605system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 606system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 607system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 608system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 609system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 610system.cpu.l2cache.fast_writes 0 # number of fast writes performed 611system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 604system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 605system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 606system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 607system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 608system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 609system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 610system.cpu.l2cache.fast_writes 0 # number of fast writes performed 611system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 612system.cpu.l2cache.writebacks::writebacks 170975 # number of writebacks 613system.cpu.l2cache.writebacks::total 170975 # number of writebacks | 612system.cpu.l2cache.writebacks::writebacks 171061 # number of writebacks 613system.cpu.l2cache.writebacks::total 171061 # number of writebacks |
| 614system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits | 614system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits |
| 615system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 25 # number of ReadReq MSHR hits 616system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits | 615system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits 616system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits |
| 617system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits | 617system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits |
| 618system.cpu.l2cache.demand_mshr_hits::cpu.data 25 # number of demand (read+write) MSHR hits 619system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits | 618system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits 619system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits |
| 620system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits | 620system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits |
| 621system.cpu.l2cache.overall_mshr_hits::cpu.data 25 # number of overall MSHR hits 622system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits 623system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3882 # number of ReadReq MSHR misses 624system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 124703 # number of ReadReq MSHR misses 625system.cpu.l2cache.ReadReq_mshr_misses::total 128585 # number of ReadReq MSHR misses 626system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses 627system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses 628system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108968 # number of ReadExReq MSHR misses 629system.cpu.l2cache.ReadExReq_mshr_misses::total 108968 # number of ReadExReq MSHR misses 630system.cpu.l2cache.demand_mshr_misses::cpu.inst 3882 # number of demand (read+write) MSHR misses 631system.cpu.l2cache.demand_mshr_misses::cpu.data 233671 # number of demand (read+write) MSHR misses 632system.cpu.l2cache.demand_mshr_misses::total 237553 # number of demand (read+write) MSHR misses 633system.cpu.l2cache.overall_mshr_misses::cpu.inst 3882 # number of overall MSHR misses 634system.cpu.l2cache.overall_mshr_misses::cpu.data 233671 # number of overall MSHR misses 635system.cpu.l2cache.overall_mshr_misses::total 237553 # number of overall MSHR misses 636system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120642000 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3870272500 # number of ReadReq MSHR miss cycles 638system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3990914500 # number of ReadReq MSHR miss cycles 639system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1489500 # number of UpgradeReq MSHR miss cycles 640system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1489500 # number of UpgradeReq MSHR miss cycles 641system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3378939500 # number of ReadExReq MSHR miss cycles 642system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3378939500 # number of ReadExReq MSHR miss cycles 643system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120642000 # number of demand (read+write) MSHR miss cycles 644system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7249212000 # number of demand (read+write) MSHR miss cycles 645system.cpu.l2cache.demand_mshr_miss_latency::total 7369854000 # number of demand (read+write) MSHR miss cycles 646system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120642000 # number of overall MSHR miss cycles 647system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7249212000 # number of overall MSHR miss cycles 648system.cpu.l2cache.overall_mshr_miss_latency::total 7369854000 # number of overall MSHR miss cycles 649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213672 # mshr miss rate for ReadReq accesses 650system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143798 # mshr miss rate for ReadReq accesses 651system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.191235 # mshr miss rate for UpgradeReq accesses 652system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319057 # mshr miss rate for ReadExReq accesses 653system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213672 # mshr miss rate for demand accesses 654system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193318 # mshr miss rate for demand accesses 655system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213672 # mshr miss rate for overall accesses 656system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193318 # mshr miss rate for overall accesses 657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31077.279753 # average ReadReq mshr miss latency 658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.921349 # average ReadReq mshr miss latency 659system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.250000 # average UpgradeReq mshr miss latency 660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.548381 # average ReadExReq mshr miss latency 661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31077.279753 # average overall mshr miss latency 662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.156489 # average overall mshr miss latency 663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31077.279753 # average overall mshr miss latency 664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.156489 # average overall mshr miss latency | 621system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 622system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits 623system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3847 # number of ReadReq MSHR misses 624system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 124590 # number of ReadReq MSHR misses 625system.cpu.l2cache.ReadReq_mshr_misses::total 128437 # number of ReadReq MSHR misses 626system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses 627system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses 628system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 109285 # number of ReadExReq MSHR misses 629system.cpu.l2cache.ReadExReq_mshr_misses::total 109285 # number of ReadExReq MSHR misses 630system.cpu.l2cache.demand_mshr_misses::cpu.inst 3847 # number of demand (read+write) MSHR misses 631system.cpu.l2cache.demand_mshr_misses::cpu.data 233875 # number of demand (read+write) MSHR misses 632system.cpu.l2cache.demand_mshr_misses::total 237722 # number of demand (read+write) MSHR misses 633system.cpu.l2cache.overall_mshr_misses::cpu.inst 3847 # number of overall MSHR misses 634system.cpu.l2cache.overall_mshr_misses::cpu.data 233875 # number of overall MSHR misses 635system.cpu.l2cache.overall_mshr_misses::total 237722 # number of overall MSHR misses 636system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 119582500 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3866885000 # number of ReadReq MSHR miss cycles 638system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3986467500 # number of ReadReq MSHR miss cycles 639system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1024500 # number of UpgradeReq MSHR miss cycles 640system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1024500 # number of UpgradeReq MSHR miss cycles 641system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3388776000 # number of ReadExReq MSHR miss cycles 642system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3388776000 # number of ReadExReq MSHR miss cycles 643system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 119582500 # number of demand (read+write) MSHR miss cycles 644system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7255661000 # number of demand (read+write) MSHR miss cycles 645system.cpu.l2cache.demand_mshr_miss_latency::total 7375243500 # number of demand (read+write) MSHR miss cycles 646system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119582500 # number of overall MSHR miss cycles 647system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 # number of overall MSHR miss cycles 648system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles 649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses 650system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses 651system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses 652system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses 653system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses 654system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses 655system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses 656system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses 657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency 658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency 659system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency 660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency 661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency 662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency 663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency 664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency |
| 665system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 666 667---------- End Simulation Statistics ---------- | 665system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 666 667---------- End Simulation Statistics ---------- |