| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.233363 # Number of seconds simulated 4sim_ticks 233363457000 # Number of ticks simulated 5final_tick 233363457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.236034 # Number of seconds simulated 4sim_ticks 236034256000 # Number of ticks simulated 5final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 153279 # Simulator instruction rate (inst/s) 8host_op_rate 166055 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 70798116 # Simulator tick rate (ticks/s) 10host_mem_usage 302508 # Number of bytes of host memory used 11host_seconds 3296.18 # Real time elapsed on the host | 7host_inst_rate 147811 # Simulator instruction rate (inst/s) 8host_op_rate 160132 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 69053974 # Simulator tick rate (ticks/s) 10host_mem_usage 301356 # Number of bytes of host memory used 11host_seconds 3418.11 # Real time elapsed on the host |
| 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 641792 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10513600 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 16409344 # Number of bytes read from this memory 20system.physmem.bytes_read::total 27564736 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 641792 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 641792 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 18651328 # Number of bytes written to this memory 24system.physmem.bytes_written::total 18651328 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 10028 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 164275 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 256396 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 430699 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 291427 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 291427 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 2750182 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 45052469 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 70316682 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 118119333 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 2750182 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 2750182 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 79923945 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 79923945 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 79923945 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 2750182 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 45052469 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 70316682 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 198043278 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 430699 # Number of read requests accepted 45system.physmem.writeReqs 291427 # Number of write requests accepted 46system.physmem.readBursts 430699 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 291427 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 27407296 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 157440 # Total number of bytes read from write queue 50system.physmem.bytesWritten 18649728 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 27564736 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 18651328 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 2460 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 637184 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10497472 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 16389440 # Number of bytes read from this memory 20system.physmem.bytes_read::total 27524096 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 637184 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 637184 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 18641536 # Number of bytes written to this memory 24system.physmem.bytes_written::total 18641536 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 9956 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 164023 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 256085 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 430064 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 291274 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 291274 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 2699540 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 44474358 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 69436701 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 116610599 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 2699540 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 2699540 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 78978095 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 78978095 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 78978095 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 2699540 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 44474358 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 69436701 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 195588695 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 430064 # Number of read requests accepted 45system.physmem.writeReqs 291274 # Number of write requests accepted 46system.physmem.readBursts 430064 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 291274 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 27360896 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 163200 # Total number of bytes read from write queue 50system.physmem.bytesWritten 18638848 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 27524096 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 18641536 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 2550 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one |
| 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 27205 # Per bank write bursts 57system.physmem.perBankRdBursts::1 26463 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25602 # Per bank write bursts 59system.physmem.perBankRdBursts::3 32969 # Per bank write bursts 60system.physmem.perBankRdBursts::4 28037 # Per bank write bursts 61system.physmem.perBankRdBursts::5 29890 # Per bank write bursts 62system.physmem.perBankRdBursts::6 25340 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24398 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25649 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25581 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25884 # Per bank write bursts 67system.physmem.perBankRdBursts::11 26303 # Per bank write bursts 68system.physmem.perBankRdBursts::12 27555 # Per bank write bursts 69system.physmem.perBankRdBursts::13 26148 # Per bank write bursts 70system.physmem.perBankRdBursts::14 24908 # Per bank write bursts 71system.physmem.perBankRdBursts::15 26307 # Per bank write bursts 72system.physmem.perBankWrBursts::0 18644 # Per bank write bursts 73system.physmem.perBankWrBursts::1 18139 # Per bank write bursts 74system.physmem.perBankWrBursts::2 17950 # Per bank write bursts 75system.physmem.perBankWrBursts::3 17944 # Per bank write bursts 76system.physmem.perBankWrBursts::4 18581 # Per bank write bursts 77system.physmem.perBankWrBursts::5 18235 # Per bank write bursts 78system.physmem.perBankWrBursts::6 17841 # Per bank write bursts 79system.physmem.perBankWrBursts::7 17708 # Per bank write bursts 80system.physmem.perBankWrBursts::8 18005 # Per bank write bursts 81system.physmem.perBankWrBursts::9 17734 # Per bank write bursts 82system.physmem.perBankWrBursts::10 18244 # Per bank write bursts 83system.physmem.perBankWrBursts::11 18783 # Per bank write bursts 84system.physmem.perBankWrBursts::12 18680 # Per bank write bursts 85system.physmem.perBankWrBursts::13 18156 # Per bank write bursts 86system.physmem.perBankWrBursts::14 18369 # Per bank write bursts 87system.physmem.perBankWrBursts::15 18389 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 27217 # Per bank write bursts 57system.physmem.perBankRdBursts::1 26580 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25459 # Per bank write bursts 59system.physmem.perBankRdBursts::3 32933 # Per bank write bursts 60system.physmem.perBankRdBursts::4 28005 # Per bank write bursts 61system.physmem.perBankRdBursts::5 30095 # Per bank write bursts 62system.physmem.perBankRdBursts::6 25324 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24336 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25637 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25661 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25768 # Per bank write bursts 67system.physmem.perBankRdBursts::11 26242 # Per bank write bursts 68system.physmem.perBankRdBursts::12 27581 # Per bank write bursts 69system.physmem.perBankRdBursts::13 26014 # Per bank write bursts 70system.physmem.perBankRdBursts::14 24864 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25798 # Per bank write bursts 72system.physmem.perBankWrBursts::0 18651 # Per bank write bursts 73system.physmem.perBankWrBursts::1 18268 # Per bank write bursts 74system.physmem.perBankWrBursts::2 17926 # Per bank write bursts 75system.physmem.perBankWrBursts::3 17983 # Per bank write bursts 76system.physmem.perBankWrBursts::4 18558 # Per bank write bursts 77system.physmem.perBankWrBursts::5 18375 # Per bank write bursts 78system.physmem.perBankWrBursts::6 17786 # Per bank write bursts 79system.physmem.perBankWrBursts::7 17681 # Per bank write bursts 80system.physmem.perBankWrBursts::8 18027 # Per bank write bursts 81system.physmem.perBankWrBursts::9 17737 # Per bank write bursts 82system.physmem.perBankWrBursts::10 18114 # Per bank write bursts 83system.physmem.perBankWrBursts::11 18781 # Per bank write bursts 84system.physmem.perBankWrBursts::12 18716 # Per bank write bursts 85system.physmem.perBankWrBursts::13 18163 # Per bank write bursts 86system.physmem.perBankWrBursts::14 18303 # Per bank write bursts 87system.physmem.perBankWrBursts::15 18163 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 233363404500 # Total gap between requests | 90system.physmem.totGap 236034203500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 430699 # Read request sizes (log2) | 97system.physmem.readPktSize::6 430064 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 291427 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 330391 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 50226 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 12856 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 8880 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 7122 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 6027 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 5118 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 4235 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 3274 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 16 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 9 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 291274 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 318869 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 60281 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 13267 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 8983 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 7229 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 6032 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 5148 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 4295 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 3299 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 63 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 23 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 7280 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 7756 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 12492 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 15016 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 16255 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 16901 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 17254 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 17654 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 17875 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 18074 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 18193 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 18541 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 18646 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 18700 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 18837 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 17505 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 17142 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 17030 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 51 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 6756 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 7242 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 12113 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 14851 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 16256 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 16916 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 17294 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 17615 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 17892 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 18128 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 18323 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 18440 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 18551 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 18644 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 18821 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 18548 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 17432 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 17189 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 149 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see |
| 172system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see | 172system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 328347 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 140.266048 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 98.833830 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 178.808988 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 208753 63.58% 63.58% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 80037 24.38% 87.95% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 14980 4.56% 92.51% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 7256 2.21% 94.72% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 4857 1.48% 96.20% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2521 0.77% 96.97% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1858 0.57% 97.54% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1524 0.46% 98.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 6561 2.00% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 328347 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 16970 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 25.230642 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 145.328941 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-1023 16968 99.99% 99.99% # Reads before turning the bus around for writes | 201system.physmem.bytesPerActivate::samples 329061 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 139.787432 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 98.478985 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 178.644390 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 210353 63.93% 63.93% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 79320 24.10% 88.03% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 14852 4.51% 92.54% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 7229 2.20% 94.74% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 4899 1.49% 96.23% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2483 0.75% 96.98% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1823 0.55% 97.54% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1564 0.48% 98.01% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 6538 1.99% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 329061 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 17032 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 25.095820 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 145.258821 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-1023 17030 99.99% 99.99% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes | 219system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 16970 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 16970 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 17.171597 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 17.099419 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 1.840930 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-17 9436 55.60% 55.60% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18-19 6694 39.45% 95.05% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20-21 588 3.46% 98.52% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22-23 150 0.88% 99.40% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::24-25 55 0.32% 99.72% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::26-27 20 0.12% 99.84% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-29 4 0.02% 99.86% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::30-31 8 0.05% 99.91% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::32-33 2 0.01% 99.92% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::34-35 4 0.02% 99.95% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::44-45 1 0.01% 99.96% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::48-49 1 0.01% 99.97% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::62-63 1 0.01% 99.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::72-73 1 0.01% 99.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::76-77 1 0.01% 99.99% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::94-95 1 0.01% 100.00% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::total 16970 # Writes before turning the bus around for reads 246system.physmem.totQLat 8687632010 # Total ticks spent queuing 247system.physmem.totMemAccLat 16717113260 # Total ticks spent from burst creation until serviced by the DRAM 248system.physmem.totBusLat 2141195000 # Total ticks spent in databus transfers 249system.physmem.avgQLat 20286.88 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 17032 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 17032 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 17.099108 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 17.028520 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 1.818567 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-17 10039 58.94% 58.94% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18-19 6203 36.42% 95.36% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20-21 545 3.20% 98.56% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22-23 139 0.82% 99.38% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::24-25 59 0.35% 99.72% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::26-27 18 0.11% 99.83% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-29 9 0.05% 99.88% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::30-31 2 0.01% 99.89% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::32-33 2 0.01% 99.91% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::34-35 2 0.01% 99.92% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::36-37 3 0.02% 99.94% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::38-39 5 0.03% 99.96% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-41 2 0.01% 99.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::60-61 2 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::104-105 1 0.01% 100.00% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::total 17032 # Writes before turning the bus around for reads 243system.physmem.totQLat 14213030846 # Total ticks spent queuing 244system.physmem.totMemAccLat 22228918346 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 2137570000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 33245.77 # Average queueing delay per DRAM burst |
| 250system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 251system.physmem.avgMemAccLat 39036.88 # Average memory access latency per DRAM burst 252system.physmem.avgRdBW 117.44 # Average DRAM read bandwidth in MiByte/s 253system.physmem.avgWrBW 79.92 # Average achieved write bandwidth in MiByte/s 254system.physmem.avgRdBWSys 118.12 # Average system read bandwidth in MiByte/s 255system.physmem.avgWrBWSys 79.92 # Average system write bandwidth in MiByte/s | 248system.physmem.avgMemAccLat 51995.77 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 115.92 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 78.97 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 116.61 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 78.98 # Average system write bandwidth in MiByte/s |
| 256system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 257system.physmem.busUtil 1.54 # Data bus utilization in percentage 258system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads | 254system.physmem.busUtil 1.52 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads |
| 259system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes 260system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing | 256system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes 257system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing |
| 261system.physmem.avgWrQLen 21.52 # Average write queue length when enqueuing 262system.physmem.readRowHits 308039 # Number of row buffer hits during reads 263system.physmem.writeRowHits 83248 # Number of row buffer hits during writes 264system.physmem.readRowHitRate 71.93 # Row buffer hit rate for reads 265system.physmem.writeRowHitRate 28.57 # Row buffer hit rate for writes 266system.physmem.avgGap 323161.62 # Average gap between requests 267system.physmem.pageHitRate 54.37 # Row buffer hit rate, read and write combined 268system.physmem_0.actEnergy 1261242360 # Energy for activate commands per rank (pJ) 269system.physmem_0.preEnergy 688177875 # Energy for precharge commands per rank (pJ) 270system.physmem_0.readEnergy 1715142000 # Energy for read commands per rank (pJ) 271system.physmem_0.writeEnergy 939872160 # Energy for write commands per rank (pJ) 272system.physmem_0.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) 273system.physmem_0.actBackEnergy 86511761685 # Energy for active background per rank (pJ) 274system.physmem_0.preBackEnergy 64129665000 # Energy for precharge background per rank (pJ) 275system.physmem_0.totalEnergy 170487912840 # Total energy per rank (pJ) 276system.physmem_0.averagePower 730.572857 # Core power per rank (mW) 277system.physmem_0.memoryStateTime::IDLE 106127593352 # Time in different power states 278system.physmem_0.memoryStateTime::REF 7792460000 # Time in different power states 279system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 280system.physmem_0.memoryStateTime::ACT 119441919148 # Time in different power states 281system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 282system.physmem_1.actEnergy 1221045840 # Energy for activate commands per rank (pJ) 283system.physmem_1.preEnergy 666245250 # Energy for precharge commands per rank (pJ) 284system.physmem_1.readEnergy 1624857000 # Energy for read commands per rank (pJ) 285system.physmem_1.writeEnergy 948412800 # Energy for write commands per rank (pJ) 286system.physmem_1.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) 287system.physmem_1.actBackEnergy 81485025165 # Energy for active background per rank (pJ) 288system.physmem_1.preBackEnergy 68539083000 # Energy for precharge background per rank (pJ) 289system.physmem_1.totalEnergy 169726720815 # Total energy per rank (pJ) 290system.physmem_1.averagePower 727.311005 # Core power per rank (mW) 291system.physmem_1.memoryStateTime::IDLE 113492657633 # Time in different power states 292system.physmem_1.memoryStateTime::REF 7792460000 # Time in different power states 293system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 294system.physmem_1.memoryStateTime::ACT 112077139867 # Time in different power states 295system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 296system.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 297system.cpu.branchPred.lookups 174594135 # Number of BP lookups 298system.cpu.branchPred.condPredicted 131061438 # Number of conditional branches predicted 299system.cpu.branchPred.condIncorrect 7233022 # Number of conditional branches incorrect 300system.cpu.branchPred.BTBLookups 90315091 # Number of BTB lookups 301system.cpu.branchPred.BTBHits 79002409 # Number of BTB hits | 258system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing 259system.physmem.readRowHits 307655 # Number of row buffer hits during reads 260system.physmem.writeRowHits 82023 # Number of row buffer hits during writes 261system.physmem.readRowHitRate 71.96 # Row buffer hit rate for reads 262system.physmem.writeRowHitRate 28.16 # Row buffer hit rate for writes 263system.physmem.avgGap 327217.20 # Average gap between requests 264system.physmem.pageHitRate 54.21 # Row buffer hit rate, read and write combined 265system.physmem_0.actEnergy 1196014260 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 635677680 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 1570435860 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 758090160 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 15730481520.000004 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 13398551100 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 618704160 # Energy for precharge background per rank (pJ) 272system.physmem_0.actPowerDownEnergy 46181225010 # Energy for active power-down per rank (pJ) 273system.physmem_0.prePowerDownEnergy 17503538880 # Energy for precharge power-down per rank (pJ) 274system.physmem_0.selfRefreshEnergy 15597346500 # Energy for self refresh per rank (pJ) 275system.physmem_0.totalEnergy 113194744170 # Total energy per rank (pJ) 276system.physmem_0.averagePower 479.569128 # Core power per rank (mW) 277system.physmem_0.totalIdleTime 205028158054 # Total Idle time Per DRAM Rank 278system.physmem_0.memoryStateTime::IDLE 920292705 # Time in different power states 279system.physmem_0.memoryStateTime::REF 6672444000 # Time in different power states 280system.physmem_0.memoryStateTime::SREF 58173065750 # Time in different power states 281system.physmem_0.memoryStateTime::PRE_PDN 45581110454 # Time in different power states 282system.physmem_0.memoryStateTime::ACT 23413245991 # Time in different power states 283system.physmem_0.memoryStateTime::ACT_PDN 101274097100 # Time in different power states 284system.physmem_1.actEnergy 1153531260 # Energy for activate commands per rank (pJ) 285system.physmem_1.preEnergy 613108815 # Energy for precharge commands per rank (pJ) 286system.physmem_1.readEnergy 1482014100 # Energy for read commands per rank (pJ) 287system.physmem_1.writeEnergy 762140880 # Energy for write commands per rank (pJ) 288system.physmem_1.refreshEnergy 15061753200.000004 # Energy for refresh commands per rank (pJ) 289system.physmem_1.actBackEnergy 13366111830 # Energy for active background per rank (pJ) 290system.physmem_1.preBackEnergy 607264320 # Energy for precharge background per rank (pJ) 291system.physmem_1.actPowerDownEnergy 42525061470 # Energy for active power-down per rank (pJ) 292system.physmem_1.prePowerDownEnergy 17168834400 # Energy for precharge power-down per rank (pJ) 293system.physmem_1.selfRefreshEnergy 17794675410 # Energy for self refresh per rank (pJ) 294system.physmem_1.totalEnergy 110539948695 # Total energy per rank (pJ) 295system.physmem_1.averagePower 468.321620 # Core power per rank (mW) 296system.physmem_1.totalIdleTime 205130134268 # Total Idle time Per DRAM Rank 297system.physmem_1.memoryStateTime::IDLE 923619714 # Time in different power states 298system.physmem_1.memoryStateTime::REF 6390116000 # Time in different power states 299system.physmem_1.memoryStateTime::SREF 67161872750 # Time in different power states 300system.physmem_1.memoryStateTime::PRE_PDN 44710479181 # Time in different power states 301system.physmem_1.memoryStateTime::ACT 23590386018 # Time in different power states 302system.physmem_1.memoryStateTime::ACT_PDN 93257782337 # Time in different power states 303system.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 304system.cpu.branchPred.lookups 174591760 # Number of BP lookups 305system.cpu.branchPred.condPredicted 131058406 # Number of conditional branches predicted 306system.cpu.branchPred.condIncorrect 7233420 # Number of conditional branches incorrect 307system.cpu.branchPred.BTBLookups 90376052 # Number of BTB lookups 308system.cpu.branchPred.BTBHits 79001018 # Number of BTB hits |
| 302system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 309system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 303system.cpu.branchPred.BTBHitPct 87.474206 # BTB Hit Percentage 304system.cpu.branchPred.usedRAS 12105110 # Number of times the RAS was used to get a target. 305system.cpu.branchPred.RASInCorrect 104499 # Number of incorrect RAS predictions. 306system.cpu.branchPred.indirectLookups 4687937 # Number of indirect predictor lookups. 307system.cpu.branchPred.indirectHits 4674274 # Number of indirect target hits. 308system.cpu.branchPred.indirectMisses 13663 # Number of indirect misses. 309system.cpu.branchPredindirectMispredicted 53871 # Number of mispredicted indirect branches. | 310system.cpu.branchPred.BTBHitPct 87.413664 # BTB Hit Percentage 311system.cpu.branchPred.usedRAS 12105632 # Number of times the RAS was used to get a target. 312system.cpu.branchPred.RASInCorrect 104483 # Number of incorrect RAS predictions. 313system.cpu.branchPred.indirectLookups 4688252 # Number of indirect predictor lookups. 314system.cpu.branchPred.indirectHits 4674256 # Number of indirect target hits. 315system.cpu.branchPred.indirectMisses 13996 # Number of indirect misses. 316system.cpu.branchPredindirectMispredicted 53921 # Number of mispredicted indirect branches. |
| 310system.cpu_clk_domain.clock 500 # Clock period in ticks | 317system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 311system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states | 318system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states |
| 312system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 333system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 334system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 336system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 337system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 338system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 339system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 340system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 319system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 340system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 341system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 342system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 343system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 344system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 345system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 346system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 347system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 341system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states | 348system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states |
| 342system.cpu.dtb.walker.walks 0 # Table walker walks requested 343system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 363system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 364system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 365system.cpu.dtb.read_accesses 0 # DTB read accesses 366system.cpu.dtb.write_accesses 0 # DTB write accesses 367system.cpu.dtb.inst_accesses 0 # ITB inst accesses 368system.cpu.dtb.hits 0 # DTB hits 369system.cpu.dtb.misses 0 # DTB misses 370system.cpu.dtb.accesses 0 # DTB accesses | 349system.cpu.dtb.walker.walks 0 # Table walker walks requested 350system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 353system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 356system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 370system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 371system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 372system.cpu.dtb.read_accesses 0 # DTB read accesses 373system.cpu.dtb.write_accesses 0 # DTB write accesses 374system.cpu.dtb.inst_accesses 0 # ITB inst accesses 375system.cpu.dtb.hits 0 # DTB hits 376system.cpu.dtb.misses 0 # DTB misses 377system.cpu.dtb.accesses 0 # DTB accesses |
| 371system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states | 378system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states |
| 372system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 393system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 394system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 395system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 396system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 397system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 398system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 399system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 400system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 379system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 383system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 384system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 386system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 400system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 401system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 402system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 403system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 404system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 405system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 406system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 407system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 401system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states | 408system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states |
| 402system.cpu.itb.walker.walks 0 # Table walker walks requested 403system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 424system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 425system.cpu.itb.read_accesses 0 # DTB read accesses 426system.cpu.itb.write_accesses 0 # DTB write accesses 427system.cpu.itb.inst_accesses 0 # ITB inst accesses 428system.cpu.itb.hits 0 # DTB hits 429system.cpu.itb.misses 0 # DTB misses 430system.cpu.itb.accesses 0 # DTB accesses 431system.cpu.workload.num_syscalls 548 # Number of system calls | 409system.cpu.itb.walker.walks 0 # Table walker walks requested 410system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 411system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 412system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 413system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 414system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 416system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 431system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 432system.cpu.itb.read_accesses 0 # DTB read accesses 433system.cpu.itb.write_accesses 0 # DTB write accesses 434system.cpu.itb.inst_accesses 0 # ITB inst accesses 435system.cpu.itb.hits 0 # DTB hits 436system.cpu.itb.misses 0 # DTB misses 437system.cpu.itb.accesses 0 # DTB accesses 438system.cpu.workload.num_syscalls 548 # Number of system calls |
| 432system.cpu.pwrStateResidencyTicks::ON 233363457000 # Cumulative time (in ticks) in various power states 433system.cpu.numCycles 466726915 # number of cpu cycles simulated | 439system.cpu.pwrStateResidencyTicks::ON 236034256000 # Cumulative time (in ticks) in various power states 440system.cpu.numCycles 472068513 # number of cpu cycles simulated |
| 434system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 435system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 441system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 442system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 436system.cpu.fetch.icacheStallCycles 7649319 # Number of cycles fetch is stalled on an Icache miss 437system.cpu.fetch.Insts 727510991 # Number of instructions fetch has processed 438system.cpu.fetch.Branches 174594135 # Number of branches that fetch encountered 439system.cpu.fetch.predictedBranches 95781793 # Number of branches that fetch has predicted taken 440system.cpu.fetch.Cycles 451018276 # Number of cycles fetch has run and was not squashing or blocked 441system.cpu.fetch.SquashCycles 14520177 # Number of cycles fetch has spent squashing 442system.cpu.fetch.MiscStallCycles 5415 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 443system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps 444system.cpu.fetch.IcacheWaitRetryStallCycles 13360 # Number of stall cycles due to full MSHR 445system.cpu.fetch.CacheLines 235275678 # Number of cache lines fetched 446system.cpu.fetch.IcacheSquashes 36827 # Number of outstanding Icache misses that were squashed 447system.cpu.fetch.rateDist::samples 465946604 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::mean 1.690437 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::stdev 1.183518 # Number of instructions fetched each cycle (Total) | 443system.cpu.fetch.icacheStallCycles 7651832 # Number of cycles fetch is stalled on an Icache miss 444system.cpu.fetch.Insts 727514898 # Number of instructions fetch has processed 445system.cpu.fetch.Branches 174591760 # Number of branches that fetch encountered 446system.cpu.fetch.predictedBranches 95780906 # Number of branches that fetch has predicted taken 447system.cpu.fetch.Cycles 456008633 # Number of cycles fetch has run and was not squashing or blocked 448system.cpu.fetch.SquashCycles 14520873 # Number of cycles fetch has spent squashing 449system.cpu.fetch.MiscStallCycles 8018 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 450system.cpu.fetch.PendingTrapStallCycles 72 # Number of stall cycles due to pending traps 451system.cpu.fetch.IcacheWaitRetryStallCycles 15159 # Number of stall cycles due to full MSHR 452system.cpu.fetch.CacheLines 235276766 # Number of cache lines fetched 453system.cpu.fetch.IcacheSquashes 36821 # Number of outstanding Icache misses that were squashed 454system.cpu.fetch.rateDist::samples 470944150 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::mean 1.672513 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::stdev 1.189889 # Number of instructions fetched each cycle (Total) |
| 450system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 457system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 451system.cpu.fetch.rateDist::0 96241342 20.66% 20.66% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::1 132050994 28.34% 49.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::2 57360477 12.31% 61.31% # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::3 180293791 38.69% 100.00% # Number of instructions fetched each cycle (Total) | 458system.cpu.fetch.rateDist::0 101233581 21.50% 21.50% # Number of instructions fetched each cycle (Total) 459system.cpu.fetch.rateDist::1 132057346 28.04% 49.54% # Number of instructions fetched each cycle (Total) 460system.cpu.fetch.rateDist::2 57356975 12.18% 61.72% # Number of instructions fetched each cycle (Total) 461system.cpu.fetch.rateDist::3 180296248 38.28% 100.00% # Number of instructions fetched each cycle (Total) |
| 455system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 462system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 463system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 464system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 458system.cpu.fetch.rateDist::total 465946604 # Number of instructions fetched each cycle (Total) 459system.cpu.fetch.branchRate 0.374082 # Number of branch fetches per cycle 460system.cpu.fetch.rate 1.558751 # Number of inst fetches per cycle 461system.cpu.decode.IdleCycles 32536552 # Number of cycles decode is idle 462system.cpu.decode.BlockedCycles 120918293 # Number of cycles decode is blocked 463system.cpu.decode.RunCycles 282902203 # Number of cycles decode is running 464system.cpu.decode.UnblockCycles 22817634 # Number of cycles decode is unblocking 465system.cpu.decode.SquashCycles 6771922 # Number of cycles decode is squashing 466system.cpu.decode.BranchResolved 23855471 # Number of times decode resolved a branch 467system.cpu.decode.BranchMispred 495849 # Number of times decode detected a branch misprediction 468system.cpu.decode.DecodedInsts 710960604 # Number of instructions handled by decode 469system.cpu.decode.SquashedInsts 29091371 # Number of squashed instructions handled by decode 470system.cpu.rename.SquashCycles 6771922 # Number of cycles rename is squashing 471system.cpu.rename.IdleCycles 63349282 # Number of cycles rename is idle 472system.cpu.rename.BlockCycles 56784032 # Number of cycles rename is blocking 473system.cpu.rename.serializeStallCycles 40401553 # count of cycles rename stalled for serializing inst 474system.cpu.rename.RunCycles 273510163 # Number of cycles rename is running 475system.cpu.rename.UnblockCycles 25129652 # Number of cycles rename is unblocking 476system.cpu.rename.RenamedInsts 682692967 # Number of instructions processed by rename 477system.cpu.rename.SquashedInsts 12844145 # Number of squashed instructions processed by rename 478system.cpu.rename.ROBFullEvents 9945202 # Number of times rename has blocked due to ROB full 479system.cpu.rename.IQFullEvents 2511648 # Number of times rename has blocked due to IQ full 480system.cpu.rename.LQFullEvents 1805093 # Number of times rename has blocked due to LQ full 481system.cpu.rename.SQFullEvents 1905777 # Number of times rename has blocked due to SQ full 482system.cpu.rename.RenamedOperands 827472920 # Number of destination operands rename has renamed 483system.cpu.rename.RenameLookups 3000392013 # Number of register rename lookups that rename has made 484system.cpu.rename.int_rename_lookups 718609980 # Number of integer rename lookups 485system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups | 465system.cpu.fetch.rateDist::total 470944150 # Number of instructions fetched each cycle (Total) 466system.cpu.fetch.branchRate 0.369844 # Number of branch fetches per cycle 467system.cpu.fetch.rate 1.541121 # Number of inst fetches per cycle 468system.cpu.decode.IdleCycles 32549558 # Number of cycles decode is idle 469system.cpu.decode.BlockedCycles 125926098 # Number of cycles decode is blocked 470system.cpu.decode.RunCycles 282874913 # Number of cycles decode is running 471system.cpu.decode.UnblockCycles 22821432 # Number of cycles decode is unblocking 472system.cpu.decode.SquashCycles 6772149 # Number of cycles decode is squashing 473system.cpu.decode.BranchResolved 23855969 # Number of times decode resolved a branch 474system.cpu.decode.BranchMispred 495947 # Number of times decode detected a branch misprediction 475system.cpu.decode.DecodedInsts 710956468 # Number of instructions handled by decode 476system.cpu.decode.SquashedInsts 29088219 # Number of squashed instructions handled by decode 477system.cpu.rename.SquashCycles 6772149 # Number of cycles rename is squashing 478system.cpu.rename.IdleCycles 63367796 # Number of cycles rename is idle 479system.cpu.rename.BlockCycles 61282237 # Number of cycles rename is blocking 480system.cpu.rename.serializeStallCycles 40473434 # count of cycles rename stalled for serializing inst 481system.cpu.rename.RunCycles 273481495 # Number of cycles rename is running 482system.cpu.rename.UnblockCycles 25567039 # Number of cycles rename is unblocking 483system.cpu.rename.RenamedInsts 682687004 # Number of instructions processed by rename 484system.cpu.rename.SquashedInsts 12847672 # Number of squashed instructions processed by rename 485system.cpu.rename.ROBFullEvents 10037372 # Number of times rename has blocked due to ROB full 486system.cpu.rename.IQFullEvents 2522908 # Number of times rename has blocked due to IQ full 487system.cpu.rename.LQFullEvents 1816731 # Number of times rename has blocked due to LQ full 488system.cpu.rename.SQFullEvents 2323927 # Number of times rename has blocked due to SQ full 489system.cpu.rename.RenamedOperands 827475029 # Number of destination operands rename has renamed 490system.cpu.rename.RenameLookups 3000364097 # Number of register rename lookups that rename has made 491system.cpu.rename.int_rename_lookups 718606364 # Number of integer rename lookups 492system.cpu.rename.fp_rename_lookups 112 # Number of floating rename lookups |
| 486system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed | 493system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed |
| 487system.cpu.rename.UndoneMaps 173377246 # Number of HB maps that are undone due to squashing 488system.cpu.rename.serializingInsts 1545812 # count of serializing insts renamed 489system.cpu.rename.tempSerializingInsts 1536134 # count of temporary serializing insts renamed 490system.cpu.rename.skidInsts 43839802 # count of insts added to the skid buffer 491system.cpu.memDep0.insertedLoads 142358029 # Number of loads inserted to the mem dependence unit. 492system.cpu.memDep0.insertedStores 67522859 # Number of stores inserted to the mem dependence unit. 493system.cpu.memDep0.conflictingLoads 12902461 # Number of conflicting loads. 494system.cpu.memDep0.conflictingStores 11335768 # Number of conflicting stores. 495system.cpu.iq.iqInstsAdded 664750936 # Number of instructions added to the IQ (excludes non-spec) 496system.cpu.iq.iqNonSpecInstsAdded 2979334 # Number of non-speculative instructions added to the IQ 497system.cpu.iq.iqInstsIssued 608926553 # Number of instructions issued 498system.cpu.iq.iqSquashedInstsIssued 5748894 # Number of squashed instructions issued 499system.cpu.iq.iqSquashedInstsExamined 120382115 # Number of squashed instructions iterated over during squash; mainly for profiling 500system.cpu.iq.iqSquashedOperandsExamined 306467952 # Number of squashed operands that are examined and possibly removed from graph 501system.cpu.iq.iqSquashedNonSpecRemoved 1702 # Number of squashed non-spec instructions that were removed 502system.cpu.iq.issued_per_cycle::samples 465946604 # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::mean 1.306859 # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::stdev 1.102130 # Number of insts issued each cycle | 494system.cpu.rename.UndoneMaps 173379355 # Number of HB maps that are undone due to squashing 495system.cpu.rename.serializingInsts 1545861 # count of serializing insts renamed 496system.cpu.rename.tempSerializingInsts 1536327 # count of temporary serializing insts renamed 497system.cpu.rename.skidInsts 43857094 # count of insts added to the skid buffer 498system.cpu.memDep0.insertedLoads 142358041 # Number of loads inserted to the mem dependence unit. 499system.cpu.memDep0.insertedStores 67520451 # Number of stores inserted to the mem dependence unit. 500system.cpu.memDep0.conflictingLoads 12908238 # Number of conflicting loads. 501system.cpu.memDep0.conflictingStores 11335045 # Number of conflicting stores. 502system.cpu.iq.iqInstsAdded 664745436 # Number of instructions added to the IQ (excludes non-spec) 503system.cpu.iq.iqNonSpecInstsAdded 2979378 # Number of non-speculative instructions added to the IQ 504system.cpu.iq.iqInstsIssued 608905066 # Number of instructions issued 505system.cpu.iq.iqSquashedInstsIssued 5749480 # Number of squashed instructions issued 506system.cpu.iq.iqSquashedInstsExamined 120376659 # Number of squashed instructions iterated over during squash; mainly for profiling 507system.cpu.iq.iqSquashedOperandsExamined 306522000 # Number of squashed operands that are examined and possibly removed from graph 508system.cpu.iq.iqSquashedNonSpecRemoved 1746 # Number of squashed non-spec instructions that were removed 509system.cpu.iq.issued_per_cycle::samples 470944150 # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::mean 1.292945 # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::stdev 1.104492 # Number of insts issued each cycle |
| 505system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 512system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 506system.cpu.iq.issued_per_cycle::0 149520607 32.09% 32.09% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::1 100880237 21.65% 53.74% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::2 145552540 31.24% 84.98% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::3 63032249 13.53% 98.51% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::4 6960366 1.49% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::5 605 0.00% 100.00% # Number of insts issued each cycle | 513system.cpu.iq.issued_per_cycle::0 154541552 32.82% 32.82% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::1 100868277 21.42% 54.23% # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::2 145535828 30.90% 85.14% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::3 63029448 13.38% 98.52% # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::4 6968436 1.48% 100.00% # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::5 609 0.00% 100.00% # Number of insts issued each cycle |
| 512system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 519system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 522system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 523system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 518system.cpu.iq.issued_per_cycle::total 465946604 # Number of insts issued each cycle | 525system.cpu.iq.issued_per_cycle::total 470944150 # Number of insts issued each cycle |
| 519system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 526system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 520system.cpu.iq.fu_full::IntAlu 71896734 53.12% 53.12% # attempts to use FU when none available 521system.cpu.iq.fu_full::IntMult 30 0.00% 53.12% # attempts to use FU when none available 522system.cpu.iq.fu_full::IntDiv 0 0.00% 53.12% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.12% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.12% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.12% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatMult 0 0.00% 53.12% # attempts to use FU when none available 527system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.12% # attempts to use FU when none available 528system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.12% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.12% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.12% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.12% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.12% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.12% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.12% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdMult 0 0.00% 53.12% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.12% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdShift 0 0.00% 53.12% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.12% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.12% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.12% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.12% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.12% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.12% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.12% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.12% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.12% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.12% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.12% # attempts to use FU when none available 549system.cpu.iq.fu_full::MemRead 44291867 32.73% 85.85% # attempts to use FU when none available 550system.cpu.iq.fu_full::MemWrite 19147796 14.15% 100.00% # attempts to use FU when none available | 527system.cpu.iq.fu_full::IntAlu 71902487 53.13% 53.13% # attempts to use FU when none available 528system.cpu.iq.fu_full::IntMult 30 0.00% 53.13% # attempts to use FU when none available 529system.cpu.iq.fu_full::IntDiv 0 0.00% 53.13% # attempts to use FU when none available 530system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # attempts to use FU when none available 531system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available 532system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available 533system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available 534system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available 535system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.13% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.13% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.13% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.13% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdMult 0 0.00% 53.13% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.13% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdShift 0 0.00% 53.13% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.13% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.13% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.13% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.13% # attempts to use FU when none available 549system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.13% # attempts to use FU when none available 550system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.13% # attempts to use FU when none available 551system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.13% # attempts to use FU when none available 552system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # attempts to use FU when none available 553system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available 554system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available 555system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available 556system.cpu.iq.fu_full::MemRead 44305814 32.74% 85.86% # attempts to use FU when none available 557system.cpu.iq.fu_full::MemWrite 19132145 14.14% 100.00% # attempts to use FU when none available |
| 551system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 552system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 553system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 558system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 559system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 560system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 554system.cpu.iq.FU_type_0::IntAlu 412590919 67.76% 67.76% # Type of FU issued 555system.cpu.iq.FU_type_0::IntMult 352109 0.06% 67.81% # Type of FU issued 556system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued 561system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued 562system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued 582system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued 583system.cpu.iq.FU_type_0::MemRead 133574983 21.94% 89.75% # Type of FU issued 584system.cpu.iq.FU_type_0::MemWrite 62408539 10.25% 100.00% # Type of FU issued | 561system.cpu.iq.FU_type_0::IntAlu 412584657 67.76% 67.76% # Type of FU issued 562system.cpu.iq.FU_type_0::IntMult 352207 0.06% 67.82% # Type of FU issued 563system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued 564system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued 565system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued 566system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued 567system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued 568system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued 569system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued 582system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued 583system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued 585system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued 586system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued 587system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued 588system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued 589system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued 590system.cpu.iq.FU_type_0::MemRead 133573210 21.94% 89.75% # Type of FU issued 591system.cpu.iq.FU_type_0::MemWrite 62394989 10.25% 100.00% # Type of FU issued |
| 585system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 586system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 592system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 593system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 587system.cpu.iq.FU_type_0::total 608926553 # Type of FU issued 588system.cpu.iq.rate 1.304674 # Inst issue rate 589system.cpu.iq.fu_busy_cnt 135336427 # FU busy when requested 590system.cpu.iq.fu_busy_rate 0.222254 # FU busy rate (busy events/executed inst) 591system.cpu.iq.int_inst_queue_reads 1824884935 # Number of integer instruction queue reads 592system.cpu.iq.int_inst_queue_writes 788141663 # Number of integer instruction queue writes 593system.cpu.iq.int_inst_queue_wakeup_accesses 594200588 # Number of integer instruction queue wakeup accesses 594system.cpu.iq.fp_inst_queue_reads 96 # Number of floating instruction queue reads 595system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes | 594system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued 595system.cpu.iq.rate 1.289866 # Inst issue rate 596system.cpu.iq.fu_busy_cnt 135340476 # FU busy when requested 597system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst) 598system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads 599system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes 600system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses 601system.cpu.iq.fp_inst_queue_reads 106 # Number of floating instruction queue reads 602system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes |
| 596system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 603system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 597system.cpu.iq.int_alu_accesses 744262920 # Number of integer alu accesses 598system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses 599system.cpu.iew.lsq.thread0.forwLoads 7284479 # Number of loads that had data forwarded from stores | 604system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses 605system.cpu.iq.fp_alu_accesses 66 # Number of floating point alu accesses 606system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores |
| 600system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 607system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 601system.cpu.iew.lsq.thread0.squashedLoads 26474746 # Number of loads squashed 602system.cpu.iew.lsq.thread0.ignoredResponses 24624 # Number of memory responses ignored because the instruction is squashed 603system.cpu.iew.lsq.thread0.memOrderViolation 29798 # Number of memory ordering violations 604system.cpu.iew.lsq.thread0.squashedStores 10662639 # Number of stores squashed | 608system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed 609system.cpu.iew.lsq.thread0.ignoredResponses 24641 # Number of memory responses ignored because the instruction is squashed 610system.cpu.iew.lsq.thread0.memOrderViolation 29761 # Number of memory ordering violations 611system.cpu.iew.lsq.thread0.squashedStores 10660231 # Number of stores squashed |
| 605system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 606system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 612system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 613system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 607system.cpu.iew.lsq.thread0.rescheduledLoads 225013 # Number of loads that were rescheduled 608system.cpu.iew.lsq.thread0.cacheBlocked 22508 # Number of times an access to memory failed due to the cache being blocked | 614system.cpu.iew.lsq.thread0.rescheduledLoads 224867 # Number of loads that were rescheduled 615system.cpu.iew.lsq.thread0.cacheBlocked 23122 # Number of times an access to memory failed due to the cache being blocked |
| 609system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 616system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 610system.cpu.iew.iewSquashCycles 6771922 # Number of cycles IEW is squashing 611system.cpu.iew.iewBlockCycles 22843049 # Number of cycles IEW is blocking 612system.cpu.iew.iewUnblockCycles 918168 # Number of cycles IEW is unblocking 613system.cpu.iew.iewDispatchedInsts 669223084 # Number of instructions dispatched to IQ | 617system.cpu.iew.iewSquashCycles 6772149 # Number of cycles IEW is squashing 618system.cpu.iew.iewBlockCycles 23809987 # Number of cycles IEW is blocking 619system.cpu.iew.iewUnblockCycles 977416 # Number of cycles IEW is unblocking 620system.cpu.iew.iewDispatchedInsts 669217601 # Number of instructions dispatched to IQ |
| 614system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 621system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 615system.cpu.iew.iewDispLoadInsts 142358029 # Number of dispatched load instructions 616system.cpu.iew.iewDispStoreInsts 67522859 # Number of dispatched store instructions 617system.cpu.iew.iewDispNonSpecInsts 1490792 # Number of dispatched non-speculative instructions 618system.cpu.iew.iewIQFullEvents 256633 # Number of times the IQ has become full, causing a stall 619system.cpu.iew.iewLSQFullEvents 523882 # Number of times the LSQ has become full, causing a stall 620system.cpu.iew.memOrderViolationEvents 29798 # Number of memory order violations 621system.cpu.iew.predictedTakenIncorrect 3590923 # Number of branches that were predicted taken incorrectly 622system.cpu.iew.predictedNotTakenIncorrect 3742651 # Number of branches that were predicted not taken incorrectly 623system.cpu.iew.branchMispredicts 7333574 # Number of branch mispredicts detected at execute 624system.cpu.iew.iewExecutedInsts 598420503 # Number of executed instructions 625system.cpu.iew.iewExecLoadInsts 129081054 # Number of load instructions executed 626system.cpu.iew.iewExecSquashedInsts 10506050 # Number of squashed instructions skipped in execute | 622system.cpu.iew.iewDispLoadInsts 142358041 # Number of dispatched load instructions 623system.cpu.iew.iewDispStoreInsts 67520451 # Number of dispatched store instructions 624system.cpu.iew.iewDispNonSpecInsts 1490836 # Number of dispatched non-speculative instructions 625system.cpu.iew.iewIQFullEvents 256647 # Number of times the IQ has become full, causing a stall 626system.cpu.iew.iewLSQFullEvents 583506 # Number of times the LSQ has become full, causing a stall 627system.cpu.iew.memOrderViolationEvents 29761 # Number of memory order violations 628system.cpu.iew.predictedTakenIncorrect 3591077 # Number of branches that were predicted taken incorrectly 629system.cpu.iew.predictedNotTakenIncorrect 3742851 # Number of branches that were predicted not taken incorrectly 630system.cpu.iew.branchMispredicts 7333928 # Number of branch mispredicts detected at execute 631system.cpu.iew.iewExecutedInsts 598406414 # Number of executed instructions 632system.cpu.iew.iewExecLoadInsts 129080217 # Number of load instructions executed 633system.cpu.iew.iewExecSquashedInsts 10498652 # Number of squashed instructions skipped in execute |
| 627system.cpu.iew.exec_swp 0 # number of swp insts executed | 634system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 628system.cpu.iew.exec_nop 1492814 # number of nop insts executed 629system.cpu.iew.exec_refs 190002009 # number of memory reference insts executed 630system.cpu.iew.exec_branches 131263961 # Number of branches executed 631system.cpu.iew.exec_stores 60920955 # Number of stores executed 632system.cpu.iew.exec_rate 1.282164 # Inst execution rate 633system.cpu.iew.wb_sent 595445456 # cumulative count of insts sent to commit 634system.cpu.iew.wb_count 594200604 # cumulative count of insts written-back 635system.cpu.iew.wb_producers 349565575 # num instructions producing a value 636system.cpu.iew.wb_consumers 571385188 # num instructions consuming a value 637system.cpu.iew.wb_rate 1.273123 # insts written-back per cycle 638system.cpu.iew.wb_fanout 0.611786 # average fanout of values written-back 639system.cpu.commit.commitSquashedInsts 107116116 # The number of squashed insts skipped by commit | 635system.cpu.iew.exec_nop 1492787 # number of nop insts executed 636system.cpu.iew.exec_refs 189993781 # number of memory reference insts executed 637system.cpu.iew.exec_branches 131261458 # Number of branches executed 638system.cpu.iew.exec_stores 60913564 # Number of stores executed 639system.cpu.iew.exec_rate 1.267626 # Inst execution rate 640system.cpu.iew.wb_sent 595430710 # cumulative count of insts sent to commit 641system.cpu.iew.wb_count 594185380 # cumulative count of insts written-back 642system.cpu.iew.wb_producers 349559163 # num instructions producing a value 643system.cpu.iew.wb_consumers 571371780 # num instructions consuming a value 644system.cpu.iew.wb_rate 1.258685 # insts written-back per cycle 645system.cpu.iew.wb_fanout 0.611789 # average fanout of values written-back 646system.cpu.commit.commitSquashedInsts 107108792 # The number of squashed insts skipped by commit |
| 640system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards | 647system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards |
| 641system.cpu.commit.branchMispredicts 6744856 # The number of times a branch was mispredicted 642system.cpu.commit.committed_per_cycle::samples 449285999 # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::mean 1.221253 # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::stdev 1.890713 # Number of insts commited each cycle | 648system.cpu.commit.branchMispredicts 6745133 # The number of times a branch was mispredicted 649system.cpu.commit.committed_per_cycle::samples 454284606 # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::mean 1.207816 # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::stdev 1.884395 # Number of insts commited each cycle |
| 645system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 652system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 646system.cpu.commit.committed_per_cycle::0 220514428 49.08% 49.08% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::1 116376748 25.90% 74.98% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::2 43480691 9.68% 84.66% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::3 23177999 5.16% 89.82% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::4 11514242 2.56% 92.38% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::5 7755129 1.73% 94.11% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::6 8259802 1.84% 95.95% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::7 4227193 0.94% 96.89% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::8 13979767 3.11% 100.00% # Number of insts commited each cycle | 653system.cpu.commit.committed_per_cycle::0 225505384 49.64% 49.64% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::1 116384460 25.62% 75.26% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::2 43472433 9.57% 84.83% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::3 23172184 5.10% 89.93% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::4 11521266 2.54% 92.47% # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::5 7756423 1.71% 94.17% # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::6 8277792 1.82% 95.99% # Number of insts commited each cycle 660system.cpu.commit.committed_per_cycle::7 4245082 0.93% 96.93% # Number of insts commited each cycle 661system.cpu.commit.committed_per_cycle::8 13949582 3.07% 100.00% # Number of insts commited each cycle |
| 655system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 662system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 663system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 664system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 658system.cpu.commit.committed_per_cycle::total 449285999 # Number of insts commited each cycle | 665system.cpu.commit.committed_per_cycle::total 454284606 # Number of insts commited each cycle |
| 659system.cpu.commit.committedInsts 506578818 # Number of instructions committed 660system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed 661system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 662system.cpu.commit.refs 172743503 # Number of memory references committed 663system.cpu.commit.loads 115883283 # Number of loads committed 664system.cpu.commit.membars 1488542 # Number of memory barriers committed 665system.cpu.commit.branches 121552863 # Number of branches committed 666system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 696system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 698system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 699system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 700system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction 701system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 702system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 703system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction | 666system.cpu.commit.committedInsts 506578818 # Number of instructions committed 667system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed 668system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 669system.cpu.commit.refs 172743503 # Number of memory references committed 670system.cpu.commit.loads 115883283 # Number of loads committed 671system.cpu.commit.membars 1488542 # Number of memory barriers committed 672system.cpu.commit.branches 121552863 # Number of branches committed 673system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 703system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 704system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 705system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 706system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 707system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction 708system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 709system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 710system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction |
| 704system.cpu.commit.bw_lim_events 13979767 # number cycles where commit BW limit reached 705system.cpu.rob.rob_reads 1091107249 # The number of ROB reads 706system.cpu.rob.rob_writes 1328306301 # The number of ROB writes 707system.cpu.timesIdled 14326 # Number of times that the entire CPU went into an idle state and unscheduled itself 708system.cpu.idleCycles 780311 # Total number of cycles that the CPU has spent unscheduled due to idling | 711system.cpu.commit.bw_lim_events 13949582 # number cycles where commit BW limit reached 712system.cpu.rob.rob_reads 1096128717 # The number of ROB reads 713system.cpu.rob.rob_writes 1328290478 # The number of ROB writes 714system.cpu.timesIdled 14613 # Number of times that the entire CPU went into an idle state and unscheduled itself 715system.cpu.idleCycles 1124363 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 709system.cpu.committedInsts 505234934 # Number of Instructions Simulated 710system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated | 716system.cpu.committedInsts 505234934 # Number of Instructions Simulated 717system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated |
| 711system.cpu.cpi 0.923782 # CPI: Cycles Per Instruction 712system.cpu.cpi_total 0.923782 # CPI: Total CPI of All Threads 713system.cpu.ipc 1.082507 # IPC: Instructions Per Cycle 714system.cpu.ipc_total 1.082507 # IPC: Total IPC of All Threads 715system.cpu.int_regfile_reads 610129735 # number of integer regfile reads 716system.cpu.int_regfile_writes 327331512 # number of integer regfile writes | 718system.cpu.cpi 0.934354 # CPI: Cycles Per Instruction 719system.cpu.cpi_total 0.934354 # CPI: Total CPI of All Threads 720system.cpu.ipc 1.070258 # IPC: Instructions Per Cycle 721system.cpu.ipc_total 1.070258 # IPC: Total IPC of All Threads 722system.cpu.int_regfile_reads 610109745 # number of integer regfile reads 723system.cpu.int_regfile_writes 327329948 # number of integer regfile writes |
| 717system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 724system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 718system.cpu.cc_regfile_reads 2166233884 # number of cc regfile reads 719system.cpu.cc_regfile_writes 376536291 # number of cc regfile writes 720system.cpu.misc_regfile_reads 217601523 # number of misc regfile reads | 725system.cpu.cc_regfile_reads 2166188285 # number of cc regfile reads 726system.cpu.cc_regfile_writes 376531340 # number of cc regfile writes 727system.cpu.misc_regfile_reads 217592371 # number of misc regfile reads |
| 721system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes | 728system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes |
| 722system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 723system.cpu.dcache.tags.replacements 2817306 # number of replacements 724system.cpu.dcache.tags.tagsinuse 511.628303 # Cycle average of tags in use 725system.cpu.dcache.tags.total_refs 168866082 # Total number of references to valid blocks. 726system.cpu.dcache.tags.sampled_refs 2817818 # Sample count of references to valid blocks. 727system.cpu.dcache.tags.avg_refs 59.927959 # Average number of references to valid blocks. 728system.cpu.dcache.tags.warmup_cycle 501259000 # Cycle when the warmup percentage was hit. 729system.cpu.dcache.tags.occ_blocks::cpu.data 511.628303 # Average occupied blocks per requestor | 729system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 730system.cpu.dcache.tags.replacements 2817297 # number of replacements 731system.cpu.dcache.tags.tagsinuse 511.628265 # Cycle average of tags in use 732system.cpu.dcache.tags.total_refs 168862807 # Total number of references to valid blocks. 733system.cpu.dcache.tags.sampled_refs 2817809 # Sample count of references to valid blocks. 734system.cpu.dcache.tags.avg_refs 59.926988 # Average number of references to valid blocks. 735system.cpu.dcache.tags.warmup_cycle 504720000 # Cycle when the warmup percentage was hit. 736system.cpu.dcache.tags.occ_blocks::cpu.data 511.628265 # Average occupied blocks per requestor |
| 730system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy 731system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy 732system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 737system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy 738system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy 739system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 733system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id 734system.cpu.dcache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id | 740system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id 741system.cpu.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id |
| 735system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 736system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 742system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 743system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 737system.cpu.dcache.tags.tag_accesses 355259202 # Number of tag accesses 738system.cpu.dcache.tags.data_accesses 355259202 # Number of data accesses 739system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 740system.cpu.dcache.ReadReq_hits::cpu.data 114162091 # number of ReadReq hits 741system.cpu.dcache.ReadReq_hits::total 114162091 # number of ReadReq hits 742system.cpu.dcache.WriteReq_hits::cpu.data 51724043 # number of WriteReq hits 743system.cpu.dcache.WriteReq_hits::total 51724043 # number of WriteReq hits 744system.cpu.dcache.SoftPFReq_hits::cpu.data 2789 # number of SoftPFReq hits 745system.cpu.dcache.SoftPFReq_hits::total 2789 # number of SoftPFReq hits | 744system.cpu.dcache.tags.tag_accesses 355255813 # Number of tag accesses 745system.cpu.dcache.tags.data_accesses 355255813 # Number of data accesses 746system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 747system.cpu.dcache.ReadReq_hits::cpu.data 114160281 # number of ReadReq hits 748system.cpu.dcache.ReadReq_hits::total 114160281 # number of ReadReq hits 749system.cpu.dcache.WriteReq_hits::cpu.data 51722579 # number of WriteReq hits 750system.cpu.dcache.WriteReq_hits::total 51722579 # number of WriteReq hits 751system.cpu.dcache.SoftPFReq_hits::cpu.data 2790 # number of SoftPFReq hits 752system.cpu.dcache.SoftPFReq_hits::total 2790 # number of SoftPFReq hits |
| 746system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits 747system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits 748system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 749system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits | 753system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits 754system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits 755system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 756system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits |
| 750system.cpu.dcache.demand_hits::cpu.data 165886134 # number of demand (read+write) hits 751system.cpu.dcache.demand_hits::total 165886134 # number of demand (read+write) hits 752system.cpu.dcache.overall_hits::cpu.data 165888923 # number of overall hits 753system.cpu.dcache.overall_hits::total 165888923 # number of overall hits 754system.cpu.dcache.ReadReq_misses::cpu.data 4839586 # number of ReadReq misses 755system.cpu.dcache.ReadReq_misses::total 4839586 # number of ReadReq misses 756system.cpu.dcache.WriteReq_misses::cpu.data 2515006 # number of WriteReq misses 757system.cpu.dcache.WriteReq_misses::total 2515006 # number of WriteReq misses 758system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses 759system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses | 757system.cpu.dcache.demand_hits::cpu.data 165882860 # number of demand (read+write) hits 758system.cpu.dcache.demand_hits::total 165882860 # number of demand (read+write) hits 759system.cpu.dcache.overall_hits::cpu.data 165885650 # number of overall hits 760system.cpu.dcache.overall_hits::total 165885650 # number of overall hits 761system.cpu.dcache.ReadReq_misses::cpu.data 4839703 # number of ReadReq misses 762system.cpu.dcache.ReadReq_misses::total 4839703 # number of ReadReq misses 763system.cpu.dcache.WriteReq_misses::cpu.data 2516470 # number of WriteReq misses 764system.cpu.dcache.WriteReq_misses::total 2516470 # number of WriteReq misses 765system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 766system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses |
| 760system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 761system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses | 767system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 768system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses |
| 762system.cpu.dcache.demand_misses::cpu.data 7354592 # number of demand (read+write) misses 763system.cpu.dcache.demand_misses::total 7354592 # number of demand (read+write) misses 764system.cpu.dcache.overall_misses::cpu.data 7354602 # number of overall misses 765system.cpu.dcache.overall_misses::total 7354602 # number of overall misses 766system.cpu.dcache.ReadReq_miss_latency::cpu.data 58596122500 # number of ReadReq miss cycles 767system.cpu.dcache.ReadReq_miss_latency::total 58596122500 # number of ReadReq miss cycles 768system.cpu.dcache.WriteReq_miss_latency::cpu.data 18922626430 # number of WriteReq miss cycles 769system.cpu.dcache.WriteReq_miss_latency::total 18922626430 # number of WriteReq miss cycles 770system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1155000 # number of LoadLockedReq miss cycles 771system.cpu.dcache.LoadLockedReq_miss_latency::total 1155000 # number of LoadLockedReq miss cycles 772system.cpu.dcache.demand_miss_latency::cpu.data 77518748930 # number of demand (read+write) miss cycles 773system.cpu.dcache.demand_miss_latency::total 77518748930 # number of demand (read+write) miss cycles 774system.cpu.dcache.overall_miss_latency::cpu.data 77518748930 # number of overall miss cycles 775system.cpu.dcache.overall_miss_latency::total 77518748930 # number of overall miss cycles 776system.cpu.dcache.ReadReq_accesses::cpu.data 119001677 # number of ReadReq accesses(hits+misses) 777system.cpu.dcache.ReadReq_accesses::total 119001677 # number of ReadReq accesses(hits+misses) | 769system.cpu.dcache.demand_misses::cpu.data 7356173 # number of demand (read+write) misses 770system.cpu.dcache.demand_misses::total 7356173 # number of demand (read+write) misses 771system.cpu.dcache.overall_misses::cpu.data 7356185 # number of overall misses 772system.cpu.dcache.overall_misses::total 7356185 # number of overall misses 773system.cpu.dcache.ReadReq_miss_latency::cpu.data 63969719500 # number of ReadReq miss cycles 774system.cpu.dcache.ReadReq_miss_latency::total 63969719500 # number of ReadReq miss cycles 775system.cpu.dcache.WriteReq_miss_latency::cpu.data 19897650428 # number of WriteReq miss cycles 776system.cpu.dcache.WriteReq_miss_latency::total 19897650428 # number of WriteReq miss cycles 777system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1356500 # number of LoadLockedReq miss cycles 778system.cpu.dcache.LoadLockedReq_miss_latency::total 1356500 # number of LoadLockedReq miss cycles 779system.cpu.dcache.demand_miss_latency::cpu.data 83867369928 # number of demand (read+write) miss cycles 780system.cpu.dcache.demand_miss_latency::total 83867369928 # number of demand (read+write) miss cycles 781system.cpu.dcache.overall_miss_latency::cpu.data 83867369928 # number of overall miss cycles 782system.cpu.dcache.overall_miss_latency::total 83867369928 # number of overall miss cycles 783system.cpu.dcache.ReadReq_accesses::cpu.data 118999984 # number of ReadReq accesses(hits+misses) 784system.cpu.dcache.ReadReq_accesses::total 118999984 # number of ReadReq accesses(hits+misses) |
| 778system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 779system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) | 785system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 786system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) |
| 780system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) 781system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) | 787system.cpu.dcache.SoftPFReq_accesses::cpu.data 2802 # number of SoftPFReq accesses(hits+misses) 788system.cpu.dcache.SoftPFReq_accesses::total 2802 # number of SoftPFReq accesses(hits+misses) |
| 782system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) 783system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) 784system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 785system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) | 789system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) 790system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) |
| 786system.cpu.dcache.demand_accesses::cpu.data 173240726 # number of demand (read+write) accesses 787system.cpu.dcache.demand_accesses::total 173240726 # number of demand (read+write) accesses 788system.cpu.dcache.overall_accesses::cpu.data 173243525 # number of overall (read+write) accesses 789system.cpu.dcache.overall_accesses::total 173243525 # number of overall (read+write) accesses 790system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040668 # miss rate for ReadReq accesses 791system.cpu.dcache.ReadReq_miss_rate::total 0.040668 # miss rate for ReadReq accesses 792system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046369 # miss rate for WriteReq accesses 793system.cpu.dcache.WriteReq_miss_rate::total 0.046369 # miss rate for WriteReq accesses 794system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003573 # miss rate for SoftPFReq accesses 795system.cpu.dcache.SoftPFReq_miss_rate::total 0.003573 # miss rate for SoftPFReq accesses | 793system.cpu.dcache.demand_accesses::cpu.data 173239033 # number of demand (read+write) accesses 794system.cpu.dcache.demand_accesses::total 173239033 # number of demand (read+write) accesses 795system.cpu.dcache.overall_accesses::cpu.data 173241835 # number of overall (read+write) accesses 796system.cpu.dcache.overall_accesses::total 173241835 # number of overall (read+write) accesses 797system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040670 # miss rate for ReadReq accesses 798system.cpu.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses 799system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046396 # miss rate for WriteReq accesses 800system.cpu.dcache.WriteReq_miss_rate::total 0.046396 # miss rate for WriteReq accesses 801system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004283 # miss rate for SoftPFReq accesses 802system.cpu.dcache.SoftPFReq_miss_rate::total 0.004283 # miss rate for SoftPFReq accesses |
| 796system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 797system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses | 803system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses |
| 798system.cpu.dcache.demand_miss_rate::cpu.data 0.042453 # miss rate for demand accesses 799system.cpu.dcache.demand_miss_rate::total 0.042453 # miss rate for demand accesses 800system.cpu.dcache.overall_miss_rate::cpu.data 0.042452 # miss rate for overall accesses 801system.cpu.dcache.overall_miss_rate::total 0.042452 # miss rate for overall accesses 802system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536 # average ReadReq miss latency 803system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536 # average ReadReq miss latency 804system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7523.889180 # average WriteReq miss latency 805system.cpu.dcache.WriteReq_avg_miss_latency::total 7523.889180 # average WriteReq miss latency 806system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17500 # average LoadLockedReq miss latency 807system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17500 # average LoadLockedReq miss latency 808system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457 # average overall miss latency 809system.cpu.dcache.demand_avg_miss_latency::total 10540.183457 # average overall miss latency 810system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125 # average overall miss latency 811system.cpu.dcache.overall_avg_miss_latency::total 10540.169125 # average overall miss latency 812system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked 813system.cpu.dcache.blocked_cycles::no_targets 907373 # number of cycles access was blocked 814system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 815system.cpu.dcache.blocked::no_targets 221320 # number of cycles access was blocked 816system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked 817system.cpu.dcache.avg_blocked_cycles::no_targets 4.099824 # average number of cycles each access was blocked 818system.cpu.dcache.writebacks::writebacks 2817306 # number of writebacks 819system.cpu.dcache.writebacks::total 2817306 # number of writebacks 820system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541564 # number of ReadReq MSHR hits 821system.cpu.dcache.ReadReq_mshr_hits::total 2541564 # number of ReadReq MSHR hits 822system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995189 # number of WriteReq MSHR hits 823system.cpu.dcache.WriteReq_mshr_hits::total 1995189 # number of WriteReq MSHR hits | 805system.cpu.dcache.demand_miss_rate::cpu.data 0.042463 # miss rate for demand accesses 806system.cpu.dcache.demand_miss_rate::total 0.042463 # miss rate for demand accesses 807system.cpu.dcache.overall_miss_rate::cpu.data 0.042462 # miss rate for overall accesses 808system.cpu.dcache.overall_miss_rate::total 0.042462 # miss rate for overall accesses 809system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280 # average ReadReq miss latency 810system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280 # average ReadReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7906.969059 # average WriteReq miss latency 812system.cpu.dcache.WriteReq_avg_miss_latency::total 7906.969059 # average WriteReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303 # average LoadLockedReq miss latency 814system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303 # average LoadLockedReq miss latency 815system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273 # average overall miss latency 816system.cpu.dcache.demand_avg_miss_latency::total 11400.951273 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675 # average overall miss latency 818system.cpu.dcache.overall_avg_miss_latency::total 11400.932675 # average overall miss latency 819system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked 820system.cpu.dcache.blocked_cycles::no_targets 1093581 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 822system.cpu.dcache.blocked::no_targets 221181 # number of cycles access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.333333 # average number of cycles each access was blocked 824system.cpu.dcache.avg_blocked_cycles::no_targets 4.944281 # average number of cycles each access was blocked 825system.cpu.dcache.writebacks::writebacks 2817297 # number of writebacks 826system.cpu.dcache.writebacks::total 2817297 # number of writebacks 827system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541719 # number of ReadReq MSHR hits 828system.cpu.dcache.ReadReq_mshr_hits::total 2541719 # number of ReadReq MSHR hits 829system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996628 # number of WriteReq MSHR hits 830system.cpu.dcache.WriteReq_mshr_hits::total 1996628 # number of WriteReq MSHR hits |
| 824system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 825system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits | 831system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 832system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits |
| 826system.cpu.dcache.demand_mshr_hits::cpu.data 4536753 # number of demand (read+write) MSHR hits 827system.cpu.dcache.demand_mshr_hits::total 4536753 # number of demand (read+write) MSHR hits 828system.cpu.dcache.overall_mshr_hits::cpu.data 4536753 # number of overall MSHR hits 829system.cpu.dcache.overall_mshr_hits::total 4536753 # number of overall MSHR hits 830system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298022 # number of ReadReq MSHR misses 831system.cpu.dcache.ReadReq_mshr_misses::total 2298022 # number of ReadReq MSHR misses 832system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519817 # number of WriteReq MSHR misses 833system.cpu.dcache.WriteReq_mshr_misses::total 519817 # number of WriteReq MSHR misses 834system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses 835system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses 836system.cpu.dcache.demand_mshr_misses::cpu.data 2817839 # number of demand (read+write) MSHR misses 837system.cpu.dcache.demand_mshr_misses::total 2817839 # number of demand (read+write) MSHR misses 838system.cpu.dcache.overall_mshr_misses::cpu.data 2817848 # number of overall MSHR misses 839system.cpu.dcache.overall_mshr_misses::total 2817848 # number of overall MSHR misses 840system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30115234500 # number of ReadReq MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_latency::total 30115234500 # number of ReadReq MSHR miss cycles 842system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603448995 # number of WriteReq MSHR miss cycles 843system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603448995 # number of WriteReq MSHR miss cycles 844system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 602500 # number of SoftPFReq MSHR miss cycles 845system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 602500 # number of SoftPFReq MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34718683495 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.demand_mshr_miss_latency::total 34718683495 # number of demand (read+write) MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34719285995 # number of overall MSHR miss cycles 849system.cpu.dcache.overall_mshr_miss_latency::total 34719285995 # number of overall MSHR miss cycles | 833system.cpu.dcache.demand_mshr_hits::cpu.data 4538347 # number of demand (read+write) MSHR hits 834system.cpu.dcache.demand_mshr_hits::total 4538347 # number of demand (read+write) MSHR hits 835system.cpu.dcache.overall_mshr_hits::cpu.data 4538347 # number of overall MSHR hits 836system.cpu.dcache.overall_mshr_hits::total 4538347 # number of overall MSHR hits 837system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297984 # number of ReadReq MSHR misses 838system.cpu.dcache.ReadReq_mshr_misses::total 2297984 # number of ReadReq MSHR misses 839system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519842 # number of WriteReq MSHR misses 840system.cpu.dcache.WriteReq_mshr_misses::total 519842 # number of WriteReq MSHR misses 841system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 842system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 843system.cpu.dcache.demand_mshr_misses::cpu.data 2817826 # number of demand (read+write) MSHR misses 844system.cpu.dcache.demand_mshr_misses::total 2817826 # number of demand (read+write) MSHR misses 845system.cpu.dcache.overall_mshr_misses::cpu.data 2817836 # number of overall MSHR misses 846system.cpu.dcache.overall_mshr_misses::total 2817836 # number of overall MSHR misses 847system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32775846000 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.ReadReq_mshr_miss_latency::total 32775846000 # number of ReadReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786094494 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786094494 # number of WriteReq MSHR miss cycles 851system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1244000 # number of SoftPFReq MSHR miss cycles 852system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1244000 # number of SoftPFReq MSHR miss cycles 853system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37561940494 # number of demand (read+write) MSHR miss cycles 854system.cpu.dcache.demand_mshr_miss_latency::total 37561940494 # number of demand (read+write) MSHR miss cycles 855system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563184494 # number of overall MSHR miss cycles 856system.cpu.dcache.overall_mshr_miss_latency::total 37563184494 # number of overall MSHR miss cycles |
| 850system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses | 857system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses 858system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses 859system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses 860system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses |
| 854system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003215 # mshr miss rate for SoftPFReq accesses 855system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003215 # mshr miss rate for SoftPFReq accesses 856system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for demand accesses 857system.cpu.dcache.demand_mshr_miss_rate::total 0.016265 # mshr miss rate for demand accesses | 861system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for SoftPFReq accesses 862system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003569 # mshr miss rate for SoftPFReq accesses 863system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016266 # mshr miss rate for demand accesses 864system.cpu.dcache.demand_mshr_miss_rate::total 0.016266 # mshr miss rate for demand accesses |
| 858system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses 859system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses | 865system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses 866system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses |
| 860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13104.850389 # average ReadReq mshr miss latency 861system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13104.850389 # average ReadReq mshr miss latency 862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.903126 # average WriteReq mshr miss latency 863system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.903126 # average WriteReq mshr miss latency 864system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66944.444444 # average SoftPFReq mshr miss latency 865system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66944.444444 # average SoftPFReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12321.031647 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 12321.031647 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12321.206110 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 12321.206110 # average overall mshr miss latency 870system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 871system.cpu.icache.tags.replacements 76636 # number of replacements 872system.cpu.icache.tags.tagsinuse 466.486924 # Cycle average of tags in use 873system.cpu.icache.tags.total_refs 235189788 # Total number of references to valid blocks. 874system.cpu.icache.tags.sampled_refs 77148 # Sample count of references to valid blocks. 875system.cpu.icache.tags.avg_refs 3048.553274 # Average number of references to valid blocks. 876system.cpu.icache.tags.warmup_cycle 115712400500 # Cycle when the warmup percentage was hit. 877system.cpu.icache.tags.occ_blocks::cpu.inst 466.486924 # Average occupied blocks per requestor 878system.cpu.icache.tags.occ_percent::cpu.inst 0.911107 # Average percentage of cache occupancy 879system.cpu.icache.tags.occ_percent::total 0.911107 # Average percentage of cache occupancy | 867system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14262.869541 # average ReadReq mshr miss latency 868system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14262.869541 # average ReadReq mshr miss latency 869system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9206.825332 # average WriteReq mshr miss latency 870system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9206.825332 # average WriteReq mshr miss latency 871system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 124400 # average SoftPFReq mshr miss latency 872system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 124400 # average SoftPFReq mshr miss latency 873system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13330.113532 # average overall mshr miss latency 874system.cpu.dcache.demand_avg_mshr_miss_latency::total 13330.113532 # average overall mshr miss latency 875system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13330.507700 # average overall mshr miss latency 876system.cpu.dcache.overall_avg_mshr_miss_latency::total 13330.507700 # average overall mshr miss latency 877system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 878system.cpu.icache.tags.replacements 76619 # number of replacements 879system.cpu.icache.tags.tagsinuse 466.071602 # Cycle average of tags in use 880system.cpu.icache.tags.total_refs 235190778 # Total number of references to valid blocks. 881system.cpu.icache.tags.sampled_refs 77131 # Sample count of references to valid blocks. 882system.cpu.icache.tags.avg_refs 3049.238024 # Average number of references to valid blocks. 883system.cpu.icache.tags.warmup_cycle 116612189500 # Cycle when the warmup percentage was hit. 884system.cpu.icache.tags.occ_blocks::cpu.inst 466.071602 # Average occupied blocks per requestor 885system.cpu.icache.tags.occ_percent::cpu.inst 0.910296 # Average percentage of cache occupancy 886system.cpu.icache.tags.occ_percent::total 0.910296 # Average percentage of cache occupancy |
| 880system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 887system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 881system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id 883system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id 884system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id | 888system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 889system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 890system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id 891system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id |
| 885system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 886system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 892system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 893system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 887system.cpu.icache.tags.tag_accesses 470628332 # Number of tag accesses 888system.cpu.icache.tags.data_accesses 470628332 # Number of data accesses 889system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 890system.cpu.icache.ReadReq_hits::cpu.inst 235189788 # number of ReadReq hits 891system.cpu.icache.ReadReq_hits::total 235189788 # number of ReadReq hits 892system.cpu.icache.demand_hits::cpu.inst 235189788 # number of demand (read+write) hits 893system.cpu.icache.demand_hits::total 235189788 # number of demand (read+write) hits 894system.cpu.icache.overall_hits::cpu.inst 235189788 # number of overall hits 895system.cpu.icache.overall_hits::total 235189788 # number of overall hits 896system.cpu.icache.ReadReq_misses::cpu.inst 85789 # number of ReadReq misses 897system.cpu.icache.ReadReq_misses::total 85789 # number of ReadReq misses 898system.cpu.icache.demand_misses::cpu.inst 85789 # number of demand (read+write) misses 899system.cpu.icache.demand_misses::total 85789 # number of demand (read+write) misses 900system.cpu.icache.overall_misses::cpu.inst 85789 # number of overall misses 901system.cpu.icache.overall_misses::total 85789 # number of overall misses 902system.cpu.icache.ReadReq_miss_latency::cpu.inst 1556704687 # number of ReadReq miss cycles 903system.cpu.icache.ReadReq_miss_latency::total 1556704687 # number of ReadReq miss cycles 904system.cpu.icache.demand_miss_latency::cpu.inst 1556704687 # number of demand (read+write) miss cycles 905system.cpu.icache.demand_miss_latency::total 1556704687 # number of demand (read+write) miss cycles 906system.cpu.icache.overall_miss_latency::cpu.inst 1556704687 # number of overall miss cycles 907system.cpu.icache.overall_miss_latency::total 1556704687 # number of overall miss cycles 908system.cpu.icache.ReadReq_accesses::cpu.inst 235275577 # number of ReadReq accesses(hits+misses) 909system.cpu.icache.ReadReq_accesses::total 235275577 # number of ReadReq accesses(hits+misses) 910system.cpu.icache.demand_accesses::cpu.inst 235275577 # number of demand (read+write) accesses 911system.cpu.icache.demand_accesses::total 235275577 # number of demand (read+write) accesses 912system.cpu.icache.overall_accesses::cpu.inst 235275577 # number of overall (read+write) accesses 913system.cpu.icache.overall_accesses::total 235275577 # number of overall (read+write) accesses | 894system.cpu.icache.tags.tag_accesses 470630395 # Number of tag accesses 895system.cpu.icache.tags.data_accesses 470630395 # Number of data accesses 896system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 897system.cpu.icache.ReadReq_hits::cpu.inst 235190778 # number of ReadReq hits 898system.cpu.icache.ReadReq_hits::total 235190778 # number of ReadReq hits 899system.cpu.icache.demand_hits::cpu.inst 235190778 # number of demand (read+write) hits 900system.cpu.icache.demand_hits::total 235190778 # number of demand (read+write) hits 901system.cpu.icache.overall_hits::cpu.inst 235190778 # number of overall hits 902system.cpu.icache.overall_hits::total 235190778 # number of overall hits 903system.cpu.icache.ReadReq_misses::cpu.inst 85841 # number of ReadReq misses 904system.cpu.icache.ReadReq_misses::total 85841 # number of ReadReq misses 905system.cpu.icache.demand_misses::cpu.inst 85841 # number of demand (read+write) misses 906system.cpu.icache.demand_misses::total 85841 # number of demand (read+write) misses 907system.cpu.icache.overall_misses::cpu.inst 85841 # number of overall misses 908system.cpu.icache.overall_misses::total 85841 # number of overall misses 909system.cpu.icache.ReadReq_miss_latency::cpu.inst 1941915678 # number of ReadReq miss cycles 910system.cpu.icache.ReadReq_miss_latency::total 1941915678 # number of ReadReq miss cycles 911system.cpu.icache.demand_miss_latency::cpu.inst 1941915678 # number of demand (read+write) miss cycles 912system.cpu.icache.demand_miss_latency::total 1941915678 # number of demand (read+write) miss cycles 913system.cpu.icache.overall_miss_latency::cpu.inst 1941915678 # number of overall miss cycles 914system.cpu.icache.overall_miss_latency::total 1941915678 # number of overall miss cycles 915system.cpu.icache.ReadReq_accesses::cpu.inst 235276619 # number of ReadReq accesses(hits+misses) 916system.cpu.icache.ReadReq_accesses::total 235276619 # number of ReadReq accesses(hits+misses) 917system.cpu.icache.demand_accesses::cpu.inst 235276619 # number of demand (read+write) accesses 918system.cpu.icache.demand_accesses::total 235276619 # number of demand (read+write) accesses 919system.cpu.icache.overall_accesses::cpu.inst 235276619 # number of overall (read+write) accesses 920system.cpu.icache.overall_accesses::total 235276619 # number of overall (read+write) accesses |
| 914system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses 915system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses 916system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses 917system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses 918system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses 919system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses | 921system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses 922system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses 923system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses 924system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses 925system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses 926system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses |
| 920system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647 # average ReadReq miss latency 921system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647 # average ReadReq miss latency 922system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency 923system.cpu.icache.demand_avg_miss_latency::total 18145.737647 # average overall miss latency 924system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency 925system.cpu.icache.overall_avg_miss_latency::total 18145.737647 # average overall miss latency 926system.cpu.icache.blocked_cycles::no_mshrs 171831 # number of cycles access was blocked 927system.cpu.icache.blocked_cycles::no_targets 200 # number of cycles access was blocked 928system.cpu.icache.blocked::no_mshrs 6857 # number of cycles access was blocked 929system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked 930system.cpu.icache.avg_blocked_cycles::no_mshrs 25.059210 # average number of cycles each access was blocked 931system.cpu.icache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked 932system.cpu.icache.writebacks::writebacks 76636 # number of writebacks 933system.cpu.icache.writebacks::total 76636 # number of writebacks 934system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8610 # number of ReadReq MSHR hits 935system.cpu.icache.ReadReq_mshr_hits::total 8610 # number of ReadReq MSHR hits 936system.cpu.icache.demand_mshr_hits::cpu.inst 8610 # number of demand (read+write) MSHR hits 937system.cpu.icache.demand_mshr_hits::total 8610 # number of demand (read+write) MSHR hits 938system.cpu.icache.overall_mshr_hits::cpu.inst 8610 # number of overall MSHR hits 939system.cpu.icache.overall_mshr_hits::total 8610 # number of overall MSHR hits 940system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77179 # number of ReadReq MSHR misses 941system.cpu.icache.ReadReq_mshr_misses::total 77179 # number of ReadReq MSHR misses 942system.cpu.icache.demand_mshr_misses::cpu.inst 77179 # number of demand (read+write) MSHR misses 943system.cpu.icache.demand_mshr_misses::total 77179 # number of demand (read+write) MSHR misses 944system.cpu.icache.overall_mshr_misses::cpu.inst 77179 # number of overall MSHR misses 945system.cpu.icache.overall_mshr_misses::total 77179 # number of overall MSHR misses 946system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1268632793 # number of ReadReq MSHR miss cycles 947system.cpu.icache.ReadReq_mshr_miss_latency::total 1268632793 # number of ReadReq MSHR miss cycles 948system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1268632793 # number of demand (read+write) MSHR miss cycles 949system.cpu.icache.demand_mshr_miss_latency::total 1268632793 # number of demand (read+write) MSHR miss cycles 950system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1268632793 # number of overall MSHR miss cycles 951system.cpu.icache.overall_mshr_miss_latency::total 1268632793 # number of overall MSHR miss cycles | 927system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22622.239699 # average ReadReq miss latency 928system.cpu.icache.ReadReq_avg_miss_latency::total 22622.239699 # average ReadReq miss latency 929system.cpu.icache.demand_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency 930system.cpu.icache.demand_avg_miss_latency::total 22622.239699 # average overall miss latency 931system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency 932system.cpu.icache.overall_avg_miss_latency::total 22622.239699 # average overall miss latency 933system.cpu.icache.blocked_cycles::no_mshrs 206659 # number of cycles access was blocked 934system.cpu.icache.blocked_cycles::no_targets 2170 # number of cycles access was blocked 935system.cpu.icache.blocked::no_mshrs 7236 # number of cycles access was blocked 936system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked 937system.cpu.icache.avg_blocked_cycles::no_mshrs 28.559840 # average number of cycles each access was blocked 938system.cpu.icache.avg_blocked_cycles::no_targets 197.272727 # average number of cycles each access was blocked 939system.cpu.icache.writebacks::writebacks 76619 # number of writebacks 940system.cpu.icache.writebacks::total 76619 # number of writebacks 941system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8683 # number of ReadReq MSHR hits 942system.cpu.icache.ReadReq_mshr_hits::total 8683 # number of ReadReq MSHR hits 943system.cpu.icache.demand_mshr_hits::cpu.inst 8683 # number of demand (read+write) MSHR hits 944system.cpu.icache.demand_mshr_hits::total 8683 # number of demand (read+write) MSHR hits 945system.cpu.icache.overall_mshr_hits::cpu.inst 8683 # number of overall MSHR hits 946system.cpu.icache.overall_mshr_hits::total 8683 # number of overall MSHR hits 947system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77158 # number of ReadReq MSHR misses 948system.cpu.icache.ReadReq_mshr_misses::total 77158 # number of ReadReq MSHR misses 949system.cpu.icache.demand_mshr_misses::cpu.inst 77158 # number of demand (read+write) MSHR misses 950system.cpu.icache.demand_mshr_misses::total 77158 # number of demand (read+write) MSHR misses 951system.cpu.icache.overall_mshr_misses::cpu.inst 77158 # number of overall MSHR misses 952system.cpu.icache.overall_mshr_misses::total 77158 # number of overall MSHR misses 953system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1536678279 # number of ReadReq MSHR miss cycles 954system.cpu.icache.ReadReq_mshr_miss_latency::total 1536678279 # number of ReadReq MSHR miss cycles 955system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1536678279 # number of demand (read+write) MSHR miss cycles 956system.cpu.icache.demand_mshr_miss_latency::total 1536678279 # number of demand (read+write) MSHR miss cycles 957system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1536678279 # number of overall MSHR miss cycles 958system.cpu.icache.overall_mshr_miss_latency::total 1536678279 # number of overall MSHR miss cycles |
| 952system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses 953system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses 954system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses 955system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses 956system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 957system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses | 959system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses 960system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses 961system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses 962system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses 963system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 964system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses |
| 958system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16437.538618 # average ReadReq mshr miss latency 959system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16437.538618 # average ReadReq mshr miss latency 960system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency 961system.cpu.icache.demand_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency 962system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency 963system.cpu.icache.overall_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency 964system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 965system.cpu.l2cache.prefetcher.num_hwpf_issued 8513734 # number of hwpf issued 966system.cpu.l2cache.prefetcher.pfIdentified 8515093 # number of prefetch candidates identified 967system.cpu.l2cache.prefetcher.pfBufferHit 374 # number of redundant prefetches already in prefetch queue | 965system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19915.994181 # average ReadReq mshr miss latency 966system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19915.994181 # average ReadReq mshr miss latency 967system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency 968system.cpu.icache.demand_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency 969system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency 970system.cpu.icache.overall_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency 971system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 972system.cpu.l2cache.prefetcher.num_hwpf_issued 8510000 # number of hwpf issued 973system.cpu.l2cache.prefetcher.pfIdentified 8511429 # number of prefetch candidates identified 974system.cpu.l2cache.prefetcher.pfBufferHit 428 # number of redundant prefetches already in prefetch queue |
| 968system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 969system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 975system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 976system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 970system.cpu.l2cache.prefetcher.pfSpanPage 743899 # number of prefetches not generated due to page crossing 971system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 972system.cpu.l2cache.tags.replacements 390403 # number of replacements 973system.cpu.l2cache.tags.tagsinuse 15000.108571 # Cycle average of tags in use 974system.cpu.l2cache.tags.total_refs 2699085 # Total number of references to valid blocks. 975system.cpu.l2cache.tags.sampled_refs 406018 # Sample count of references to valid blocks. 976system.cpu.l2cache.tags.avg_refs 6.647698 # Average number of references to valid blocks. | 977system.cpu.l2cache.prefetcher.pfSpanPage 743291 # number of prefetches not generated due to page crossing 978system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 979system.cpu.l2cache.tags.replacements 389594 # number of replacements 980system.cpu.l2cache.tags.tagsinuse 15007.037789 # Cycle average of tags in use 981system.cpu.l2cache.tags.total_refs 2698812 # Total number of references to valid blocks. 982system.cpu.l2cache.tags.sampled_refs 405195 # Sample count of references to valid blocks. 983system.cpu.l2cache.tags.avg_refs 6.660526 # Average number of references to valid blocks. |
| 977system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 984system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 978system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493 # Average occupied blocks per requestor 979system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.046079 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_percent::writebacks 0.911015 # Average percentage of cache occupancy 981system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004519 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_percent::total 0.915534 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_task_id_blocks::1022 114 # Occupied blocks per task id 984system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # Occupied blocks per task id | 985system.cpu.l2cache.tags.occ_blocks::writebacks 14932.547255 # Average occupied blocks per requestor 986system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.490534 # Average occupied blocks per requestor 987system.cpu.l2cache.tags.occ_percent::writebacks 0.911410 # Average percentage of cache occupancy 988system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004547 # Average percentage of cache occupancy 989system.cpu.l2cache.tags.occ_percent::total 0.915957 # Average percentage of cache occupancy 990system.cpu.l2cache.tags.occ_task_id_blocks::1022 98 # Occupied blocks per task id 991system.cpu.l2cache.tags.occ_task_id_blocks::1024 15503 # Occupied blocks per task id |
| 985system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id | 992system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id |
| 986system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1022::3 46 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5426 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6626 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2533 # Occupied blocks per task id 995system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006958 # Percentage of cache occupancy per task id 996system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946106 # Percentage of cache occupancy per task id 997system.cpu.l2cache.tags.tag_accesses 95370697 # Number of tag accesses 998system.cpu.l2cache.tags.data_accesses 95370697 # Number of data accesses 999system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 1000system.cpu.l2cache.WritebackDirty_hits::writebacks 2353941 # number of WritebackDirty hits 1001system.cpu.l2cache.WritebackDirty_hits::total 2353941 # number of WritebackDirty hits 1002system.cpu.l2cache.WritebackClean_hits::writebacks 516320 # number of WritebackClean hits 1003system.cpu.l2cache.WritebackClean_hits::total 516320 # number of WritebackClean hits 1004system.cpu.l2cache.ReadExReq_hits::cpu.data 516934 # number of ReadExReq hits 1005system.cpu.l2cache.ReadExReq_hits::total 516934 # number of ReadExReq hits 1006system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67108 # number of ReadCleanReq hits 1007system.cpu.l2cache.ReadCleanReq_hits::total 67108 # number of ReadCleanReq hits 1008system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130993 # number of ReadSharedReq hits 1009system.cpu.l2cache.ReadSharedReq_hits::total 2130993 # number of ReadSharedReq hits 1010system.cpu.l2cache.demand_hits::cpu.inst 67108 # number of demand (read+write) hits 1011system.cpu.l2cache.demand_hits::cpu.data 2647927 # number of demand (read+write) hits 1012system.cpu.l2cache.demand_hits::total 2715035 # number of demand (read+write) hits 1013system.cpu.l2cache.overall_hits::cpu.inst 67108 # number of overall hits 1014system.cpu.l2cache.overall_hits::cpu.data 2647927 # number of overall hits 1015system.cpu.l2cache.overall_hits::total 2715035 # number of overall hits 1016system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses 1017system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses 1018system.cpu.l2cache.ReadExReq_misses::cpu.data 5078 # number of ReadExReq misses 1019system.cpu.l2cache.ReadExReq_misses::total 5078 # number of ReadExReq misses 1020system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10036 # number of ReadCleanReq misses 1021system.cpu.l2cache.ReadCleanReq_misses::total 10036 # number of ReadCleanReq misses 1022system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164813 # number of ReadSharedReq misses 1023system.cpu.l2cache.ReadSharedReq_misses::total 164813 # number of ReadSharedReq misses 1024system.cpu.l2cache.demand_misses::cpu.inst 10036 # number of demand (read+write) misses 1025system.cpu.l2cache.demand_misses::cpu.data 169891 # number of demand (read+write) misses 1026system.cpu.l2cache.demand_misses::total 179927 # number of demand (read+write) misses 1027system.cpu.l2cache.overall_misses::cpu.inst 10036 # number of overall misses 1028system.cpu.l2cache.overall_misses::cpu.data 169891 # number of overall misses 1029system.cpu.l2cache.overall_misses::total 179927 # number of overall misses 1030system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21000 # number of UpgradeReq miss cycles 1031system.cpu.l2cache.UpgradeReq_miss_latency::total 21000 # number of UpgradeReq miss cycles 1032system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 484083500 # number of ReadExReq miss cycles 1033system.cpu.l2cache.ReadExReq_miss_latency::total 484083500 # number of ReadExReq miss cycles 1034system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 750585000 # number of ReadCleanReq miss cycles 1035system.cpu.l2cache.ReadCleanReq_miss_latency::total 750585000 # number of ReadCleanReq miss cycles 1036system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12710440000 # number of ReadSharedReq miss cycles 1037system.cpu.l2cache.ReadSharedReq_miss_latency::total 12710440000 # number of ReadSharedReq miss cycles 1038system.cpu.l2cache.demand_miss_latency::cpu.inst 750585000 # number of demand (read+write) miss cycles 1039system.cpu.l2cache.demand_miss_latency::cpu.data 13194523500 # number of demand (read+write) miss cycles 1040system.cpu.l2cache.demand_miss_latency::total 13945108500 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.overall_miss_latency::cpu.inst 750585000 # number of overall miss cycles 1042system.cpu.l2cache.overall_miss_latency::cpu.data 13194523500 # number of overall miss cycles 1043system.cpu.l2cache.overall_miss_latency::total 13945108500 # number of overall miss cycles 1044system.cpu.l2cache.WritebackDirty_accesses::writebacks 2353941 # number of WritebackDirty accesses(hits+misses) 1045system.cpu.l2cache.WritebackDirty_accesses::total 2353941 # number of WritebackDirty accesses(hits+misses) 1046system.cpu.l2cache.WritebackClean_accesses::writebacks 516320 # number of WritebackClean accesses(hits+misses) 1047system.cpu.l2cache.WritebackClean_accesses::total 516320 # number of WritebackClean accesses(hits+misses) 1048system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30 # number of UpgradeReq accesses(hits+misses) 1049system.cpu.l2cache.UpgradeReq_accesses::total 30 # number of UpgradeReq accesses(hits+misses) 1050system.cpu.l2cache.ReadExReq_accesses::cpu.data 522012 # number of ReadExReq accesses(hits+misses) 1051system.cpu.l2cache.ReadExReq_accesses::total 522012 # number of ReadExReq accesses(hits+misses) 1052system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77144 # number of ReadCleanReq accesses(hits+misses) 1053system.cpu.l2cache.ReadCleanReq_accesses::total 77144 # number of ReadCleanReq accesses(hits+misses) 1054system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295806 # number of ReadSharedReq accesses(hits+misses) 1055system.cpu.l2cache.ReadSharedReq_accesses::total 2295806 # number of ReadSharedReq accesses(hits+misses) 1056system.cpu.l2cache.demand_accesses::cpu.inst 77144 # number of demand (read+write) accesses 1057system.cpu.l2cache.demand_accesses::cpu.data 2817818 # number of demand (read+write) accesses 1058system.cpu.l2cache.demand_accesses::total 2894962 # number of demand (read+write) accesses 1059system.cpu.l2cache.overall_accesses::cpu.inst 77144 # number of overall (read+write) accesses 1060system.cpu.l2cache.overall_accesses::cpu.data 2817818 # number of overall (read+write) accesses 1061system.cpu.l2cache.overall_accesses::total 2894962 # number of overall (read+write) accesses | 993system.cpu.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1022::3 41 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id 997system.cpu.l2cache.tags.age_task_id_blocks_1024::1 672 # Occupied blocks per task id 998system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5433 # Occupied blocks per task id 999system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6587 # Occupied blocks per task id 1000system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2565 # Occupied blocks per task id 1001system.cpu.l2cache.tags.occ_task_id_percent::1022 0.005981 # Percentage of cache occupancy per task id 1002system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946228 # Percentage of cache occupancy per task id 1003system.cpu.l2cache.tags.tag_accesses 95366335 # Number of tag accesses 1004system.cpu.l2cache.tags.data_accesses 95366335 # Number of data accesses 1005system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 1006system.cpu.l2cache.WritebackDirty_hits::writebacks 2351800 # number of WritebackDirty hits 1007system.cpu.l2cache.WritebackDirty_hits::total 2351800 # number of WritebackDirty hits 1008system.cpu.l2cache.WritebackClean_hits::writebacks 518252 # number of WritebackClean hits 1009system.cpu.l2cache.WritebackClean_hits::total 518252 # number of WritebackClean hits 1010system.cpu.l2cache.ReadExReq_hits::cpu.data 516857 # number of ReadExReq hits 1011system.cpu.l2cache.ReadExReq_hits::total 516857 # number of ReadExReq hits 1012system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67161 # number of ReadCleanReq hits 1013system.cpu.l2cache.ReadCleanReq_hits::total 67161 # number of ReadCleanReq hits 1014system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130903 # number of ReadSharedReq hits 1015system.cpu.l2cache.ReadSharedReq_hits::total 2130903 # number of ReadSharedReq hits 1016system.cpu.l2cache.demand_hits::cpu.inst 67161 # number of demand (read+write) hits 1017system.cpu.l2cache.demand_hits::cpu.data 2647760 # number of demand (read+write) hits 1018system.cpu.l2cache.demand_hits::total 2714921 # number of demand (read+write) hits 1019system.cpu.l2cache.overall_hits::cpu.inst 67161 # number of overall hits 1020system.cpu.l2cache.overall_hits::cpu.data 2647760 # number of overall hits 1021system.cpu.l2cache.overall_hits::total 2714921 # number of overall hits 1022system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses 1023system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses 1024system.cpu.l2cache.ReadExReq_misses::cpu.data 5168 # number of ReadExReq misses 1025system.cpu.l2cache.ReadExReq_misses::total 5168 # number of ReadExReq misses 1026system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9964 # number of ReadCleanReq misses 1027system.cpu.l2cache.ReadCleanReq_misses::total 9964 # number of ReadCleanReq misses 1028system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164881 # number of ReadSharedReq misses 1029system.cpu.l2cache.ReadSharedReq_misses::total 164881 # number of ReadSharedReq misses 1030system.cpu.l2cache.demand_misses::cpu.inst 9964 # number of demand (read+write) misses 1031system.cpu.l2cache.demand_misses::cpu.data 170049 # number of demand (read+write) misses 1032system.cpu.l2cache.demand_misses::total 180013 # number of demand (read+write) misses 1033system.cpu.l2cache.overall_misses::cpu.inst 9964 # number of overall misses 1034system.cpu.l2cache.overall_misses::cpu.data 170049 # number of overall misses 1035system.cpu.l2cache.overall_misses::total 180013 # number of overall misses 1036system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 20500 # number of UpgradeReq miss cycles 1037system.cpu.l2cache.UpgradeReq_miss_latency::total 20500 # number of UpgradeReq miss cycles 1038system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 668599000 # number of ReadExReq miss cycles 1039system.cpu.l2cache.ReadExReq_miss_latency::total 668599000 # number of ReadExReq miss cycles 1040system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1018287500 # number of ReadCleanReq miss cycles 1041system.cpu.l2cache.ReadCleanReq_miss_latency::total 1018287500 # number of ReadCleanReq miss cycles 1042system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371092500 # number of ReadSharedReq miss cycles 1043system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371092500 # number of ReadSharedReq miss cycles 1044system.cpu.l2cache.demand_miss_latency::cpu.inst 1018287500 # number of demand (read+write) miss cycles 1045system.cpu.l2cache.demand_miss_latency::cpu.data 16039691500 # number of demand (read+write) miss cycles 1046system.cpu.l2cache.demand_miss_latency::total 17057979000 # number of demand (read+write) miss cycles 1047system.cpu.l2cache.overall_miss_latency::cpu.inst 1018287500 # number of overall miss cycles 1048system.cpu.l2cache.overall_miss_latency::cpu.data 16039691500 # number of overall miss cycles 1049system.cpu.l2cache.overall_miss_latency::total 17057979000 # number of overall miss cycles 1050system.cpu.l2cache.WritebackDirty_accesses::writebacks 2351800 # number of WritebackDirty accesses(hits+misses) 1051system.cpu.l2cache.WritebackDirty_accesses::total 2351800 # number of WritebackDirty accesses(hits+misses) 1052system.cpu.l2cache.WritebackClean_accesses::writebacks 518252 # number of WritebackClean accesses(hits+misses) 1053system.cpu.l2cache.WritebackClean_accesses::total 518252 # number of WritebackClean accesses(hits+misses) 1054system.cpu.l2cache.UpgradeReq_accesses::cpu.data 27 # number of UpgradeReq accesses(hits+misses) 1055system.cpu.l2cache.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) 1056system.cpu.l2cache.ReadExReq_accesses::cpu.data 522025 # number of ReadExReq accesses(hits+misses) 1057system.cpu.l2cache.ReadExReq_accesses::total 522025 # number of ReadExReq accesses(hits+misses) 1058system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77125 # number of ReadCleanReq accesses(hits+misses) 1059system.cpu.l2cache.ReadCleanReq_accesses::total 77125 # number of ReadCleanReq accesses(hits+misses) 1060system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295784 # number of ReadSharedReq accesses(hits+misses) 1061system.cpu.l2cache.ReadSharedReq_accesses::total 2295784 # number of ReadSharedReq accesses(hits+misses) 1062system.cpu.l2cache.demand_accesses::cpu.inst 77125 # number of demand (read+write) accesses 1063system.cpu.l2cache.demand_accesses::cpu.data 2817809 # number of demand (read+write) accesses 1064system.cpu.l2cache.demand_accesses::total 2894934 # number of demand (read+write) accesses 1065system.cpu.l2cache.overall_accesses::cpu.inst 77125 # number of overall (read+write) accesses 1066system.cpu.l2cache.overall_accesses::cpu.data 2817809 # number of overall (read+write) accesses 1067system.cpu.l2cache.overall_accesses::total 2894934 # number of overall (read+write) accesses |
| 1062system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1063system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1068system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1069system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1064system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009728 # miss rate for ReadExReq accesses 1065system.cpu.l2cache.ReadExReq_miss_rate::total 0.009728 # miss rate for ReadExReq accesses 1066system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.130094 # miss rate for ReadCleanReq accesses 1067system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.130094 # miss rate for ReadCleanReq accesses 1068system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071789 # miss rate for ReadSharedReq accesses 1069system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071789 # miss rate for ReadSharedReq accesses 1070system.cpu.l2cache.demand_miss_rate::cpu.inst 0.130094 # miss rate for demand accesses 1071system.cpu.l2cache.demand_miss_rate::cpu.data 0.060292 # miss rate for demand accesses 1072system.cpu.l2cache.demand_miss_rate::total 0.062152 # miss rate for demand accesses 1073system.cpu.l2cache.overall_miss_rate::cpu.inst 0.130094 # miss rate for overall accesses 1074system.cpu.l2cache.overall_miss_rate::cpu.data 0.060292 # miss rate for overall accesses 1075system.cpu.l2cache.overall_miss_rate::total 0.062152 # miss rate for overall accesses 1076system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 700 # average UpgradeReq miss latency 1077system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 700 # average UpgradeReq miss latency 1078system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95329.558881 # average ReadExReq miss latency 1079system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95329.558881 # average ReadExReq miss latency 1080system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74789.258669 # average ReadCleanReq miss latency 1081system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74789.258669 # average ReadCleanReq miss latency 1082system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77120.372786 # average ReadSharedReq miss latency 1083system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77120.372786 # average ReadSharedReq miss latency 1084system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74789.258669 # average overall miss latency 1085system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77664.640858 # average overall miss latency 1086system.cpu.l2cache.demand_avg_miss_latency::total 77504.257282 # average overall miss latency 1087system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74789.258669 # average overall miss latency 1088system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77664.640858 # average overall miss latency 1089system.cpu.l2cache.overall_avg_miss_latency::total 77504.257282 # average overall miss latency | 1070system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009900 # miss rate for ReadExReq accesses 1071system.cpu.l2cache.ReadExReq_miss_rate::total 0.009900 # miss rate for ReadExReq accesses 1072system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129193 # miss rate for ReadCleanReq accesses 1073system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129193 # miss rate for ReadCleanReq accesses 1074system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071819 # miss rate for ReadSharedReq accesses 1075system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071819 # miss rate for ReadSharedReq accesses 1076system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129193 # miss rate for demand accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.data 0.060348 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::total 0.062182 # miss rate for demand accesses 1079system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129193 # miss rate for overall accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.data 0.060348 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::total 0.062182 # miss rate for overall accesses 1082system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 759.259259 # average UpgradeReq miss latency 1083system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 759.259259 # average UpgradeReq miss latency 1084system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129372.871517 # average ReadExReq miss latency 1085system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129372.871517 # average ReadExReq miss latency 1086system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102196.657969 # average ReadCleanReq miss latency 1087system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102196.657969 # average ReadCleanReq miss latency 1088system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93225.371632 # average ReadSharedReq miss latency 1089system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93225.371632 # average ReadSharedReq miss latency 1090system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency 1091system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency 1092system.cpu.l2cache.demand_avg_miss_latency::total 94759.706243 # average overall miss latency 1093system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency 1094system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency 1095system.cpu.l2cache.overall_avg_miss_latency::total 94759.706243 # average overall miss latency |
| 1090system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1091system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1094system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1095system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1096system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1097system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1098system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1099system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1100system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1101system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1096system.cpu.l2cache.unused_prefetches 2029 # number of HardPF blocks evicted w/o reference 1097system.cpu.l2cache.writebacks::writebacks 291427 # number of writebacks 1098system.cpu.l2cache.writebacks::total 291427 # number of writebacks 1099system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1416 # number of ReadExReq MSHR hits 1100system.cpu.l2cache.ReadExReq_mshr_hits::total 1416 # number of ReadExReq MSHR hits | 1102system.cpu.l2cache.unused_prefetches 2063 # number of HardPF blocks evicted w/o reference 1103system.cpu.l2cache.writebacks::writebacks 291274 # number of writebacks 1104system.cpu.l2cache.writebacks::total 291274 # number of writebacks 1105system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1581 # number of ReadExReq MSHR hits 1106system.cpu.l2cache.ReadExReq_mshr_hits::total 1581 # number of ReadExReq MSHR hits |
| 1101system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits 1102system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits | 1107system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits 1108system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits |
| 1103system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4197 # number of ReadSharedReq MSHR hits 1104system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4197 # number of ReadSharedReq MSHR hits | 1109system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4441 # number of ReadSharedReq MSHR hits 1110system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4441 # number of ReadSharedReq MSHR hits |
| 1105system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits | 1111system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits |
| 1106system.cpu.l2cache.demand_mshr_hits::cpu.data 5613 # number of demand (read+write) MSHR hits 1107system.cpu.l2cache.demand_mshr_hits::total 5621 # number of demand (read+write) MSHR hits | 1112system.cpu.l2cache.demand_mshr_hits::cpu.data 6022 # number of demand (read+write) MSHR hits 1113system.cpu.l2cache.demand_mshr_hits::total 6030 # number of demand (read+write) MSHR hits |
| 1108system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits | 1114system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits |
| 1109system.cpu.l2cache.overall_mshr_hits::cpu.data 5613 # number of overall MSHR hits 1110system.cpu.l2cache.overall_mshr_hits::total 5621 # number of overall MSHR hits 1111system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356222 # number of HardPFReq MSHR misses 1112system.cpu.l2cache.HardPFReq_mshr_misses::total 356222 # number of HardPFReq MSHR misses 1113system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses 1114system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses 1115system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3662 # number of ReadExReq MSHR misses 1116system.cpu.l2cache.ReadExReq_mshr_misses::total 3662 # number of ReadExReq MSHR misses 1117system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10028 # number of ReadCleanReq MSHR misses 1118system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10028 # number of ReadCleanReq MSHR misses 1119system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160616 # number of ReadSharedReq MSHR misses 1120system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160616 # number of ReadSharedReq MSHR misses 1121system.cpu.l2cache.demand_mshr_misses::cpu.inst 10028 # number of demand (read+write) MSHR misses 1122system.cpu.l2cache.demand_mshr_misses::cpu.data 164278 # number of demand (read+write) MSHR misses 1123system.cpu.l2cache.demand_mshr_misses::total 174306 # number of demand (read+write) MSHR misses 1124system.cpu.l2cache.overall_mshr_misses::cpu.inst 10028 # number of overall MSHR misses 1125system.cpu.l2cache.overall_mshr_misses::cpu.data 164278 # number of overall MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356222 # number of overall MSHR misses 1127system.cpu.l2cache.overall_mshr_misses::total 530528 # number of overall MSHR misses 1128system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of HardPFReq MSHR miss cycles 1129system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18747915458 # number of HardPFReq MSHR miss cycles 1130system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 462000 # number of UpgradeReq MSHR miss cycles 1131system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 462000 # number of UpgradeReq MSHR miss cycles 1132system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 336888000 # number of ReadExReq MSHR miss cycles 1133system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 336888000 # number of ReadExReq MSHR miss cycles 1134system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 689794500 # number of ReadCleanReq MSHR miss cycles 1135system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 689794500 # number of ReadCleanReq MSHR miss cycles 1136system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11439165000 # number of ReadSharedReq MSHR miss cycles 1137system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11439165000 # number of ReadSharedReq MSHR miss cycles 1138system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689794500 # number of demand (read+write) MSHR miss cycles 1139system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11776053000 # number of demand (read+write) MSHR miss cycles 1140system.cpu.l2cache.demand_mshr_miss_latency::total 12465847500 # number of demand (read+write) MSHR miss cycles 1141system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689794500 # number of overall MSHR miss cycles 1142system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11776053000 # number of overall MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of overall MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::total 31213762958 # number of overall MSHR miss cycles | 1115system.cpu.l2cache.overall_mshr_hits::cpu.data 6022 # number of overall MSHR hits 1116system.cpu.l2cache.overall_mshr_hits::total 6030 # number of overall MSHR hits 1117system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355324 # number of HardPFReq MSHR misses 1118system.cpu.l2cache.HardPFReq_mshr_misses::total 355324 # number of HardPFReq MSHR misses 1119system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses 1120system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses 1121system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3587 # number of ReadExReq MSHR misses 1122system.cpu.l2cache.ReadExReq_mshr_misses::total 3587 # number of ReadExReq MSHR misses 1123system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9956 # number of ReadCleanReq MSHR misses 1124system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9956 # number of ReadCleanReq MSHR misses 1125system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160440 # number of ReadSharedReq MSHR misses 1126system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160440 # number of ReadSharedReq MSHR misses 1127system.cpu.l2cache.demand_mshr_misses::cpu.inst 9956 # number of demand (read+write) MSHR misses 1128system.cpu.l2cache.demand_mshr_misses::cpu.data 164027 # number of demand (read+write) MSHR misses 1129system.cpu.l2cache.demand_mshr_misses::total 173983 # number of demand (read+write) MSHR misses 1130system.cpu.l2cache.overall_mshr_misses::cpu.inst 9956 # number of overall MSHR misses 1131system.cpu.l2cache.overall_mshr_misses::cpu.data 164027 # number of overall MSHR misses 1132system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355324 # number of overall MSHR misses 1133system.cpu.l2cache.overall_mshr_misses::total 529307 # number of overall MSHR misses 1134system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of HardPFReq MSHR miss cycles 1135system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21295211595 # number of HardPFReq MSHR miss cycles 1136system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 417500 # number of UpgradeReq MSHR miss cycles 1137system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 417500 # number of UpgradeReq MSHR miss cycles 1138system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 461178500 # number of ReadExReq MSHR miss cycles 1139system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 461178500 # number of ReadExReq MSHR miss cycles 1140system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 956729500 # number of ReadCleanReq MSHR miss cycles 1141system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 956729500 # number of ReadCleanReq MSHR miss cycles 1142system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14002333000 # number of ReadSharedReq MSHR miss cycles 1143system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14002333000 # number of ReadSharedReq MSHR miss cycles 1144system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 956729500 # number of demand (read+write) MSHR miss cycles 1145system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14463511500 # number of demand (read+write) MSHR miss cycles 1146system.cpu.l2cache.demand_mshr_miss_latency::total 15420241000 # number of demand (read+write) MSHR miss cycles 1147system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 956729500 # number of overall MSHR miss cycles 1148system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14463511500 # number of overall MSHR miss cycles 1149system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of overall MSHR miss cycles 1150system.cpu.l2cache.overall_mshr_miss_latency::total 36715452595 # number of overall MSHR miss cycles |
| 1145system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1146system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1147system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1148system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1151system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1152system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1154system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1149system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007015 # mshr miss rate for ReadExReq accesses 1150system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007015 # mshr miss rate for ReadExReq accesses 1151system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for ReadCleanReq accesses 1152system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129991 # mshr miss rate for ReadCleanReq accesses 1153system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069961 # mshr miss rate for ReadSharedReq accesses 1154system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069961 # mshr miss rate for ReadSharedReq accesses 1155system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for demand accesses 1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for demand accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::total 0.060210 # mshr miss rate for demand accesses 1158system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for overall accesses 1159system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for overall accesses | 1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006871 # mshr miss rate for ReadExReq accesses 1156system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006871 # mshr miss rate for ReadExReq accesses 1157system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for ReadCleanReq accesses 1158system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129089 # mshr miss rate for ReadCleanReq accesses 1159system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069885 # mshr miss rate for ReadSharedReq accesses 1160system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069885 # mshr miss rate for ReadSharedReq accesses 1161system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for demand accesses 1162system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for demand accesses 1163system.cpu.l2cache.demand_mshr_miss_rate::total 0.060099 # mshr miss rate for demand accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for overall accesses 1165system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for overall accesses |
| 1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1166system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1161system.cpu.l2cache.overall_mshr_miss_rate::total 0.183259 # mshr miss rate for overall accesses 1162system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average HardPFReq mshr miss latency 1163system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124 # average HardPFReq mshr miss latency 1164system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15400 # average UpgradeReq mshr miss latency 1165system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15400 # average UpgradeReq mshr miss latency 1166system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803 # average ReadExReq mshr miss latency 1167system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803 # average ReadExReq mshr miss latency 1168system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829 # average ReadCleanReq mshr miss latency 1169system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829 # average ReadCleanReq mshr miss latency 1170system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009 # average ReadSharedReq mshr miss latency 1171system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009 # average ReadSharedReq mshr miss latency 1172system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency 1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395 # average overall mshr miss latency 1175system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114 # average overall mshr miss latency 1179system.cpu.toL2Bus.snoop_filter.tot_requests 5788969 # Total number of requests made to the snoop filter. 1180system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893984 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1181system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23717 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1182system.cpu.toL2Bus.snoop_filter.tot_snoops 99826 # Total number of snoops made to the snoop filter. 1183system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99825 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1167system.cpu.l2cache.overall_mshr_miss_rate::total 0.182839 # mshr miss rate for overall accesses 1168system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average HardPFReq mshr miss latency 1169system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204 # average HardPFReq mshr miss latency 1170system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963 # average UpgradeReq mshr miss latency 1171system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963 # average UpgradeReq mshr miss latency 1172system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340 # average ReadExReq mshr miss latency 1173system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340 # average ReadExReq mshr miss latency 1174system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394 # average ReadCleanReq mshr miss latency 1175system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394 # average ReadCleanReq mshr miss latency 1176system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166 # average ReadSharedReq mshr miss latency 1177system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166 # average ReadSharedReq mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency 1180system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average overall mshr miss latency 1184system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047 # average overall mshr miss latency 1185system.cpu.toL2Bus.snoop_filter.tot_requests 5788910 # Total number of requests made to the snoop filter. 1186system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893955 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1187system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23897 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1188system.cpu.toL2Bus.snoop_filter.tot_snoops 99240 # Total number of snoops made to the snoop filter. 1189system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1184system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1190system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1185system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 1186system.cpu.toL2Bus.trans_dist::ReadResp 2372984 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::WritebackDirty 2645368 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::WritebackClean 540001 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::CleanEvict 98976 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::HardPFReq 397627 # Transaction distribution | 1191system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 1192system.cpu.toL2Bus.trans_dist::ReadResp 2372941 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::WritebackDirty 2643074 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::WritebackClean 542116 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::CleanEvict 98320 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::HardPFReq 402261 # Transaction distribution |
| 1191system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution | 1197system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution |
| 1192system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::ReadExReq 522012 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::ReadExResp 522012 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::ReadCleanReq 77179 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295806 # Transaction distribution 1198system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230958 # Packet count per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453003 # Packet count per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_count::total 8683961 # Packet count per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9841856 # Cumulative packet size per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360648000 # Cumulative packet size per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size::total 370489856 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.snoops 788066 # Total snoops (count) 1205system.cpu.toL2Bus.snoopTraffic 18653632 # Total snoop traffic (bytes) 1206system.cpu.toL2Bus.snoop_fanout::samples 3683057 # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::mean 0.033555 # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::stdev 0.180083 # Request fanout histogram | 1198system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::ReadExReq 522025 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::ReadExResp 522025 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::ReadCleanReq 77158 # Transaction distribution 1203system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295784 # Transaction distribution 1204system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230901 # Packet count per connected master and slave (bytes) 1205system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452970 # Packet count per connected master and slave (bytes) 1206system.cpu.toL2Bus.pkt_count::total 8683871 # Packet count per connected master and slave (bytes) 1207system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839552 # Cumulative packet size per connected master and slave (bytes) 1208system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360646848 # Cumulative packet size per connected master and slave (bytes) 1209system.cpu.toL2Bus.pkt_size::total 370486400 # Cumulative packet size per connected master and slave (bytes) 1210system.cpu.toL2Bus.snoops 791889 # Total snoops (count) 1211system.cpu.toL2Bus.snoopTraffic 18643712 # Total snoop traffic (bytes) 1212system.cpu.toL2Bus.snoop_fanout::samples 3686849 # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::mean 0.033410 # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::stdev 0.179705 # Request fanout histogram |
| 1209system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1215system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1210system.cpu.toL2Bus.snoop_fanout::0 3559472 96.64% 96.64% # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::1 123584 3.36% 100.00% # Request fanout histogram | 1216system.cpu.toL2Bus.snoop_fanout::0 3563674 96.66% 96.66% # Request fanout histogram 1217system.cpu.toL2Bus.snoop_fanout::1 123174 3.34% 100.00% # Request fanout histogram |
| 1212system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1218system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1219system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1220system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1221system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1216system.cpu.toL2Bus.snoop_fanout::total 3683057 # Request fanout histogram 1217system.cpu.toL2Bus.reqLayer0.occupancy 5788426505 # Layer occupancy (ticks) | 1222system.cpu.toL2Bus.snoop_fanout::total 3686849 # Request fanout histogram 1223system.cpu.toL2Bus.reqLayer0.occupancy 5788371005 # Layer occupancy (ticks) |
| 1218system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 1219system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 1220system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1224system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 1225system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 1226system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1221system.cpu.toL2Bus.respLayer0.occupancy 115796940 # Layer occupancy (ticks) | 1227system.cpu.toL2Bus.respLayer0.occupancy 115765939 # Layer occupancy (ticks) |
| 1222system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1228system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1223system.cpu.toL2Bus.respLayer1.occupancy 4226763956 # Layer occupancy (ticks) | 1229system.cpu.toL2Bus.respLayer1.occupancy 4226743467 # Layer occupancy (ticks) |
| 1224system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) | 1230system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) |
| 1225system.membus.snoop_filter.tot_requests 821136 # Total number of requests made to the snoop filter. 1226system.membus.snoop_filter.hit_single_requests 414105 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1231system.membus.snoop_filter.tot_requests 819690 # Total number of requests made to the snoop filter. 1232system.membus.snoop_filter.hit_single_requests 413483 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1227system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1228system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1229system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1230system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1233system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1234system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1235system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1236system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1231system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states 1232system.membus.trans_dist::ReadResp 427040 # Transaction distribution 1233system.membus.trans_dist::WritebackDirty 291427 # Transaction distribution 1234system.membus.trans_dist::CleanEvict 98976 # Transaction distribution 1235system.membus.trans_dist::UpgradeReq 34 # Transaction distribution 1236system.membus.trans_dist::ReadExReq 3658 # Transaction distribution 1237system.membus.trans_dist::ReadExResp 3658 # Transaction distribution 1238system.membus.trans_dist::ReadSharedReq 427041 # Transaction distribution 1239system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251834 # Packet count per connected master and slave (bytes) 1240system.membus.pkt_count::total 1251834 # Packet count per connected master and slave (bytes) 1241system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46216000 # Cumulative packet size per connected master and slave (bytes) 1242system.membus.pkt_size::total 46216000 # Cumulative packet size per connected master and slave (bytes) | 1237system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states 1238system.membus.trans_dist::ReadResp 426481 # Transaction distribution 1239system.membus.trans_dist::WritebackDirty 291274 # Transaction distribution 1240system.membus.trans_dist::CleanEvict 98320 # Transaction distribution 1241system.membus.trans_dist::UpgradeReq 32 # Transaction distribution 1242system.membus.trans_dist::ReadExReq 3582 # Transaction distribution 1243system.membus.trans_dist::ReadExResp 3582 # Transaction distribution 1244system.membus.trans_dist::ReadSharedReq 426482 # Transaction distribution 1245system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1249753 # Packet count per connected master and slave (bytes) 1246system.membus.pkt_count::total 1249753 # Packet count per connected master and slave (bytes) 1247system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46165568 # Cumulative packet size per connected master and slave (bytes) 1248system.membus.pkt_size::total 46165568 # Cumulative packet size per connected master and slave (bytes) |
| 1243system.membus.snoops 0 # Total snoops (count) 1244system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1249system.membus.snoops 0 # Total snoops (count) 1250system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1245system.membus.snoop_fanout::samples 430733 # Request fanout histogram | 1251system.membus.snoop_fanout::samples 430096 # Request fanout histogram |
| 1246system.membus.snoop_fanout::mean 0 # Request fanout histogram 1247system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1248system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1252system.membus.snoop_fanout::mean 0 # Request fanout histogram 1253system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1254system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1249system.membus.snoop_fanout::0 430733 100.00% 100.00% # Request fanout histogram | 1255system.membus.snoop_fanout::0 430096 100.00% 100.00% # Request fanout histogram |
| 1250system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1251system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1252system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1253system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1256system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1257system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1258system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1259system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1254system.membus.snoop_fanout::total 430733 # Request fanout histogram 1255system.membus.reqLayer0.occupancy 2217216132 # Layer occupancy (ticks) 1256system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) 1257system.membus.respLayer1.occupancy 2280002282 # Layer occupancy (ticks) | 1260system.membus.snoop_fanout::total 430096 # Request fanout histogram 1261system.membus.reqLayer0.occupancy 2210866206 # Layer occupancy (ticks) 1262system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 1263system.membus.respLayer1.occupancy 2276438586 # Layer occupancy (ticks) |
| 1258system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 1259 1260---------- End Simulation Statistics ---------- | 1264system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 1265 1266---------- End Simulation Statistics ---------- |