| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.232865 # Number of seconds simulated 4sim_ticks 232864525000 # Number of ticks simulated 5final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.232865 # Number of seconds simulated 4sim_ticks 232864525000 # Number of ticks simulated 5final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 230904 # Simulator instruction rate (inst/s) 8host_op_rate 250150 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 106424359 # Simulator tick rate (ticks/s) 10host_mem_usage 342436 # Number of bytes of host memory used 11host_seconds 2188.08 # Real time elapsed on the host | 7host_inst_rate 221507 # Simulator instruction rate (inst/s) 8host_op_rate 239970 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 102093126 # Simulator tick rate (ticks/s) 10host_mem_usage 343096 # Number of bytes of host memory used 11host_seconds 2280.90 # Real time elapsed on the host |
| 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory --- 264 unchanged lines hidden (view full) --- 288system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) 289system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) 290system.physmem_1.averagePower 725.972811 # Core power per rank (mW) 291system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states 292system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states 293system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 294system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states 295system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory 20system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory 24system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory --- 264 unchanged lines hidden (view full) --- 289system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) 290system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) 291system.physmem_1.averagePower 725.972811 # Core power per rank (mW) 292system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states 293system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states 294system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 295system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states 296system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 297system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 296system.cpu.branchPred.lookups 174583649 # Number of BP lookups 297system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 302system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage 303system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. 305system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. 306system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. 307system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. 308system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. 309system.cpu_clk_domain.clock 500 # Clock period in ticks | 298system.cpu.branchPred.lookups 174583649 # Number of BP lookups 299system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted 300system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect 301system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups 302system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits 303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 304system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage 305system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. 306system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. 307system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. 308system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. 309system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. 310system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. 311system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 312system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 310system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 334system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 335system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 336system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 337system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 338system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 313system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 334system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 335system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 336system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 337system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 338system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 339system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 340system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 341system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 342system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 339system.cpu.dtb.walker.walks 0 # Table walker walks requested 340system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 360system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.dtb.read_accesses 0 # DTB read accesses 363system.cpu.dtb.write_accesses 0 # DTB write accesses 364system.cpu.dtb.inst_accesses 0 # ITB inst accesses 365system.cpu.dtb.hits 0 # DTB hits 366system.cpu.dtb.misses 0 # DTB misses 367system.cpu.dtb.accesses 0 # DTB accesses | 343system.cpu.dtb.walker.walks 0 # Table walker walks requested 344system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 364system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.dtb.read_accesses 0 # DTB read accesses 367system.cpu.dtb.write_accesses 0 # DTB write accesses 368system.cpu.dtb.inst_accesses 0 # ITB inst accesses 369system.cpu.dtb.hits 0 # DTB hits 370system.cpu.dtb.misses 0 # DTB misses 371system.cpu.dtb.accesses 0 # DTB accesses |
| 372system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 368system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 389system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 390system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 391system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 392system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 393system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 394system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 395system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 396system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 373system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 394system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 402system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 397system.cpu.itb.walker.walks 0 # Table walker walks requested 398system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 419system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 420system.cpu.itb.read_accesses 0 # DTB read accesses 421system.cpu.itb.write_accesses 0 # DTB write accesses 422system.cpu.itb.inst_accesses 0 # ITB inst accesses 423system.cpu.itb.hits 0 # DTB hits 424system.cpu.itb.misses 0 # DTB misses 425system.cpu.itb.accesses 0 # DTB accesses 426system.cpu.workload.num_syscalls 548 # Number of system calls | 403system.cpu.itb.walker.walks 0 # Table walker walks requested 404system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 425system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 426system.cpu.itb.read_accesses 0 # DTB read accesses 427system.cpu.itb.write_accesses 0 # DTB write accesses 428system.cpu.itb.inst_accesses 0 # ITB inst accesses 429system.cpu.itb.hits 0 # DTB hits 430system.cpu.itb.misses 0 # DTB misses 431system.cpu.itb.accesses 0 # DTB accesses 432system.cpu.workload.num_syscalls 548 # Number of system calls |
| 433system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states |
|
| 427system.cpu.numCycles 465729051 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 708system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads 709system.cpu.int_regfile_reads 610135542 # number of integer regfile reads 710system.cpu.int_regfile_writes 327337405 # number of integer regfile writes 711system.cpu.fp_regfile_reads 16 # number of floating regfile reads 712system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads 713system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes 714system.cpu.misc_regfile_reads 217603177 # number of misc regfile reads 715system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes | 434system.cpu.numCycles 465729051 # number of cpu cycles simulated 435system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 436system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 437system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss 438system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed 439system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered 440system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken 441system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 715system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads 716system.cpu.int_regfile_reads 610135542 # number of integer regfile reads 717system.cpu.int_regfile_writes 327337405 # number of integer regfile writes 718system.cpu.fp_regfile_reads 16 # number of floating regfile reads 719system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads 720system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes 721system.cpu.misc_regfile_reads 217603177 # number of misc regfile reads 722system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes |
| 723system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 716system.cpu.dcache.tags.replacements 2817145 # number of replacements 717system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use 718system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. 719system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. 720system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. 721system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. 722system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor 723system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy 724system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy 725system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 726system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 727system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 728system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 729system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 730system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses 731system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses | 724system.cpu.dcache.tags.replacements 2817145 # number of replacements 725system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use 726system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. 727system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. 728system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. 729system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. 730system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor 731system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy 732system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy 733system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 734system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 735system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 736system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 737system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 738system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses 739system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses |
| 740system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 732system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits 733system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits 734system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits 735system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits 736system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits 737system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits 738system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits 739system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits --- 114 unchanged lines hidden (view full) --- 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency 857system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency | 741system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits 742system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits 743system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits 744system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits 745system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits 746system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits 747system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits 748system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits --- 114 unchanged lines hidden (view full) --- 863system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency 865system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency 866system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency 868system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency 870system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency |
| 871system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 862system.cpu.icache.tags.replacements 76528 # number of replacements 863system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use 864system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. 865system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. 866system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. 867system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. 868system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor 869system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy 870system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy 871system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 872system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 873system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 877system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 878system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses 879system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses | 872system.cpu.icache.tags.replacements 76528 # number of replacements 873system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use 874system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. 875system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. 876system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. 877system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. 878system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor 879system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy 880system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy 881system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 883system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 884system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 885system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 887system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 888system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses 889system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses |
| 890system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 880system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits 881system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits 882system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits 883system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits 884system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits 885system.cpu.icache.overall_hits::total 235186472 # number of overall hits 886system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses 887system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency | 891system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits 892system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits 893system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits 894system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits 895system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits 896system.cpu.icache.overall_hits::total 235186472 # number of overall hits 897system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses 898system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 957system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 958system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses 959system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency 960system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency 961system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 962system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 963system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 964system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency |
| 965system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 954system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued 955system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified 956system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue 957system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 958system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 959system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing | 966system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued 967system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified 968system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue 969system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 970system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 971system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing |
| 972system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 960system.cpu.l2cache.tags.replacements 395630 # number of replacements 961system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use 962system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. 963system.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. 964system.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. 965system.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. 966system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor 967system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor --- 12 unchanged lines hidden (view full) --- 980system.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id 984system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id 985system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id 986system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses 987system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses | 973system.cpu.l2cache.tags.replacements 395630 # number of replacements 974system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use 975system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. 976system.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. 977system.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. 978system.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. 979system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor --- 12 unchanged lines hidden (view full) --- 993system.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id 997system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id 998system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id 999system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses 1000system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses |
| 1001system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 988system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits 989system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits 990system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits 991system.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits 992system.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits 993system.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits 994system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits 995system.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits --- 169 unchanged lines hidden (view full) --- 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency 1167system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. 1168system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1169system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1170system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. 1171system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1172system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1002system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits 1003system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits 1004system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits 1005system.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits 1006system.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits 1007system.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits 1008system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits 1009system.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits --- 169 unchanged lines hidden (view full) --- 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency 1181system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1187system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 1173system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 1203system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) 1204system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 1205system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 1206system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1207system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) 1208system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1209system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) 1210system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) | 1188system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 1218system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) 1219system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 1220system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 1221system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1222system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) 1223system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1224system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) 1225system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) |
| 1226system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states |
|
| 1211system.membus.trans_dist::ReadResp 420223 # Transaction distribution 1212system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution 1213system.membus.trans_dist::CleanEvict 98859 # Transaction distribution 1214system.membus.trans_dist::UpgradeReq 33 # Transaction distribution 1215system.membus.trans_dist::ReadExReq 3697 # Transaction distribution 1216system.membus.trans_dist::ReadExResp 3697 # Transaction distribution 1217system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution 1218system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 1227system.membus.trans_dist::ReadResp 420223 # Transaction distribution 1228system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution 1229system.membus.trans_dist::CleanEvict 98859 # Transaction distribution 1230system.membus.trans_dist::UpgradeReq 33 # Transaction distribution 1231system.membus.trans_dist::ReadExReq 3697 # Transaction distribution 1232system.membus.trans_dist::ReadExResp 3697 # Transaction distribution 1233system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution 1234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- |