| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.232865 # Number of seconds simulated 4sim_ticks 232864525000 # Number of ticks simulated 5final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.232865 # Number of seconds simulated 4sim_ticks 232864525000 # Number of ticks simulated 5final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 164421 # Simulator instruction rate (inst/s) 8host_op_rate 178126 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 75782118 # Simulator tick rate (ticks/s) 10host_mem_usage 300244 # Number of bytes of host memory used 11host_seconds 3072.82 # Real time elapsed on the host | 7host_inst_rate 163970 # Simulator instruction rate (inst/s) 8host_op_rate 177638 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 75574513 # Simulator tick rate (ticks/s) 10host_mem_usage 300240 # Number of bytes of host memory used 11host_seconds 3081.26 # Real time elapsed on the host |
| 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory --- 782 unchanged lines hidden (view full) --- 802system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency 803system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency 804system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked 805system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked 806system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 807system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked 809system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked | 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory --- 782 unchanged lines hidden (view full) --- 802system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency 803system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency 804system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked 805system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked 806system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 807system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked 809system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked |
| 810system.cpu.dcache.fast_writes 0 # number of fast writes performed 811system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 812system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks 813system.cpu.dcache.writebacks::total 2817145 # number of writebacks 814system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits 815system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits 816system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits 817system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits 818system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 819system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency 857system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency 858system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency 859system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency 860system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency 861system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency 862system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency 863system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency | 810system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks 811system.cpu.dcache.writebacks::total 2817145 # number of writebacks 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 817system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency 857system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency |
| 864system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 865system.cpu.icache.tags.replacements 76528 # number of replacements 866system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use 867system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. 868system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. 869system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. 870system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. 871system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor 872system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 917system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency 918system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency 919system.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked 920system.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked 921system.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked 922system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked 923system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked 924system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked | 862system.cpu.icache.tags.replacements 76528 # number of replacements 863system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use 864system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. 865system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. 866system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. 867system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. 868system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor 869system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 914system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency 916system.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked 917system.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked 918system.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked 919system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked 920system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked 921system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked |
| 925system.cpu.icache.fast_writes 0 # number of fast writes performed 926system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 927system.cpu.icache.writebacks::writebacks 76528 # number of writebacks 928system.cpu.icache.writebacks::total 76528 # number of writebacks 929system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits 930system.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits 931system.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits 932system.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits 933system.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits 934system.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 951system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 952system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses 953system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency 954system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency 955system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 956system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 957system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 958system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency | 922system.cpu.icache.writebacks::writebacks 76528 # number of writebacks 923system.cpu.icache.writebacks::total 76528 # number of writebacks 924system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits 925system.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits 926system.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits 927system.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits 928system.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits 929system.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency |
| 959system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 960system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued 961system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified 962system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue 963system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 964system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 965system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing 966system.cpu.l2cache.tags.replacements 395630 # number of replacements 967system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use --- 114 unchanged lines hidden (view full) --- 1082system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency 1083system.cpu.l2cache.overall_avg_miss_latency::total 76495.483414 # average overall miss latency 1084system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1085system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1086system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1087system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1088system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1089system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 954system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued 955system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified 956system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue 957system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 958system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 959system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing 960system.cpu.l2cache.tags.replacements 395630 # number of replacements 961system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use --- 114 unchanged lines hidden (view full) --- 1076system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency 1077system.cpu.l2cache.overall_avg_miss_latency::total 76495.483414 # average overall miss latency 1078system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1090system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1091system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1092system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference 1093system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks 1094system.cpu.l2cache.writebacks::total 292354 # number of writebacks 1095system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1396 # number of ReadExReq MSHR hits 1096system.cpu.l2cache.ReadExReq_mshr_hits::total 1396 # number of ReadExReq MSHR hits 1097system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits 1098system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 1099system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4126 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1167system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency 1168system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 1169system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 1170system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency 1171system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 1172system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 1173system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency 1174system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency | 1084system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference 1085system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks 1086system.cpu.l2cache.writebacks::total 292354 # number of writebacks 1087system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1396 # number of ReadExReq MSHR hits 1088system.cpu.l2cache.ReadExReq_mshr_hits::total 1396 # number of ReadExReq MSHR hits 1089system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits 1090system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 1091system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4126 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1159system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency |
| 1175system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1176system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. 1177system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1178system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1179system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. 1180system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1181system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1182system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution --- 64 unchanged lines hidden --- | 1167system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. 1168system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1169system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1170system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. 1171system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1172system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1173system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution --- 64 unchanged lines hidden --- |