| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.233382 # Number of seconds simulated 4sim_ticks 233381523500 # Number of ticks simulated 5final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 139639 # Simulator instruction rate (inst/s) 8host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) --- 672 unchanged lines hidden (view full) --- 681system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 683system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 684system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction 688system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.233382 # Number of seconds simulated 4sim_ticks 233381523500 # Number of ticks simulated 5final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 139639 # Simulator instruction rate (inst/s) 8host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) --- 672 unchanged lines hidden (view full) --- 681system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 683system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 684system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction 688system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached |
| 689system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 690system.cpu.rob.rob_reads 1093653497 # The number of ROB reads 691system.cpu.rob.rob_writes 1334601058 # The number of ROB writes 692system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself 693system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling 694system.cpu.committedInsts 505237723 # Number of Instructions Simulated 695system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated 696system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction 697system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads --- 513 unchanged lines hidden --- | 689system.cpu.rob.rob_reads 1093653497 # The number of ROB reads 690system.cpu.rob.rob_writes 1334601058 # The number of ROB writes 691system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself 692system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling 693system.cpu.committedInsts 505237723 # Number of Instructions Simulated 694system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated 695system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction 696system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads --- 513 unchanged lines hidden --- |