| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.231519 # Number of seconds simulated 4sim_ticks 231518815500 # Number of ticks simulated 5final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.232212 # Number of seconds simulated 4sim_ticks 232211555000 # Number of ticks simulated 5final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 137569 # Simulator instruction rate (inst/s) 8host_op_rate 149036 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63039200 # Simulator tick rate (ticks/s) 10host_mem_usage 324016 # Number of bytes of host memory used 11host_seconds 3672.62 # Real time elapsed on the host | 7host_inst_rate 135087 # Simulator instruction rate (inst/s) 8host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62087234 # Simulator tick rate (ticks/s) 10host_mem_usage 317808 # Number of bytes of host memory used 11host_seconds 3740.09 # Real time elapsed on the host |
| 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 547350944 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 547350944 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory 23system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 448618 # Number of read requests accepted 44system.physmem.writeReqs 303849 # Number of write requests accepted 45system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue 49system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 412658 # Number of read requests accepted 44system.physmem.writeReqs 292638 # Number of write requests accepted 45system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue 49system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one | 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one |
| 54system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 28534 # Per bank write bursts 56system.physmem.perBankRdBursts::1 27313 # Per bank write bursts 57system.physmem.perBankRdBursts::2 27956 # Per bank write bursts 58system.physmem.perBankRdBursts::3 26702 # Per bank write bursts 59system.physmem.perBankRdBursts::4 30075 # Per bank write bursts 60system.physmem.perBankRdBursts::5 29207 # Per bank write bursts 61system.physmem.perBankRdBursts::6 27700 # Per bank write bursts 62system.physmem.perBankRdBursts::7 26438 # Per bank write bursts 63system.physmem.perBankRdBursts::8 28442 # Per bank write bursts 64system.physmem.perBankRdBursts::9 26796 # Per bank write bursts 65system.physmem.perBankRdBursts::10 28037 # Per bank write bursts 66system.physmem.perBankRdBursts::11 28667 # Per bank write bursts 67system.physmem.perBankRdBursts::12 28663 # Per bank write bursts 68system.physmem.perBankRdBursts::13 27984 # Per bank write bursts 69system.physmem.perBankRdBursts::14 26659 # Per bank write bursts 70system.physmem.perBankRdBursts::15 27067 # Per bank write bursts 71system.physmem.perBankWrBursts::0 19504 # Per bank write bursts 72system.physmem.perBankWrBursts::1 19011 # Per bank write bursts 73system.physmem.perBankWrBursts::2 18881 # Per bank write bursts 74system.physmem.perBankWrBursts::3 18629 # Per bank write bursts 75system.physmem.perBankWrBursts::4 19556 # Per bank write bursts 76system.physmem.perBankWrBursts::5 19014 # Per bank write bursts 77system.physmem.perBankWrBursts::6 18738 # Per bank write bursts 78system.physmem.perBankWrBursts::7 18227 # Per bank write bursts 79system.physmem.perBankWrBursts::8 18808 # Per bank write bursts 80system.physmem.perBankWrBursts::9 18381 # Per bank write bursts 81system.physmem.perBankWrBursts::10 19036 # Per bank write bursts 82system.physmem.perBankWrBursts::11 19525 # Per bank write bursts 83system.physmem.perBankWrBursts::12 19578 # Per bank write bursts 84system.physmem.perBankWrBursts::13 19080 # Per bank write bursts 85system.physmem.perBankWrBursts::14 18969 # Per bank write bursts 86system.physmem.perBankWrBursts::15 18884 # Per bank write bursts | 54system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 26576 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25575 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25174 # Per bank write bursts 58system.physmem.perBankRdBursts::3 24876 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27202 # Per bank write bursts 60system.physmem.perBankRdBursts::5 26589 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25428 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24234 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25846 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24812 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25055 # Per bank write bursts 66system.physmem.perBankRdBursts::11 26081 # Per bank write bursts 67system.physmem.perBankRdBursts::12 26502 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25872 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25198 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25467 # Per bank write bursts 71system.physmem.perBankWrBursts::0 18795 # Per bank write bursts 72system.physmem.perBankWrBursts::1 18343 # Per bank write bursts 73system.physmem.perBankWrBursts::2 17877 # Per bank write bursts 74system.physmem.perBankWrBursts::3 18076 # Per bank write bursts 75system.physmem.perBankWrBursts::4 18802 # Per bank write bursts 76system.physmem.perBankWrBursts::5 18306 # Per bank write bursts 77system.physmem.perBankWrBursts::6 18071 # Per bank write bursts 78system.physmem.perBankWrBursts::7 17638 # Per bank write bursts 79system.physmem.perBankWrBursts::8 18138 # Per bank write bursts 80system.physmem.perBankWrBursts::9 17849 # Per bank write bursts 81system.physmem.perBankWrBursts::10 18079 # Per bank write bursts 82system.physmem.perBankWrBursts::11 18708 # Per bank write bursts 83system.physmem.perBankWrBursts::12 18879 # Per bank write bursts 84system.physmem.perBankWrBursts::13 18261 # Per bank write bursts 85system.physmem.perBankWrBursts::14 18465 # Per bank write bursts 86system.physmem.perBankWrBursts::15 18329 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 89system.physmem.totGap 231518762500 # Total gap between requests | 89system.physmem.totGap 232211534500 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 448618 # Read request sizes (log2) | 96system.physmem.readPktSize::6 412658 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 303849 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 292638 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 200system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads 238system.physmem.totQLat 10651839911 # Total ticks spent queuing 239system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst | 200system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads 237system.physmem.totQLat 9526506707 # Total ticks spent queuing 238system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM 239system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers 240system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst |
| 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 243system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s | 242system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst 243system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s |
| 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 249system.physmem.busUtil 1.62 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing 254system.physmem.readRowHits 331076 # Number of row buffer hits during reads 255system.physmem.writeRowHits 99609 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes 258system.physmem.avgGap 307679.62 # Average gap between requests 259system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined 260system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states 261system.physmem.memoryStateTime::REF 7730840000 # Time in different power states 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.physmem.actEnergy::0 1204270200 # Energy for activate commands per rank (pJ) 266system.physmem.actEnergy::1 1209705840 # Energy for activate commands per rank (pJ) 267system.physmem.preEnergy::0 657091875 # Energy for precharge commands per rank (pJ) 268system.physmem.preEnergy::1 660057750 # Energy for precharge commands per rank (pJ) 269system.physmem.readEnergy::0 1746123600 # Energy for read commands per rank (pJ) 270system.physmem.readEnergy::1 1733674800 # Energy for read commands per rank (pJ) 271system.physmem.writeEnergy::0 981894960 # Energy for write commands per rank (pJ) 272system.physmem.writeEnergy::1 986450400 # Energy for write commands per rank (pJ) 273system.physmem.refreshEnergy::0 15121523040 # Energy for refresh commands per rank (pJ) 274system.physmem.refreshEnergy::1 15121523040 # Energy for refresh commands per rank (pJ) 275system.physmem.actBackEnergy::0 75885673770 # Energy for active background per rank (pJ) 276system.physmem.actBackEnergy::1 75815795475 # Energy for active background per rank (pJ) 277system.physmem.preBackEnergy::0 72343590000 # Energy for precharge background per rank (pJ) 278system.physmem.preBackEnergy::1 72404886750 # Energy for precharge background per rank (pJ) 279system.physmem.totalEnergy::0 167940167445 # Total energy per rank (pJ) 280system.physmem.totalEnergy::1 167932094055 # Total energy per rank (pJ) 281system.physmem.averagePower::0 725.391418 # Core power per rank (mW) 282system.physmem.averagePower::1 725.356546 # Core power per rank (mW) 283system.membus.trans_dist::ReadReq 445006 # Transaction distribution 284system.membus.trans_dist::ReadResp 445005 # Transaction distribution 285system.membus.trans_dist::Writeback 303849 # Transaction distribution 286system.membus.trans_dist::UpgradeReq 4 # Transaction distribution 287system.membus.trans_dist::UpgradeResp 4 # Transaction distribution 288system.membus.trans_dist::ReadExReq 3612 # Transaction distribution 289system.membus.trans_dist::ReadExResp 3612 # Transaction distribution 290system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) 291system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) 292system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) 293system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) 294system.membus.snoops 0 # Total snoops (count) 295system.membus.snoop_fanout::samples 752471 # Request fanout histogram 296system.membus.snoop_fanout::mean 0 # Request fanout histogram 297system.membus.snoop_fanout::stdev 0 # Request fanout histogram 298system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 299system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram 300system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 301system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 302system.membus.snoop_fanout::min_value 0 # Request fanout histogram 303system.membus.snoop_fanout::max_value 0 # Request fanout histogram 304system.membus.snoop_fanout::total 752471 # Request fanout histogram 305system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) 306system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 307system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) 308system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 309system.cpu_clk_domain.clock 500 # Clock period in ticks 310system.cpu.branchPred.lookups 175071152 # Number of BP lookups 311system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted 312system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect 313system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups 314system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits | 248system.physmem.busUtil 1.51 # Data bus utilization in percentage 249system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing 253system.physmem.readRowHits 299737 # Number of row buffer hits during reads 254system.physmem.writeRowHits 95481 # Number of row buffer hits during writes 255system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes 257system.physmem.avgGap 329239.83 # Average gap between requests 258system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined 259system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) 261system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) 263system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) 266system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) 267system.physmem_0.averagePower 723.427350 # Core power per rank (mW) 268system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states 269system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states 270system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states 272system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) 274system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) 275system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) 276system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) 277system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) 278system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) 279system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) 281system.physmem_1.averagePower 723.098525 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states 283system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.cpu.branchPred.lookups 175052211 # Number of BP lookups 288system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits |
| 315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 316system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage 317system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. 318system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. | 293system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. 296system.cpu_clk_domain.clock 500 # Clock period in ticks 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| 319system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 320system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 321system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 322system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 323system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 324system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 325system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 332system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 333system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 334system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 335system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 336system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 337system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 338system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 339system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 305system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 306system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 307system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 308system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 309system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 310system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 326system.cpu.dtb.walker.walks 0 # Table walker walks requested 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 340system.cpu.dtb.inst_hits 0 # ITB inst hits 341system.cpu.dtb.inst_misses 0 # ITB inst misses 342system.cpu.dtb.read_hits 0 # DTB read hits 343system.cpu.dtb.read_misses 0 # DTB read misses 344system.cpu.dtb.write_hits 0 # DTB write hits 345system.cpu.dtb.write_misses 0 # DTB write misses 346system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses | 334system.cpu.dtb.inst_hits 0 # ITB inst hits 335system.cpu.dtb.inst_misses 0 # ITB inst misses 336system.cpu.dtb.read_hits 0 # DTB read hits 337system.cpu.dtb.read_misses 0 # DTB read misses 338system.cpu.dtb.write_hits 0 # DTB write hits 339system.cpu.dtb.write_misses 0 # DTB write misses 340system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 341system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 347system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 348system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 349system.cpu.dtb.read_accesses 0 # DTB read accesses 350system.cpu.dtb.write_accesses 0 # DTB write accesses 351system.cpu.dtb.inst_accesses 0 # ITB inst accesses 352system.cpu.dtb.hits 0 # DTB hits 353system.cpu.dtb.misses 0 # DTB misses 354system.cpu.dtb.accesses 0 # DTB accesses |
| 355system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 361system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 362system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 363system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 364system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 365system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 366system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 367system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 374system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 377system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 378system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 379system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 380system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 381system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 363system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 364system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 365system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 366system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 367system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 368system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 376system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 384system.cpu.itb.walker.walks 0 # Table walker walks requested 385system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 382system.cpu.itb.inst_hits 0 # ITB inst hits 383system.cpu.itb.inst_misses 0 # ITB inst misses 384system.cpu.itb.read_hits 0 # DTB read hits 385system.cpu.itb.read_misses 0 # DTB read misses 386system.cpu.itb.write_hits 0 # DTB write hits 387system.cpu.itb.write_misses 0 # DTB write misses 388system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 389system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses 403system.cpu.workload.num_syscalls 548 # Number of system calls | 392system.cpu.itb.inst_hits 0 # ITB inst hits 393system.cpu.itb.inst_misses 0 # ITB inst misses 394system.cpu.itb.read_hits 0 # DTB read hits 395system.cpu.itb.read_misses 0 # DTB read misses 396system.cpu.itb.write_hits 0 # DTB write hits 397system.cpu.itb.write_misses 0 # DTB write misses 398system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 406system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu.itb.read_accesses 0 # DTB read accesses 408system.cpu.itb.write_accesses 0 # DTB write accesses 409system.cpu.itb.inst_accesses 0 # ITB inst accesses 410system.cpu.itb.hits 0 # DTB hits 411system.cpu.itb.misses 0 # DTB misses 412system.cpu.itb.accesses 0 # DTB accesses 413system.cpu.workload.num_syscalls 548 # Number of system calls |
| 404system.cpu.numCycles 463037632 # number of cpu cycles simulated | 414system.cpu.numCycles 464423111 # number of cpu cycles simulated |
| 405system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 406system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 415system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 416system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 407system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss 408system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed 409system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered 410system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken 411system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked 412system.cpu.fetch.SquashCycles 14941835 # Number of cycles fetch has spent squashing 413system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 414system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps 415system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR 416system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched 417system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed 418system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) | 417system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss 418system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed 419system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered 420system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken 421system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked 422system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing 423system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 424system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps 425system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR 426system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched 427system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed 428system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) |
| 421system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 431system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 422system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) | 432system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) |
| 426system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 436system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 429system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle 431system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle 432system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle 433system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked 434system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running 435system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking 436system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing 437system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch 438system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction 439system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode 440system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode 441system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing 442system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle 443system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking 444system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst 445system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running 446system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking 447system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename 448system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename 449system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full 450system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full 451system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full 452system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full 453system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed 454system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made 455system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups | 439system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle 441system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle 442system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle 443system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked 444system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running 445system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking 446system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing 447system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch 448system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction 449system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode 450system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode 451system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing 452system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle 453system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking 454system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst 455system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running 456system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking 457system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename 458system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename 459system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full 460system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full 461system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full 462system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full 463system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed 464system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made 465system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups |
| 456system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 457system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed | 466system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 467system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed |
| 458system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing 459system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed 460system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed 461system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer 462system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. 463system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. 464system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. 465system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. 466system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) 467system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ 468system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued 469system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued 470system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling 471system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph 472system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed 473system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle | 468system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing 469system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed 470system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed 471system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer 472system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. 473system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. 474system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. 475system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. 476system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) 477system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ 478system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued 479system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued 480system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling 481system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph 482system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed 483system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle |
| 476system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 486system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 477system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle | 487system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle |
| 483system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 493system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 489system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle | 499system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle |
| 490system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 500system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 491system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available 492system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available 494system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available 520system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available 521system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available | 501system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available 502system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available 503system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available 504system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available 530system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available 531system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available |
| 522system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 523system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 524system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 532system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 533system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 534system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 525system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued 526system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued | 535system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued 536system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued |
| 527system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 528system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 529system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 546system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued | 537system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 556system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued |
| 554system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued 555system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued | 564system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued 565system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued |
| 556system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 557system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 566system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 567system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 558system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued 559system.cpu.iq.rate 1.317880 # Inst issue rate 560system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested 561system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) 562system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads 563system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes 564system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses | 568system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued 569system.cpu.iq.rate 1.313932 # Inst issue rate 570system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested 571system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) 572system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads 573system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes 574system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses |
| 565system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 566system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 567system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 575system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 576system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 577system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 568system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses | 578system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses |
| 569system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses | 579system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses |
| 570system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores | 580system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores |
| 571system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 581system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 572system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed 573system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed 574system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations 575system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed | 582system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed 583system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed 584system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations 585system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed |
| 576system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 577system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 586system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 587system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 578system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled 579system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked | 588system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled 589system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked |
| 580system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 590system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 581system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing 582system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking 583system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking 584system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ | 591system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing 592system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking 593system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking 594system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ |
| 585system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 595system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 586system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions 587system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions 588system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions 589system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall 590system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall 591system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations 592system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly 593system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly 594system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute 595system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions 596system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed 597system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute | 596system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions 597system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions 598system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions 599system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall 600system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall 601system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations 602system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly 603system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly 604system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute 605system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions 606system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed 607system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute |
| 598system.cpu.iew.exec_swp 0 # number of swp insts executed | 608system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 599system.cpu.iew.exec_nop 1486621 # number of nop insts executed 600system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed 601system.cpu.iew.exec_branches 131372634 # Number of branches executed 602system.cpu.iew.exec_stores 60949141 # Number of stores executed 603system.cpu.iew.exec_rate 1.294450 # Inst execution rate 604system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit 605system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back 606system.cpu.iew.wb_producers 349881958 # num instructions producing a value 607system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value | 609system.cpu.iew.exec_nop 1486524 # number of nop insts executed 610system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed 611system.cpu.iew.exec_branches 131371292 # Number of branches executed 612system.cpu.iew.exec_stores 60952468 # Number of stores executed 613system.cpu.iew.exec_rate 1.290583 # Inst execution rate 614system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit 615system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back 616system.cpu.iew.wb_producers 349870966 # num instructions producing a value 617system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value |
| 608system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 618system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 609system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle 610system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back | 619system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle 620system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back |
| 611system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 621system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 612system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit | 622system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit |
| 613system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards | 623system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards |
| 614system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted 615system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle | 624system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted 625system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle |
| 618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 628system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 619system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle | 629system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle |
| 628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 638system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 631system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle | 641system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle |
| 632system.cpu.commit.committedInsts 506581607 # Number of instructions committed 633system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed 634system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 635system.cpu.commit.refs 172745233 # Number of memory references committed 636system.cpu.commit.loads 115884756 # Number of loads committed 637system.cpu.commit.membars 1488542 # Number of memory barriers committed 638system.cpu.commit.branches 121548301 # Number of branches committed 639system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 669system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 672system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 673system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 674system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction | 642system.cpu.commit.committedInsts 506581607 # Number of instructions committed 643system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed 644system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 645system.cpu.commit.refs 172745233 # Number of memory references committed 646system.cpu.commit.loads 115884756 # Number of loads committed 647system.cpu.commit.membars 1488542 # Number of memory barriers committed 648system.cpu.commit.branches 121548301 # Number of branches committed 649system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 679system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 682system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 683system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 684system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction |
| 677system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached | 687system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached |
| 678system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 688system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 679system.cpu.rob.rob_reads 1090469902 # The number of ROB reads 680system.cpu.rob.rob_writes 1334452492 # The number of ROB writes 681system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself 682system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling | 689system.cpu.rob.rob_reads 1091332417 # The number of ROB reads 690system.cpu.rob.rob_writes 1334357175 # The number of ROB writes 691system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself 692system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 683system.cpu.committedInsts 505237723 # Number of Instructions Simulated 684system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated | 693system.cpu.committedInsts 505237723 # Number of Instructions Simulated 694system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated |
| 685system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction 686system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads 687system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle 688system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads 689system.cpu.int_regfile_reads 611059162 # number of integer regfile reads 690system.cpu.int_regfile_writes 328109228 # number of integer regfile writes | 695system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction 696system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads 697system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle 698system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads 699system.cpu.int_regfile_reads 611063177 # number of integer regfile reads 700system.cpu.int_regfile_writes 328106532 # number of integer regfile writes |
| 691system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 701system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 692system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads 693system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes 694system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads | 702system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads 703system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes 704system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads |
| 695system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes | 705system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes |
| 696system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution 697system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution 698system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution 699system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution 700system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 701system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution 702system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution 704system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution 705system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) 706system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) 708system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) 709system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) 710system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) 711system.cpu.toL2Bus.snoops 453214 # Total snoops (count) 712system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram 713system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram 714system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram 715system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 716system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 717system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 718system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 719system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 720system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 721system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram 722system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram 723system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 724system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 725system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 726system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram 727system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) 728system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 729system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) 730system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 731system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) 732system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 733system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) 734system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 735system.cpu.icache.tags.replacements 73538 # number of replacements 736system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use 737system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. 738system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. 739system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. 740system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. 741system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor 742system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy 743system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy | 706system.cpu.dcache.tags.replacements 2823114 # number of replacements 707system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use 708system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. 709system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. 710system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. 711system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. 712system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor 713system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy 714system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 716system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id 718system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id 719system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 720system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses 721system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses 722system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits 723system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits 724system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits 725system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits 726system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits 727system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits 728system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits 729system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits 730system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 731system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 732system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits 733system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits 734system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits 735system.cpu.dcache.overall_hits::total 166674811 # number of overall hits 736system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses 737system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses 738system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses 739system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses 740system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses 741system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses 742system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 743system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 744system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses 745system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses 746system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses 747system.cpu.dcache.overall_misses::total 7050523 # number of overall misses 748system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles 749system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles 750system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles 751system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles 752system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles 753system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles 754system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles 755system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles 756system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles 757system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles 758system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) 759system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) 760system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 761system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 762system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) 763system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) 764system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) 765system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) 766system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 767system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 768system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses 769system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses 770system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses 771system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses 772system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses 773system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses 774system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses 775system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses 776system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses 777system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses 778system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 779system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 780system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses 781system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses 782system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses 783system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses 784system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency 785system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency 786system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency 787system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency 788system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency 789system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency 790system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency 791system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency 793system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency 794system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked 795system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked 796system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked 797system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked 798system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked 799system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked 800system.cpu.dcache.fast_writes 0 # number of fast writes performed 801system.cpu.dcache.cache_copies 0 # number of cache copies performed 802system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks 803system.cpu.dcache.writebacks::total 2354028 # number of writebacks 804system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits 805system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits 807system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits 808system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 809system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 810system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits 811system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits 812system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits 813system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits 814system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses 815system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses 816system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses 817system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses 818system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 819system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 820system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses 821system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses 822system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses 823system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses 824system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles 825system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles 826system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles 827system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles 828system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles 829system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles 830system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles 831system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles 832system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles 833system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles 834system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses 835system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses 836system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses 837system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses 838system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses 839system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses 840system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses 841system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses 842system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses 843system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses 844system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency 845system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency 846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency 847system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency 848system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency 849system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency 850system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency 851system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency 852system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency 853system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency 854system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 855system.cpu.icache.tags.replacements 73454 # number of replacements 856system.cpu.icache.tags.tagsinuse 465.665769 # Cycle average of tags in use 857system.cpu.icache.tags.total_refs 236580046 # Total number of references to valid blocks. 858system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks. 859system.cpu.icache.tags.avg_refs 3198.497228 # Average number of references to valid blocks. 860system.cpu.icache.tags.warmup_cycle 114499459250 # Cycle when the warmup percentage was hit. 861system.cpu.icache.tags.occ_blocks::cpu.inst 465.665769 # Average occupied blocks per requestor 862system.cpu.icache.tags.occ_percent::cpu.inst 0.909503 # Average percentage of cache occupancy 863system.cpu.icache.tags.occ_percent::total 0.909503 # Average percentage of cache occupancy |
| 744system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 864system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 745system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 746system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 747system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id | 865system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 867system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id |
| 748system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id | 868system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id |
| 749system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id | 869system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id |
| 750system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 870system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 751system.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses 752system.cpu.icache.tags.data_accesses 473451718 # Number of data accesses 753system.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits 754system.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits 755system.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits 756system.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits 757system.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits 758system.cpu.icache.overall_hits::total 236609871 # number of overall hits 759system.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses 760system.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses 761system.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses 762system.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses 763system.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses 764system.cpu.icache.overall_misses::total 78950 # number of overall misses 765system.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles 766system.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles 767system.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles 768system.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles 769system.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles 770system.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles 771system.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # number of ReadReq accesses(hits+misses) 772system.cpu.icache.ReadReq_accesses::total 236688821 # number of ReadReq accesses(hits+misses) 773system.cpu.icache.demand_accesses::cpu.inst 236688821 # number of demand (read+write) accesses 774system.cpu.icache.demand_accesses::total 236688821 # number of demand (read+write) accesses 775system.cpu.icache.overall_accesses::cpu.inst 236688821 # number of overall (read+write) accesses 776system.cpu.icache.overall_accesses::total 236688821 # number of overall (read+write) accesses 777system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000334 # miss rate for ReadReq accesses 778system.cpu.icache.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses 779system.cpu.icache.demand_miss_rate::cpu.inst 0.000334 # miss rate for demand accesses 780system.cpu.icache.demand_miss_rate::total 0.000334 # miss rate for demand accesses 781system.cpu.icache.overall_miss_rate::cpu.inst 0.000334 # miss rate for overall accesses 782system.cpu.icache.overall_miss_rate::total 0.000334 # miss rate for overall accesses 783system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11031.212983 # average ReadReq miss latency 784system.cpu.icache.ReadReq_avg_miss_latency::total 11031.212983 # average ReadReq miss latency 785system.cpu.icache.demand_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency 786system.cpu.icache.demand_avg_miss_latency::total 11031.212983 # average overall miss latency 787system.cpu.icache.overall_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency 788system.cpu.icache.overall_avg_miss_latency::total 11031.212983 # average overall miss latency 789system.cpu.icache.blocked_cycles::no_mshrs 56449 # number of cycles access was blocked 790system.cpu.icache.blocked_cycles::no_targets 14 # number of cycles access was blocked 791system.cpu.icache.blocked::no_mshrs 5209 # number of cycles access was blocked 792system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 793system.cpu.icache.avg_blocked_cycles::no_mshrs 10.836821 # average number of cycles each access was blocked 794system.cpu.icache.avg_blocked_cycles::no_targets 14 # average number of cycles each access was blocked | 871system.cpu.icache.tags.tag_accesses 473397028 # Number of tag accesses 872system.cpu.icache.tags.data_accesses 473397028 # Number of data accesses 873system.cpu.icache.ReadReq_hits::cpu.inst 236580046 # number of ReadReq hits 874system.cpu.icache.ReadReq_hits::total 236580046 # number of ReadReq hits 875system.cpu.icache.demand_hits::cpu.inst 236580046 # number of demand (read+write) hits 876system.cpu.icache.demand_hits::total 236580046 # number of demand (read+write) hits 877system.cpu.icache.overall_hits::cpu.inst 236580046 # number of overall hits 878system.cpu.icache.overall_hits::total 236580046 # number of overall hits 879system.cpu.icache.ReadReq_misses::cpu.inst 81472 # number of ReadReq misses 880system.cpu.icache.ReadReq_misses::total 81472 # number of ReadReq misses 881system.cpu.icache.demand_misses::cpu.inst 81472 # number of demand (read+write) misses 882system.cpu.icache.demand_misses::total 81472 # number of demand (read+write) misses 883system.cpu.icache.overall_misses::cpu.inst 81472 # number of overall misses 884system.cpu.icache.overall_misses::total 81472 # number of overall misses 885system.cpu.icache.ReadReq_miss_latency::cpu.inst 1465585914 # number of ReadReq miss cycles 886system.cpu.icache.ReadReq_miss_latency::total 1465585914 # number of ReadReq miss cycles 887system.cpu.icache.demand_miss_latency::cpu.inst 1465585914 # number of demand (read+write) miss cycles 888system.cpu.icache.demand_miss_latency::total 1465585914 # number of demand (read+write) miss cycles 889system.cpu.icache.overall_miss_latency::cpu.inst 1465585914 # number of overall miss cycles 890system.cpu.icache.overall_miss_latency::total 1465585914 # number of overall miss cycles 891system.cpu.icache.ReadReq_accesses::cpu.inst 236661518 # number of ReadReq accesses(hits+misses) 892system.cpu.icache.ReadReq_accesses::total 236661518 # number of ReadReq accesses(hits+misses) 893system.cpu.icache.demand_accesses::cpu.inst 236661518 # number of demand (read+write) accesses 894system.cpu.icache.demand_accesses::total 236661518 # number of demand (read+write) accesses 895system.cpu.icache.overall_accesses::cpu.inst 236661518 # number of overall (read+write) accesses 896system.cpu.icache.overall_accesses::total 236661518 # number of overall (read+write) accesses 897system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000344 # miss rate for ReadReq accesses 898system.cpu.icache.ReadReq_miss_rate::total 0.000344 # miss rate for ReadReq accesses 899system.cpu.icache.demand_miss_rate::cpu.inst 0.000344 # miss rate for demand accesses 900system.cpu.icache.demand_miss_rate::total 0.000344 # miss rate for demand accesses 901system.cpu.icache.overall_miss_rate::cpu.inst 0.000344 # miss rate for overall accesses 902system.cpu.icache.overall_miss_rate::total 0.000344 # miss rate for overall accesses 903system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17988.829463 # average ReadReq miss latency 904system.cpu.icache.ReadReq_avg_miss_latency::total 17988.829463 # average ReadReq miss latency 905system.cpu.icache.demand_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency 906system.cpu.icache.demand_avg_miss_latency::total 17988.829463 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency 908system.cpu.icache.overall_avg_miss_latency::total 17988.829463 # average overall miss latency 909system.cpu.icache.blocked_cycles::no_mshrs 164374 # number of cycles access was blocked 910system.cpu.icache.blocked_cycles::no_targets 692 # number of cycles access was blocked 911system.cpu.icache.blocked::no_mshrs 6271 # number of cycles access was blocked 912system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 913system.cpu.icache.avg_blocked_cycles::no_mshrs 26.211768 # average number of cycles each access was blocked 914system.cpu.icache.avg_blocked_cycles::no_targets 138.400000 # average number of cycles each access was blocked |
| 795system.cpu.icache.fast_writes 0 # number of fast writes performed 796system.cpu.icache.cache_copies 0 # number of cache copies performed | 915system.cpu.icache.fast_writes 0 # number of fast writes performed 916system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 797system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4873 # number of ReadReq MSHR hits 798system.cpu.icache.ReadReq_mshr_hits::total 4873 # number of ReadReq MSHR hits 799system.cpu.icache.demand_mshr_hits::cpu.inst 4873 # number of demand (read+write) MSHR hits 800system.cpu.icache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits 801system.cpu.icache.overall_mshr_hits::cpu.inst 4873 # number of overall MSHR hits 802system.cpu.icache.overall_mshr_hits::total 4873 # number of overall MSHR hits 803system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74077 # number of ReadReq MSHR misses 804system.cpu.icache.ReadReq_mshr_misses::total 74077 # number of ReadReq MSHR misses 805system.cpu.icache.demand_mshr_misses::cpu.inst 74077 # number of demand (read+write) MSHR misses 806system.cpu.icache.demand_mshr_misses::total 74077 # number of demand (read+write) MSHR misses 807system.cpu.icache.overall_mshr_misses::cpu.inst 74077 # number of overall MSHR misses 808system.cpu.icache.overall_mshr_misses::total 74077 # number of overall MSHR misses 809system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 689302633 # number of ReadReq MSHR miss cycles 810system.cpu.icache.ReadReq_mshr_miss_latency::total 689302633 # number of ReadReq MSHR miss cycles 811system.cpu.icache.demand_mshr_miss_latency::cpu.inst 689302633 # number of demand (read+write) MSHR miss cycles 812system.cpu.icache.demand_mshr_miss_latency::total 689302633 # number of demand (read+write) MSHR miss cycles 813system.cpu.icache.overall_mshr_miss_latency::cpu.inst 689302633 # number of overall MSHR miss cycles 814system.cpu.icache.overall_mshr_miss_latency::total 689302633 # number of overall MSHR miss cycles | 917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7479 # number of ReadReq MSHR hits 918system.cpu.icache.ReadReq_mshr_hits::total 7479 # number of ReadReq MSHR hits 919system.cpu.icache.demand_mshr_hits::cpu.inst 7479 # number of demand (read+write) MSHR hits 920system.cpu.icache.demand_mshr_hits::total 7479 # number of demand (read+write) MSHR hits 921system.cpu.icache.overall_mshr_hits::cpu.inst 7479 # number of overall MSHR hits 922system.cpu.icache.overall_mshr_hits::total 7479 # number of overall MSHR hits 923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73993 # number of ReadReq MSHR misses 924system.cpu.icache.ReadReq_mshr_misses::total 73993 # number of ReadReq MSHR misses 925system.cpu.icache.demand_mshr_misses::cpu.inst 73993 # number of demand (read+write) MSHR misses 926system.cpu.icache.demand_mshr_misses::total 73993 # number of demand (read+write) MSHR misses 927system.cpu.icache.overall_mshr_misses::cpu.inst 73993 # number of overall MSHR misses 928system.cpu.icache.overall_mshr_misses::total 73993 # number of overall MSHR misses 929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1129183847 # number of ReadReq MSHR miss cycles 930system.cpu.icache.ReadReq_mshr_miss_latency::total 1129183847 # number of ReadReq MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1129183847 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::total 1129183847 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1129183847 # number of overall MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::total 1129183847 # number of overall MSHR miss cycles |
| 815system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 816system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 817system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 818system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 819system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 820system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses | 935system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 936system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 937system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 938system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 939system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 940system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses |
| 821system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9305.217989 # average ReadReq mshr miss latency 822system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9305.217989 # average ReadReq mshr miss latency 823system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency 824system.cpu.icache.demand_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency | 941system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15260.684754 # average ReadReq mshr miss latency 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15260.684754 # average ReadReq mshr miss latency 943system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency 945system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency |
| 827system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 947system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 828system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 9798854 # number of hwpf identified 829system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 305321 # number of hwpf that were already in mshr 830system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9106282 # number of hwpf that were already in the cache 831system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 15837 # number of hwpf that were already in the prefetch queue 832system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 833system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6052 # number of hwpf removed because MSHR allocated 834system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 365354 # number of hwpf issued 835system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 921882 # number of hwpf spanning a virtual page 836system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 837system.cpu.l2cache.tags.replacements 438181 # number of replacements 838system.cpu.l2cache.tags.tagsinuse 15477.013957 # Cycle average of tags in use 839system.cpu.l2cache.tags.total_refs 4572801 # Total number of references to valid blocks. 840system.cpu.l2cache.tags.sampled_refs 454520 # Sample count of references to valid blocks. 841system.cpu.l2cache.tags.avg_refs 10.060726 # Average number of references to valid blocks. 842system.cpu.l2cache.tags.warmup_cycle 34588215000 # Cycle when the warmup percentage was hit. 843system.cpu.l2cache.tags.occ_blocks::writebacks 8046.531064 # Average occupied blocks per requestor 844system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.372204 # Average occupied blocks per requestor 845system.cpu.l2cache.tags.occ_blocks::cpu.data 4345.243734 # Average occupied blocks per requestor 846system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3000.866954 # Average occupied blocks per requestor 847system.cpu.l2cache.tags.occ_percent::writebacks 0.491121 # Average percentage of cache occupancy 848system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005150 # Average percentage of cache occupancy 849system.cpu.l2cache.tags.occ_percent::cpu.data 0.265213 # Average percentage of cache occupancy 850system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183158 # Average percentage of cache occupancy 851system.cpu.l2cache.tags.occ_percent::total 0.944642 # Average percentage of cache occupancy 852system.cpu.l2cache.tags.occ_task_id_blocks::1022 4229 # Occupied blocks per task id 853system.cpu.l2cache.tags.occ_task_id_blocks::1024 12110 # Occupied blocks per task id 854system.cpu.l2cache.tags.age_task_id_blocks_1022::0 106 # Occupied blocks per task id 855system.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 856system.cpu.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id 857system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2013 # Occupied blocks per task id 858system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1770 # Occupied blocks per task id 859system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 860system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 861system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id 862system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8654 # Occupied blocks per task id 863system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1689 # Occupied blocks per task id 864system.cpu.l2cache.tags.occ_task_id_percent::1022 0.258118 # Percentage of cache occupancy per task id 865system.cpu.l2cache.tags.occ_task_id_percent::1024 0.739136 # Percentage of cache occupancy per task id 866system.cpu.l2cache.tags.tag_accesses 84920061 # Number of tag accesses 867system.cpu.l2cache.tags.data_accesses 84920061 # Number of data accesses 868system.cpu.l2cache.ReadReq_hits::cpu.inst 70946 # number of ReadReq hits 869system.cpu.l2cache.ReadReq_hits::cpu.data 2166314 # number of ReadReq hits 870system.cpu.l2cache.ReadReq_hits::total 2237260 # number of ReadReq hits 871system.cpu.l2cache.Writeback_hits::writebacks 2348838 # number of Writeback hits 872system.cpu.l2cache.Writeback_hits::total 2348838 # number of Writeback hits | 948system.cpu.l2cache.prefetcher.num_hwpf_issued 8509131 # number of hwpf issued 949system.cpu.l2cache.prefetcher.pfIdentified 8512942 # number of prefetch candidates identified 950system.cpu.l2cache.prefetcher.pfBufferHit 2237 # number of redundant prefetches already in prefetch queue 951system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 952system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 953system.cpu.l2cache.prefetcher.pfSpanPage 743602 # number of prefetches not generated due to page crossing 954system.cpu.l2cache.tags.replacements 401614 # number of replacements 955system.cpu.l2cache.tags.tagsinuse 15413.386139 # Cycle average of tags in use 956system.cpu.l2cache.tags.total_refs 4559849 # Total number of references to valid blocks. 957system.cpu.l2cache.tags.sampled_refs 417953 # Sample count of references to valid blocks. 958system.cpu.l2cache.tags.avg_refs 10.909956 # Average number of references to valid blocks. 959system.cpu.l2cache.tags.warmup_cycle 34584601500 # Cycle when the warmup percentage was hit. 960system.cpu.l2cache.tags.occ_blocks::writebacks 8474.787715 # Average occupied blocks per requestor 961system.cpu.l2cache.tags.occ_blocks::cpu.inst 477.139723 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_blocks::cpu.data 4908.892257 # Average occupied blocks per requestor 963system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1552.566443 # Average occupied blocks per requestor 964system.cpu.l2cache.tags.occ_percent::writebacks 0.517260 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029122 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_percent::cpu.data 0.299615 # Average percentage of cache occupancy 967system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.094761 # Average percentage of cache occupancy 968system.cpu.l2cache.tags.occ_percent::total 0.940758 # Average percentage of cache occupancy 969system.cpu.l2cache.tags.occ_task_id_blocks::1022 1129 # Occupied blocks per task id 970system.cpu.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1022::2 49 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1022::4 821 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1536 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10030 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id 979system.cpu.l2cache.tags.occ_task_id_percent::1022 0.068909 # Percentage of cache occupancy per task id 980system.cpu.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id 981system.cpu.l2cache.tags.tag_accesses 84965966 # Number of tag accesses 982system.cpu.l2cache.tags.data_accesses 84965966 # Number of data accesses 983system.cpu.l2cache.ReadReq_hits::cpu.inst 63311 # number of ReadReq hits 984system.cpu.l2cache.ReadReq_hits::cpu.data 2156931 # number of ReadReq hits 985system.cpu.l2cache.ReadReq_hits::total 2220242 # number of ReadReq hits 986system.cpu.l2cache.Writeback_hits::writebacks 2354028 # number of Writeback hits 987system.cpu.l2cache.Writeback_hits::total 2354028 # number of Writeback hits |
| 873system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 874system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits | 988system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 989system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits |
| 875system.cpu.l2cache.ReadExReq_hits::cpu.data 516602 # number of ReadExReq hits 876system.cpu.l2cache.ReadExReq_hits::total 516602 # number of ReadExReq hits 877system.cpu.l2cache.demand_hits::cpu.inst 70946 # number of demand (read+write) hits 878system.cpu.l2cache.demand_hits::cpu.data 2682916 # number of demand (read+write) hits 879system.cpu.l2cache.demand_hits::total 2753862 # number of demand (read+write) hits 880system.cpu.l2cache.overall_hits::cpu.inst 70946 # number of overall hits 881system.cpu.l2cache.overall_hits::cpu.data 2682916 # number of overall hits 882system.cpu.l2cache.overall_hits::total 2753862 # number of overall hits 883system.cpu.l2cache.ReadReq_misses::cpu.inst 3100 # number of ReadReq misses 884system.cpu.l2cache.ReadReq_misses::cpu.data 135521 # number of ReadReq misses 885system.cpu.l2cache.ReadReq_misses::total 138621 # number of ReadReq misses 886system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 887system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 888system.cpu.l2cache.ReadExReq_misses::cpu.data 5139 # number of ReadExReq misses 889system.cpu.l2cache.ReadExReq_misses::total 5139 # number of ReadExReq misses 890system.cpu.l2cache.demand_misses::cpu.inst 3100 # number of demand (read+write) misses 891system.cpu.l2cache.demand_misses::cpu.data 140660 # number of demand (read+write) misses 892system.cpu.l2cache.demand_misses::total 143760 # number of demand (read+write) misses 893system.cpu.l2cache.overall_misses::cpu.inst 3100 # number of overall misses 894system.cpu.l2cache.overall_misses::cpu.data 140660 # number of overall misses 895system.cpu.l2cache.overall_misses::total 143760 # number of overall misses 896system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 221563221 # number of ReadReq miss cycles 897system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9589796237 # number of ReadReq miss cycles 898system.cpu.l2cache.ReadReq_miss_latency::total 9811359458 # number of ReadReq miss cycles 899system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14999 # number of UpgradeReq miss cycles 900system.cpu.l2cache.UpgradeReq_miss_latency::total 14999 # number of UpgradeReq miss cycles 901system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 412963248 # number of ReadExReq miss cycles 902system.cpu.l2cache.ReadExReq_miss_latency::total 412963248 # number of ReadExReq miss cycles 903system.cpu.l2cache.demand_miss_latency::cpu.inst 221563221 # number of demand (read+write) miss cycles 904system.cpu.l2cache.demand_miss_latency::cpu.data 10002759485 # number of demand (read+write) miss cycles 905system.cpu.l2cache.demand_miss_latency::total 10224322706 # number of demand (read+write) miss cycles 906system.cpu.l2cache.overall_miss_latency::cpu.inst 221563221 # number of overall miss cycles 907system.cpu.l2cache.overall_miss_latency::cpu.data 10002759485 # number of overall miss cycles 908system.cpu.l2cache.overall_miss_latency::total 10224322706 # number of overall miss cycles 909system.cpu.l2cache.ReadReq_accesses::cpu.inst 74046 # number of ReadReq accesses(hits+misses) 910system.cpu.l2cache.ReadReq_accesses::cpu.data 2301835 # number of ReadReq accesses(hits+misses) 911system.cpu.l2cache.ReadReq_accesses::total 2375881 # number of ReadReq accesses(hits+misses) 912system.cpu.l2cache.Writeback_accesses::writebacks 2348838 # number of Writeback accesses(hits+misses) 913system.cpu.l2cache.Writeback_accesses::total 2348838 # number of Writeback accesses(hits+misses) 914system.cpu.l2cache.UpgradeReq_accesses::cpu.data 26 # number of UpgradeReq accesses(hits+misses) 915system.cpu.l2cache.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) 916system.cpu.l2cache.ReadExReq_accesses::cpu.data 521741 # number of ReadExReq accesses(hits+misses) 917system.cpu.l2cache.ReadExReq_accesses::total 521741 # number of ReadExReq accesses(hits+misses) 918system.cpu.l2cache.demand_accesses::cpu.inst 74046 # number of demand (read+write) accesses 919system.cpu.l2cache.demand_accesses::cpu.data 2823576 # number of demand (read+write) accesses 920system.cpu.l2cache.demand_accesses::total 2897622 # number of demand (read+write) accesses 921system.cpu.l2cache.overall_accesses::cpu.inst 74046 # number of overall (read+write) accesses 922system.cpu.l2cache.overall_accesses::cpu.data 2823576 # number of overall (read+write) accesses 923system.cpu.l2cache.overall_accesses::total 2897622 # number of overall (read+write) accesses 924system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.041866 # miss rate for ReadReq accesses 925system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.058875 # miss rate for ReadReq accesses 926system.cpu.l2cache.ReadReq_miss_rate::total 0.058345 # miss rate for ReadReq accesses 927system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses 928system.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses 929system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009850 # miss rate for ReadExReq accesses 930system.cpu.l2cache.ReadExReq_miss_rate::total 0.009850 # miss rate for ReadExReq accesses 931system.cpu.l2cache.demand_miss_rate::cpu.inst 0.041866 # miss rate for demand accesses 932system.cpu.l2cache.demand_miss_rate::cpu.data 0.049816 # miss rate for demand accesses 933system.cpu.l2cache.demand_miss_rate::total 0.049613 # miss rate for demand accesses 934system.cpu.l2cache.overall_miss_rate::cpu.inst 0.041866 # miss rate for overall accesses 935system.cpu.l2cache.overall_miss_rate::cpu.data 0.049816 # miss rate for overall accesses 936system.cpu.l2cache.overall_miss_rate::total 0.049613 # miss rate for overall accesses 937system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71472.006774 # average ReadReq miss latency 938system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70762.437091 # average ReadReq miss latency 939system.cpu.l2cache.ReadReq_avg_miss_latency::total 70778.305293 # average ReadReq miss latency 940system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4999.666667 # average UpgradeReq miss latency 941system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4999.666667 # average UpgradeReq miss latency 942system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80358.678342 # average ReadExReq miss latency 943system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80358.678342 # average ReadExReq miss latency 944system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency 945system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency 946system.cpu.l2cache.demand_avg_miss_latency::total 71120.775640 # average overall miss latency 947system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency 948system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency 949system.cpu.l2cache.overall_avg_miss_latency::total 71120.775640 # average overall miss latency 950system.cpu.l2cache.blocked_cycles::no_mshrs 8362 # number of cycles access was blocked | 990system.cpu.l2cache.ReadExReq_hits::cpu.data 516650 # number of ReadExReq hits 991system.cpu.l2cache.ReadExReq_hits::total 516650 # number of ReadExReq hits 992system.cpu.l2cache.demand_hits::cpu.inst 63311 # number of demand (read+write) hits 993system.cpu.l2cache.demand_hits::cpu.data 2673581 # number of demand (read+write) hits 994system.cpu.l2cache.demand_hits::total 2736892 # number of demand (read+write) hits 995system.cpu.l2cache.overall_hits::cpu.inst 63311 # number of overall hits 996system.cpu.l2cache.overall_hits::cpu.data 2673581 # number of overall hits 997system.cpu.l2cache.overall_hits::total 2736892 # number of overall hits 998system.cpu.l2cache.ReadReq_misses::cpu.inst 10651 # number of ReadReq misses 999system.cpu.l2cache.ReadReq_misses::cpu.data 144961 # number of ReadReq misses 1000system.cpu.l2cache.ReadReq_misses::total 155612 # number of ReadReq misses 1001system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 1002system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 1003system.cpu.l2cache.ReadExReq_misses::cpu.data 5084 # number of ReadExReq misses 1004system.cpu.l2cache.ReadExReq_misses::total 5084 # number of ReadExReq misses 1005system.cpu.l2cache.demand_misses::cpu.inst 10651 # number of demand (read+write) misses 1006system.cpu.l2cache.demand_misses::cpu.data 150045 # number of demand (read+write) misses 1007system.cpu.l2cache.demand_misses::total 160696 # number of demand (read+write) misses 1008system.cpu.l2cache.overall_misses::cpu.inst 10651 # number of overall misses 1009system.cpu.l2cache.overall_misses::cpu.data 150045 # number of overall misses 1010system.cpu.l2cache.overall_misses::total 160696 # number of overall misses 1011system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711026986 # number of ReadReq miss cycles 1012system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10160623428 # number of ReadReq miss cycles 1013system.cpu.l2cache.ReadReq_miss_latency::total 10871650414 # number of ReadReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 411274728 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadExReq_miss_latency::total 411274728 # number of ReadExReq miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.inst 711026986 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.data 10571898156 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::total 11282925142 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.overall_miss_latency::cpu.inst 711026986 # number of overall miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.data 10571898156 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::total 11282925142 # number of overall miss cycles 1022system.cpu.l2cache.ReadReq_accesses::cpu.inst 73962 # number of ReadReq accesses(hits+misses) 1023system.cpu.l2cache.ReadReq_accesses::cpu.data 2301892 # number of ReadReq accesses(hits+misses) 1024system.cpu.l2cache.ReadReq_accesses::total 2375854 # number of ReadReq accesses(hits+misses) 1025system.cpu.l2cache.Writeback_accesses::writebacks 2354028 # number of Writeback accesses(hits+misses) 1026system.cpu.l2cache.Writeback_accesses::total 2354028 # number of Writeback accesses(hits+misses) 1027system.cpu.l2cache.UpgradeReq_accesses::cpu.data 25 # number of UpgradeReq accesses(hits+misses) 1028system.cpu.l2cache.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses) 1029system.cpu.l2cache.ReadExReq_accesses::cpu.data 521734 # number of ReadExReq accesses(hits+misses) 1030system.cpu.l2cache.ReadExReq_accesses::total 521734 # number of ReadExReq accesses(hits+misses) 1031system.cpu.l2cache.demand_accesses::cpu.inst 73962 # number of demand (read+write) accesses 1032system.cpu.l2cache.demand_accesses::cpu.data 2823626 # number of demand (read+write) accesses 1033system.cpu.l2cache.demand_accesses::total 2897588 # number of demand (read+write) accesses 1034system.cpu.l2cache.overall_accesses::cpu.inst 73962 # number of overall (read+write) accesses 1035system.cpu.l2cache.overall_accesses::cpu.data 2823626 # number of overall (read+write) accesses 1036system.cpu.l2cache.overall_accesses::total 2897588 # number of overall (read+write) accesses 1037system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.144006 # miss rate for ReadReq accesses 1038system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062975 # miss rate for ReadReq accesses 1039system.cpu.l2cache.ReadReq_miss_rate::total 0.065497 # miss rate for ReadReq accesses 1040system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.080000 # miss rate for UpgradeReq accesses 1041system.cpu.l2cache.UpgradeReq_miss_rate::total 0.080000 # miss rate for UpgradeReq accesses 1042system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009744 # miss rate for ReadExReq accesses 1043system.cpu.l2cache.ReadExReq_miss_rate::total 0.009744 # miss rate for ReadExReq accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144006 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::cpu.data 0.053139 # miss rate for demand accesses 1046system.cpu.l2cache.demand_miss_rate::total 0.055459 # miss rate for demand accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144006 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.data 0.053139 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::total 0.055459 # miss rate for overall accesses 1050system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66756.829030 # average ReadReq miss latency 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70092.117383 # average ReadReq miss latency 1052system.cpu.l2cache.ReadReq_avg_miss_latency::total 69863.830643 # average ReadReq miss latency 1053system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80895.894571 # average ReadExReq miss latency 1054system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80895.894571 # average ReadExReq miss latency 1055system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66756.829030 # average overall miss latency 1056system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70458.183585 # average overall miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::total 70212.856213 # average overall miss latency 1058system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66756.829030 # average overall miss latency 1059system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70458.183585 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::total 70212.856213 # average overall miss latency 1061system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 951system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1062system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 952system.cpu.l2cache.blocked::no_mshrs 219 # number of cycles access was blocked | 1063system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 953system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1064system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 954system.cpu.l2cache.avg_blocked_cycles::no_mshrs 38.182648 # average number of cycles each access was blocked | 1065system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 955system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 956system.cpu.l2cache.fast_writes 0 # number of fast writes performed 957system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1066system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1067system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1068system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 958system.cpu.l2cache.writebacks::writebacks 303849 # number of writebacks 959system.cpu.l2cache.writebacks::total 303849 # number of writebacks 960system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 992 # number of ReadReq MSHR hits 961system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5184 # number of ReadReq MSHR hits 962system.cpu.l2cache.ReadReq_mshr_hits::total 6176 # number of ReadReq MSHR hits 963system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1526 # number of ReadExReq MSHR hits 964system.cpu.l2cache.ReadExReq_mshr_hits::total 1526 # number of ReadExReq MSHR hits 965system.cpu.l2cache.demand_mshr_hits::cpu.inst 992 # number of demand (read+write) MSHR hits 966system.cpu.l2cache.demand_mshr_hits::cpu.data 6710 # number of demand (read+write) MSHR hits 967system.cpu.l2cache.demand_mshr_hits::total 7702 # number of demand (read+write) MSHR hits 968system.cpu.l2cache.overall_mshr_hits::cpu.inst 992 # number of overall MSHR hits 969system.cpu.l2cache.overall_mshr_hits::cpu.data 6710 # number of overall MSHR hits 970system.cpu.l2cache.overall_mshr_hits::total 7702 # number of overall MSHR hits 971system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2108 # number of ReadReq MSHR misses 972system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 130337 # number of ReadReq MSHR misses 973system.cpu.l2cache.ReadReq_mshr_misses::total 132445 # number of ReadReq MSHR misses 974system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 365353 # number of HardPFReq MSHR misses 975system.cpu.l2cache.HardPFReq_mshr_misses::total 365353 # number of HardPFReq MSHR misses 976system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 977system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 978system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3613 # number of ReadExReq MSHR misses 979system.cpu.l2cache.ReadExReq_mshr_misses::total 3613 # number of ReadExReq MSHR misses 980system.cpu.l2cache.demand_mshr_misses::cpu.inst 2108 # number of demand (read+write) MSHR misses 981system.cpu.l2cache.demand_mshr_misses::cpu.data 133950 # number of demand (read+write) MSHR misses 982system.cpu.l2cache.demand_mshr_misses::total 136058 # number of demand (read+write) MSHR misses 983system.cpu.l2cache.overall_mshr_misses::cpu.inst 2108 # number of overall MSHR misses 984system.cpu.l2cache.overall_mshr_misses::cpu.data 133950 # number of overall MSHR misses 985system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 365353 # number of overall MSHR misses 986system.cpu.l2cache.overall_mshr_misses::total 501411 # number of overall MSHR misses 987system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154832998 # number of ReadReq MSHR miss cycles 988system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8096605997 # number of ReadReq MSHR miss cycles 989system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8251438995 # number of ReadReq MSHR miss cycles 990system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of HardPFReq MSHR miss cycles 991system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21877894699 # number of HardPFReq MSHR miss cycles 992system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 18003 # number of UpgradeReq MSHR miss cycles 993system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 18003 # number of UpgradeReq MSHR miss cycles 994system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 231375752 # number of ReadExReq MSHR miss cycles 995system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 231375752 # number of ReadExReq MSHR miss cycles 996system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154832998 # number of demand (read+write) MSHR miss cycles 997system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8327981749 # number of demand (read+write) MSHR miss cycles 998system.cpu.l2cache.demand_mshr_miss_latency::total 8482814747 # number of demand (read+write) MSHR miss cycles 999system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154832998 # number of overall MSHR miss cycles 1000system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8327981749 # number of overall MSHR miss cycles 1001system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of overall MSHR miss cycles 1002system.cpu.l2cache.overall_mshr_miss_latency::total 30360709446 # number of overall MSHR miss cycles 1003system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for ReadReq accesses 1004system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.056623 # mshr miss rate for ReadReq accesses 1005system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.055746 # mshr miss rate for ReadReq accesses | 1069system.cpu.l2cache.writebacks::writebacks 292638 # number of writebacks 1070system.cpu.l2cache.writebacks::total 292638 # number of writebacks 1071system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 1072system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4068 # number of ReadReq MSHR hits 1073system.cpu.l2cache.ReadReq_mshr_hits::total 4076 # number of ReadReq MSHR hits 1074system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1399 # number of ReadExReq MSHR hits 1075system.cpu.l2cache.ReadExReq_mshr_hits::total 1399 # number of ReadExReq MSHR hits 1076system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 1077system.cpu.l2cache.demand_mshr_hits::cpu.data 5467 # number of demand (read+write) MSHR hits 1078system.cpu.l2cache.demand_mshr_hits::total 5475 # number of demand (read+write) MSHR hits 1079system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 1080system.cpu.l2cache.overall_mshr_hits::cpu.data 5467 # number of overall MSHR hits 1081system.cpu.l2cache.overall_mshr_hits::total 5475 # number of overall MSHR hits 1082system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10643 # number of ReadReq MSHR misses 1083system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 140893 # number of ReadReq MSHR misses 1084system.cpu.l2cache.ReadReq_mshr_misses::total 151536 # number of ReadReq MSHR misses 1085system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275229 # number of HardPFReq MSHR misses 1086system.cpu.l2cache.HardPFReq_mshr_misses::total 275229 # number of HardPFReq MSHR misses 1087system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 1088system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 1089system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3685 # number of ReadExReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::total 3685 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.demand_mshr_misses::cpu.inst 10643 # number of demand (read+write) MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.data 144578 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::total 155221 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.overall_mshr_misses::cpu.inst 10643 # number of overall MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.data 144578 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275229 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::total 430450 # number of overall MSHR misses 1098system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619626514 # number of ReadReq MSHR miss cycles 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8627975760 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9247602274 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of HardPFReq MSHR miss cycles 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18094630257 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles 1104system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles 1105system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 229963510 # number of ReadExReq MSHR miss cycles 1106system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 229963510 # number of ReadExReq MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619626514 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8857939270 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::total 9477565784 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619626514 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8857939270 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::total 27572196041 # number of overall MSHR miss cycles 1114system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for ReadReq accesses 1115system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.061207 # mshr miss rate for ReadReq accesses 1116system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063782 # mshr miss rate for ReadReq accesses |
| 1006system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1007system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1117system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1118system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1008system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses 1009system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses 1010system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006925 # mshr miss rate for ReadExReq accesses 1011system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006925 # mshr miss rate for ReadExReq accesses 1012system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for demand accesses 1013system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for demand accesses 1014system.cpu.l2cache.demand_mshr_miss_rate::total 0.046955 # mshr miss rate for demand accesses 1015system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for overall accesses 1016system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for overall accesses | 1119system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses 1120system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses 1121system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses 1122system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses 1123system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses 1124system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses 1125system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses 1126system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses |
| 1017system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1128system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1018system.cpu.l2cache.overall_mshr_miss_rate::total 0.173042 # mshr miss rate for overall accesses 1019system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73450.188805 # average ReadReq mshr miss latency 1020system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62120.549015 # average ReadReq mshr miss latency 1021system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency 1022system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency 1023system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency | 1129system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses 1130system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency 1131system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency 1132system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency 1133system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency 1134system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency |
| 1024system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1025system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency | 1135system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1136system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency |
| 1026system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency 1027system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency 1028system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency 1029system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency 1030system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency 1031system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency 1032system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency 1033system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency 1034system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency | 1137system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency 1138system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency |
| 1035system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1146system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1036system.cpu.dcache.tags.replacements 2823064 # number of replacements 1037system.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use 1038system.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks. 1039system.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks. 1040system.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks. 1041system.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit. 1042system.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor 1043system.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy 1044system.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy 1045system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1046system.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 1047system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 1048system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id 1049system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1050system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses 1051system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses 1052system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits 1053system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits 1054system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits 1055system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits 1056system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits 1057system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits 1058system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits 1059system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits 1060system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 1061system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 1062system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits 1063system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits 1064system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits 1065system.cpu.dcache.overall_hits::total 166678355 # number of overall hits 1066system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses 1067system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses 1068system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses 1069system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses 1070system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses 1071system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses 1072system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 1073system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 1074system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses 1075system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses 1076system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses 1077system.cpu.dcache.overall_misses::total 7049008 # number of overall misses 1078system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles 1079system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles 1080system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles 1081system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles 1082system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles 1083system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles 1084system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles 1085system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles 1086system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles 1087system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles 1088system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) 1089system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) 1090system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 1091system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 1092system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) 1093system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) 1094system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) 1095system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) 1096system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 1097system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 1098system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses 1099system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses 1100system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses 1101system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses 1102system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses 1103system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses 1104system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses 1105system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses 1106system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses 1107system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses 1108system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 1109system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 1110system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses 1111system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses 1112system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses 1113system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses 1114system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency 1115system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency 1116system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency 1117system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency 1118system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency 1119system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency 1120system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency 1121system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency 1122system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency 1123system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency 1124system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked 1125system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked 1126system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 1127system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked 1128system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked 1129system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked 1130system.cpu.dcache.fast_writes 0 # number of fast writes performed 1131system.cpu.dcache.cache_copies 0 # number of cache copies performed 1132system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks 1133system.cpu.dcache.writebacks::total 2348838 # number of writebacks 1134system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits 1135system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits 1136system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits 1137system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits 1138system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 1139system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 1140system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits 1141system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits 1142system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits 1143system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits 1144system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses 1145system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses 1146system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses 1147system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses 1148system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 1149system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 1150system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses 1151system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses 1152system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses 1153system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses 1154system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles 1155system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles 1156system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles 1157system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles 1158system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles 1159system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles 1160system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles 1161system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles 1162system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles 1163system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles 1164system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses 1165system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses 1166system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses 1167system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses 1168system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses 1169system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses 1170system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses 1171system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses 1172system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses 1173system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses 1174system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency 1175system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency 1176system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency 1177system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency 1178system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency 1179system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency 1180system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency 1181system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency 1182system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency 1183system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency 1184system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1147system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution 1155system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) 1156system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) 1157system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.snoops 335729 # Total snoops (count) 1162system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram 1177system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) 1178system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 1179system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1181system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) 1182system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 1183system.membus.trans_dist::ReadReq 408974 # Transaction distribution 1184system.membus.trans_dist::ReadResp 408974 # Transaction distribution 1185system.membus.trans_dist::Writeback 292638 # Transaction distribution 1186system.membus.trans_dist::UpgradeReq 3 # Transaction distribution 1187system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1188system.membus.trans_dist::ReadExReq 3684 # Transaction distribution 1189system.membus.trans_dist::ReadExResp 3684 # Transaction distribution 1190system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) 1191system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) 1192system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) 1193system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) 1194system.membus.snoops 0 # Total snoops (count) 1195system.membus.snoop_fanout::samples 705299 # Request fanout histogram 1196system.membus.snoop_fanout::mean 0 # Request fanout histogram 1197system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1198system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1199system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram 1200system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1201system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1202system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1203system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1204system.membus.snoop_fanout::total 705299 # Request fanout histogram 1205system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) 1206system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 1207system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) 1208system.membus.respLayer1.utilization 1.7 # Layer utilization (%) |
| 1185 1186---------- End Simulation Statistics ---------- | 1209 1210---------- End Simulation Statistics ---------- |