1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.199845 # Number of seconds simulated
4sim_ticks 199845137000 # Number of ticks simulated
5final_tick 199845137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 125206 # Simulator instruction rate (inst/s)
8host_op_rate 141162 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 49524846 # Simulator tick rate (ticks/s)
10host_mem_usage 271424 # Number of bytes of host memory used
11host_seconds 4035.25 # Real time elapsed on the host
|
7host_inst_rate 125858 # Simulator instruction rate (inst/s)
8host_op_rate 141897 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 49782690 # Simulator tick rate (ticks/s)
10host_mem_usage 271600 # Number of bytes of host memory used
11host_seconds 4014.35 # Real time elapsed on the host |
12sim_insts 505237723 # Number of instructions simulated
13sim_ops 569624283 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 216832 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9264064 # Number of bytes read from this memory
16system.physmem.bytes_read::total 9480896 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 216832 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 216832 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 6248064 # Number of bytes written to this memory
20system.physmem.bytes_written::total 6248064 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3388 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 144751 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 148139 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 97626 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 97626 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 1085000 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 46356214 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 47441214 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 1085000 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 1085000 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 31264529 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 31264529 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 31264529 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 1085000 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 46356214 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 78705743 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 148141 # Total number of read requests seen
38system.physmem.writeReqs 97626 # Total number of write requests seen
39system.physmem.cpureqs 245778 # Reqs generatd by CPU via cache - shady
40system.physmem.bytesRead 9480896 # Total number of bytes read from memory
41system.physmem.bytesWritten 6248064 # Total number of bytes written to memory
42system.physmem.bytesConsumedRd 9480896 # bytesRead derated as per pkt->getSize()
43system.physmem.bytesConsumedWr 6248064 # bytesWritten derated as per pkt->getSize()
44system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 9221 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::3 8810 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::4 9230 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::5 8975 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::6 9245 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::7 9467 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::8 9113 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::9 10253 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::10 9691 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 9704 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::12 9106 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::13 8950 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 9023 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 8762 # Track reads on a per bank basis
62system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::3 5944 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::4 6131 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::5 5962 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::7 6376 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::8 5947 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::9 6637 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::12 6036 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::13 6064 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::15 5787 # Track writes on a per bank basis
78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
80system.physmem.totGap 199845120000 # Total gap between requests
81system.physmem.readPktSize::0 0 # Categorize read packet sizes
82system.physmem.readPktSize::1 0 # Categorize read packet sizes
83system.physmem.readPktSize::2 0 # Categorize read packet sizes
84system.physmem.readPktSize::3 0 # Categorize read packet sizes
85system.physmem.readPktSize::4 0 # Categorize read packet sizes
86system.physmem.readPktSize::5 0 # Categorize read packet sizes
87system.physmem.readPktSize::6 148141 # Categorize read packet sizes
88system.physmem.readPktSize::7 0 # Categorize read packet sizes
89system.physmem.readPktSize::8 0 # Categorize read packet sizes
90system.physmem.writePktSize::0 0 # categorize write packet sizes
91system.physmem.writePktSize::1 0 # categorize write packet sizes
92system.physmem.writePktSize::2 0 # categorize write packet sizes
93system.physmem.writePktSize::3 0 # categorize write packet sizes
94system.physmem.writePktSize::4 0 # categorize write packet sizes
95system.physmem.writePktSize::5 0 # categorize write packet sizes
96system.physmem.writePktSize::6 97626 # categorize write packet sizes
97system.physmem.writePktSize::7 0 # categorize write packet sizes
98system.physmem.writePktSize::8 0 # categorize write packet sizes
99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
105system.physmem.neitherpktsize::6 11 # categorize neither packet sizes
106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
108system.physmem.rdQLenPdf::0 138213 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::1 9240 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::2 554 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
141system.physmem.wrQLenPdf::0 4234 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
174system.physmem.totQLat 1637260686 # Total cycles spent in queuing delays
175system.physmem.totMemAccLat 4709936686 # Sum of mem lat for all requests
176system.physmem.totBusLat 592324000 # Total cycles spent in databus access
177system.physmem.totBankLat 2480352000 # Total cycles spent in bank access
178system.physmem.avgQLat 11056.52 # Average queueing delay per request
179system.physmem.avgBankLat 16749.97 # Average bank access latency per request
180system.physmem.avgBusLat 4000.00 # Average bus latency per request
181system.physmem.avgMemAccLat 31806.49 # Average memory access latency
182system.physmem.avgRdBW 47.44 # Average achieved read bandwidth in MB/s
183system.physmem.avgWrBW 31.26 # Average achieved write bandwidth in MB/s
184system.physmem.avgConsumedRdBW 47.44 # Average consumed read bandwidth in MB/s
185system.physmem.avgConsumedWrBW 31.26 # Average consumed write bandwidth in MB/s
186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
187system.physmem.busUtil 0.49 # Data bus utilization in percentage
188system.physmem.avgRdQLen 0.02 # Average read queue length over time
189system.physmem.avgWrQLen 8.64 # Average write queue length over time
190system.physmem.readRowHits 128534 # Number of row buffer hits during reads
191system.physmem.writeRowHits 35160 # Number of row buffer hits during writes
192system.physmem.readRowHitRate 86.80 # Row buffer hit rate for reads
193system.physmem.writeRowHitRate 36.01 # Row buffer hit rate for writes
194system.physmem.avgGap 813148.71 # Average gap between requests
|
195system.cpu.branchPred.lookups 182820446 # Number of BP lookups
196system.cpu.branchPred.condPredicted 143128871 # Number of conditional branches predicted
197system.cpu.branchPred.condIncorrect 7268870 # Number of conditional branches incorrect
198system.cpu.branchPred.BTBLookups 92944153 # Number of BTB lookups
199system.cpu.branchPred.BTBHits 87230072 # Number of BTB hits
200system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
201system.cpu.branchPred.BTBHitPct 93.852135 # BTB Hit Percentage
202system.cpu.branchPred.usedRAS 12684982 # Number of times the RAS was used to get a target.
203system.cpu.branchPred.RASInCorrect 116077 # Number of incorrect RAS predictions. |
204system.cpu.dtb.inst_hits 0 # ITB inst hits
205system.cpu.dtb.inst_misses 0 # ITB inst misses
206system.cpu.dtb.read_hits 0 # DTB read hits
207system.cpu.dtb.read_misses 0 # DTB read misses
208system.cpu.dtb.write_hits 0 # DTB write hits
209system.cpu.dtb.write_misses 0 # DTB write misses
210system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
211system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
212system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
213system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
214system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
215system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
216system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
217system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
218system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
219system.cpu.dtb.read_accesses 0 # DTB read accesses
220system.cpu.dtb.write_accesses 0 # DTB write accesses
221system.cpu.dtb.inst_accesses 0 # ITB inst accesses
222system.cpu.dtb.hits 0 # DTB hits
223system.cpu.dtb.misses 0 # DTB misses
224system.cpu.dtb.accesses 0 # DTB accesses
225system.cpu.itb.inst_hits 0 # ITB inst hits
226system.cpu.itb.inst_misses 0 # ITB inst misses
227system.cpu.itb.read_hits 0 # DTB read hits
228system.cpu.itb.read_misses 0 # DTB read misses
229system.cpu.itb.write_hits 0 # DTB write hits
230system.cpu.itb.write_misses 0 # DTB write misses
231system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
232system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
233system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
234system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
235system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
236system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
237system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
238system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
239system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
240system.cpu.itb.read_accesses 0 # DTB read accesses
241system.cpu.itb.write_accesses 0 # DTB write accesses
242system.cpu.itb.inst_accesses 0 # ITB inst accesses
243system.cpu.itb.hits 0 # DTB hits
244system.cpu.itb.misses 0 # DTB misses
245system.cpu.itb.accesses 0 # DTB accesses
246system.cpu.workload.num_syscalls 548 # Number of system calls
247system.cpu.numCycles 399690275 # number of cpu cycles simulated
248system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
249system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
241system.cpu.BPredUnit.lookups 182820446 # Number of BP lookups
242system.cpu.BPredUnit.condPredicted 143128871 # Number of conditional branches predicted
243system.cpu.BPredUnit.condIncorrect 7268870 # Number of conditional branches incorrect
244system.cpu.BPredUnit.BTBLookups 92944153 # Number of BTB lookups
245system.cpu.BPredUnit.BTBHits 87230072 # Number of BTB hits
246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
247system.cpu.BPredUnit.usedRAS 12684982 # Number of times the RAS was used to get a target.
248system.cpu.BPredUnit.RASInCorrect 116077 # Number of incorrect RAS predictions.
|
250system.cpu.fetch.icacheStallCycles 119371931 # Number of cycles fetch is stalled on an Icache miss
251system.cpu.fetch.Insts 761680364 # Number of instructions fetch has processed
252system.cpu.fetch.Branches 182820446 # Number of branches that fetch encountered
253system.cpu.fetch.predictedBranches 99915054 # Number of branches that fetch has predicted taken
254system.cpu.fetch.Cycles 170174199 # Number of cycles fetch has run and was not squashing or blocked
255system.cpu.fetch.SquashCycles 35702256 # Number of cycles fetch has spent squashing
256system.cpu.fetch.BlockedCycles 75350704 # Number of cycles fetch has spent blocked
257system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
258system.cpu.fetch.PendingTrapStallCycles 616 # Number of stall cycles due to pending traps
259system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
260system.cpu.fetch.CacheLines 114527354 # Number of cache lines fetched
261system.cpu.fetch.IcacheSquashes 2441016 # Number of outstanding Icache misses that were squashed
262system.cpu.fetch.rateDist::samples 392530086 # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::mean 2.176527 # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.rateDist::stdev 2.990721 # Number of instructions fetched each cycle (Total)
265system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
266system.cpu.fetch.rateDist::0 222368477 56.65% 56.65% # Number of instructions fetched each cycle (Total)
267system.cpu.fetch.rateDist::1 14183765 3.61% 60.26% # Number of instructions fetched each cycle (Total)
268system.cpu.fetch.rateDist::2 22901577 5.83% 66.10% # Number of instructions fetched each cycle (Total)
269system.cpu.fetch.rateDist::3 22747664 5.80% 71.89% # Number of instructions fetched each cycle (Total)
270system.cpu.fetch.rateDist::4 20903604 5.33% 77.22% # Number of instructions fetched each cycle (Total)
271system.cpu.fetch.rateDist::5 11591587 2.95% 80.17% # Number of instructions fetched each cycle (Total)
272system.cpu.fetch.rateDist::6 13062137 3.33% 83.50% # Number of instructions fetched each cycle (Total)
273system.cpu.fetch.rateDist::7 11992821 3.06% 86.55% # Number of instructions fetched each cycle (Total)
274system.cpu.fetch.rateDist::8 52778454 13.45% 100.00% # Number of instructions fetched each cycle (Total)
275system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
276system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
277system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
278system.cpu.fetch.rateDist::total 392530086 # Number of instructions fetched each cycle (Total)
279system.cpu.fetch.branchRate 0.457405 # Number of branch fetches per cycle
280system.cpu.fetch.rate 1.905676 # Number of inst fetches per cycle
281system.cpu.decode.IdleCycles 129024913 # Number of cycles decode is idle
282system.cpu.decode.BlockedCycles 70885415 # Number of cycles decode is blocked
283system.cpu.decode.RunCycles 158884550 # Number of cycles decode is running
284system.cpu.decode.UnblockCycles 6176695 # Number of cycles decode is unblocking
285system.cpu.decode.SquashCycles 27558513 # Number of cycles decode is squashing
286system.cpu.decode.BranchResolved 26126183 # Number of times decode resolved a branch
287system.cpu.decode.BranchMispred 76772 # Number of times decode detected a branch misprediction
288system.cpu.decode.DecodedInsts 825683046 # Number of instructions handled by decode
289system.cpu.decode.SquashedInsts 296199 # Number of squashed instructions handled by decode
290system.cpu.rename.SquashCycles 27558513 # Number of cycles rename is squashing
291system.cpu.rename.IdleCycles 135608190 # Number of cycles rename is idle
292system.cpu.rename.BlockCycles 9588825 # Number of cycles rename is blocking
293system.cpu.rename.serializeStallCycles 46459719 # count of cycles rename stalled for serializing inst
294system.cpu.rename.RunCycles 158300780 # Number of cycles rename is running
295system.cpu.rename.UnblockCycles 15014059 # Number of cycles rename is unblocking
296system.cpu.rename.RenamedInsts 800754331 # Number of instructions processed by rename
297system.cpu.rename.ROBFullEvents 1065 # Number of times rename has blocked due to ROB full
298system.cpu.rename.IQFullEvents 3044118 # Number of times rename has blocked due to IQ full
299system.cpu.rename.LSQFullEvents 8771537 # Number of times rename has blocked due to LSQ full
300system.cpu.rename.FullRegisterEvents 204 # Number of times there has been no free registers
301system.cpu.rename.RenamedOperands 954467105 # Number of destination operands rename has renamed
302system.cpu.rename.RenameLookups 3501224581 # Number of register rename lookups that rename has made
303system.cpu.rename.int_rename_lookups 3501223353 # Number of integer rename lookups
304system.cpu.rename.fp_rename_lookups 1228 # Number of floating rename lookups
305system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
306system.cpu.rename.UndoneMaps 288214814 # Number of HB maps that are undone due to squashing
307system.cpu.rename.serializingInsts 2293021 # count of serializing insts renamed
308system.cpu.rename.tempSerializingInsts 2293019 # count of temporary serializing insts renamed
309system.cpu.rename.skidInsts 41499614 # count of insts added to the skid buffer
310system.cpu.memDep0.insertedLoads 170286842 # Number of loads inserted to the mem dependence unit.
311system.cpu.memDep0.insertedStores 73502565 # Number of stores inserted to the mem dependence unit.
312system.cpu.memDep0.conflictingLoads 28542432 # Number of conflicting loads.
313system.cpu.memDep0.conflictingStores 15757224 # Number of conflicting stores.
314system.cpu.iq.iqInstsAdded 755181384 # Number of instructions added to the IQ (excludes non-spec)
315system.cpu.iq.iqNonSpecInstsAdded 3775400 # Number of non-speculative instructions added to the IQ
316system.cpu.iq.iqInstsIssued 665429696 # Number of instructions issued
317system.cpu.iq.iqSquashedInstsIssued 1394216 # Number of squashed instructions issued
318system.cpu.iq.iqSquashedInstsExamined 187494219 # Number of squashed instructions iterated over during squash; mainly for profiling
319system.cpu.iq.iqSquashedOperandsExamined 479993782 # Number of squashed operands that are examined and possibly removed from graph
320system.cpu.iq.iqSquashedNonSpecRemoved 797768 # Number of squashed non-spec instructions that were removed
321system.cpu.iq.issued_per_cycle::samples 392530086 # Number of insts issued each cycle
322system.cpu.iq.issued_per_cycle::mean 1.695232 # Number of insts issued each cycle
323system.cpu.iq.issued_per_cycle::stdev 1.736006 # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::0 137153831 34.94% 34.94% # Number of insts issued each cycle
326system.cpu.iq.issued_per_cycle::1 69768231 17.77% 52.71% # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::2 71497423 18.21% 70.93% # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::3 53360624 13.59% 84.52% # Number of insts issued each cycle
329system.cpu.iq.issued_per_cycle::4 31181551 7.94% 92.47% # Number of insts issued each cycle
330system.cpu.iq.issued_per_cycle::5 16101363 4.10% 96.57% # Number of insts issued each cycle
331system.cpu.iq.issued_per_cycle::6 8735003 2.23% 98.79% # Number of insts issued each cycle
332system.cpu.iq.issued_per_cycle::7 2914770 0.74% 99.54% # Number of insts issued each cycle
333system.cpu.iq.issued_per_cycle::8 1817290 0.46% 100.00% # Number of insts issued each cycle
334system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::total 392530086 # Number of insts issued each cycle
338system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
339system.cpu.iq.fu_full::IntAlu 481185 5.01% 5.01% # attempts to use FU when none available
340system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available
341system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available
342system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available
343system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available
344system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available
345system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available
346system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available
347system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
348system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available
349system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available
350system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available
351system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available
352system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available
353system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available
354system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available
355system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available
356system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
368system.cpu.iq.fu_full::MemRead 6545421 68.20% 73.22% # attempts to use FU when none available
369system.cpu.iq.fu_full::MemWrite 2570325 26.78% 100.00% # attempts to use FU when none available
370system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
371system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
372system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
373system.cpu.iq.FU_type_0::IntAlu 447832117 67.30% 67.30% # Type of FU issued
374system.cpu.iq.FU_type_0::IntMult 383268 0.06% 67.36% # Type of FU issued
375system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
376system.cpu.iq.FU_type_0::FloatAdd 86 0.00% 67.36% # Type of FU issued
377system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
378system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
379system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
380system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
381system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued
388system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued
389system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
402system.cpu.iq.FU_type_0::MemRead 153411814 23.05% 90.41% # Type of FU issued
403system.cpu.iq.FU_type_0::MemWrite 63802408 9.59% 100.00% # Type of FU issued
404system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
405system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
406system.cpu.iq.FU_type_0::total 665429696 # Type of FU issued
407system.cpu.iq.rate 1.664863 # Inst issue rate
408system.cpu.iq.fu_busy_cnt 9596931 # FU busy when requested
409system.cpu.iq.fu_busy_rate 0.014422 # FU busy rate (busy events/executed inst)
410system.cpu.iq.int_inst_queue_reads 1734380418 # Number of integer instruction queue reads
411system.cpu.iq.int_inst_queue_writes 947258082 # Number of integer instruction queue writes
412system.cpu.iq.int_inst_queue_wakeup_accesses 646140584 # Number of integer instruction queue wakeup accesses
413system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads
414system.cpu.iq.fp_inst_queue_writes 274 # Number of floating instruction queue writes
415system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
416system.cpu.iq.int_alu_accesses 675026522 # Number of integer alu accesses
417system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses
418system.cpu.iew.lsq.thread0.forwLoads 8582869 # Number of loads that had data forwarded from stores
419system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
420system.cpu.iew.lsq.thread0.squashedLoads 44257287 # Number of loads squashed
421system.cpu.iew.lsq.thread0.ignoredResponses 42197 # Number of memory responses ignored because the instruction is squashed
422system.cpu.iew.lsq.thread0.memOrderViolation 811123 # Number of memory ordering violations
423system.cpu.iew.lsq.thread0.squashedStores 16642088 # Number of stores squashed
424system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
425system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
426system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled
427system.cpu.iew.lsq.thread0.cacheBlocked 4090 # Number of times an access to memory failed due to the cache being blocked
428system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
429system.cpu.iew.iewSquashCycles 27558513 # Number of cycles IEW is squashing
430system.cpu.iew.iewBlockCycles 4987467 # Number of cycles IEW is blocking
431system.cpu.iew.iewUnblockCycles 372691 # Number of cycles IEW is unblocking
432system.cpu.iew.iewDispatchedInsts 760516980 # Number of instructions dispatched to IQ
433system.cpu.iew.iewDispSquashedInsts 1117257 # Number of squashed instructions skipped by dispatch
434system.cpu.iew.iewDispLoadInsts 170286842 # Number of dispatched load instructions
435system.cpu.iew.iewDispStoreInsts 73502565 # Number of dispatched store instructions
436system.cpu.iew.iewDispNonSpecInsts 2286858 # Number of dispatched non-speculative instructions
437system.cpu.iew.iewIQFullEvents 219486 # Number of times the IQ has become full, causing a stall
438system.cpu.iew.iewLSQFullEvents 11052 # Number of times the LSQ has become full, causing a stall
439system.cpu.iew.memOrderViolationEvents 811123 # Number of memory order violations
440system.cpu.iew.predictedTakenIncorrect 4340984 # Number of branches that were predicted taken incorrectly
441system.cpu.iew.predictedNotTakenIncorrect 4003792 # Number of branches that were predicted not taken incorrectly
442system.cpu.iew.branchMispredicts 8344776 # Number of branch mispredicts detected at execute
443system.cpu.iew.iewExecutedInsts 656001968 # Number of executed instructions
444system.cpu.iew.iewExecLoadInsts 150122200 # Number of load instructions executed
445system.cpu.iew.iewExecSquashedInsts 9427728 # Number of squashed instructions skipped in execute
446system.cpu.iew.exec_swp 0 # number of swp insts executed
447system.cpu.iew.exec_nop 1560196 # number of nop insts executed
448system.cpu.iew.exec_refs 212633148 # number of memory reference insts executed
449system.cpu.iew.exec_branches 138504923 # Number of branches executed
450system.cpu.iew.exec_stores 62510948 # Number of stores executed
451system.cpu.iew.exec_rate 1.641276 # Inst execution rate
452system.cpu.iew.wb_sent 651119979 # cumulative count of insts sent to commit
453system.cpu.iew.wb_count 646140600 # cumulative count of insts written-back
454system.cpu.iew.wb_producers 374813030 # num instructions producing a value
455system.cpu.iew.wb_consumers 646558310 # num instructions consuming a value
456system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
457system.cpu.iew.wb_rate 1.616603 # insts written-back per cycle
458system.cpu.iew.wb_fanout 0.579705 # average fanout of values written-back
459system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
460system.cpu.commit.commitSquashedInsts 189575186 # The number of squashed insts skipped by commit
461system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
462system.cpu.commit.branchMispredicts 7194795 # The number of times a branch was mispredicted
463system.cpu.commit.committed_per_cycle::samples 364971573 # Number of insts commited each cycle
464system.cpu.commit.committed_per_cycle::mean 1.564418 # Number of insts commited each cycle
465system.cpu.commit.committed_per_cycle::stdev 2.233675 # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::0 157304822 43.10% 43.10% # Number of insts commited each cycle
468system.cpu.commit.committed_per_cycle::1 98491978 26.99% 70.09% # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::2 33807803 9.26% 79.35% # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::3 18748044 5.14% 84.49% # Number of insts commited each cycle
471system.cpu.commit.committed_per_cycle::4 16202992 4.44% 88.93% # Number of insts commited each cycle
472system.cpu.commit.committed_per_cycle::5 7453577 2.04% 90.97% # Number of insts commited each cycle
473system.cpu.commit.committed_per_cycle::6 6993904 1.92% 92.88% # Number of insts commited each cycle
474system.cpu.commit.committed_per_cycle::7 3174450 0.87% 93.75% # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::8 22794003 6.25% 100.00% # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::total 364971573 # Number of insts commited each cycle
480system.cpu.commit.committedInsts 506581607 # Number of instructions committed
481system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
482system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
483system.cpu.commit.refs 182890032 # Number of memory references committed
484system.cpu.commit.loads 126029555 # Number of loads committed
485system.cpu.commit.membars 1488542 # Number of memory barriers committed
486system.cpu.commit.branches 121548301 # Number of branches committed
487system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
488system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
489system.cpu.commit.function_calls 9757362 # Number of function calls committed.
490system.cpu.commit.bw_lim_events 22794003 # number cycles where commit BW limit reached
491system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
492system.cpu.rob.rob_reads 1102713785 # The number of ROB reads
493system.cpu.rob.rob_writes 1548767048 # The number of ROB writes
494system.cpu.timesIdled 306858 # Number of times that the entire CPU went into an idle state and unscheduled itself
495system.cpu.idleCycles 7160189 # Total number of cycles that the CPU has spent unscheduled due to idling
496system.cpu.committedInsts 505237723 # Number of Instructions Simulated
497system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
498system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
499system.cpu.cpi 0.791093 # CPI: Cycles Per Instruction
500system.cpu.cpi_total 0.791093 # CPI: Total CPI of All Threads
501system.cpu.ipc 1.264073 # IPC: Instructions Per Cycle
502system.cpu.ipc_total 1.264073 # IPC: Total IPC of All Threads
503system.cpu.int_regfile_reads 3059184222 # number of integer regfile reads
504system.cpu.int_regfile_writes 752090779 # number of integer regfile writes
505system.cpu.fp_regfile_reads 16 # number of floating regfile reads
506system.cpu.misc_regfile_reads 210880028 # number of misc regfile reads
507system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
508system.cpu.icache.replacements 15058 # number of replacements
509system.cpu.icache.tagsinuse 1101.681539 # Cycle average of tags in use
510system.cpu.icache.total_refs 114506253 # Total number of references to valid blocks.
511system.cpu.icache.sampled_refs 16915 # Sample count of references to valid blocks.
512system.cpu.icache.avg_refs 6769.509489 # Average number of references to valid blocks.
513system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
514system.cpu.icache.occ_blocks::cpu.inst 1101.681539 # Average occupied blocks per requestor
515system.cpu.icache.occ_percent::cpu.inst 0.537930 # Average percentage of cache occupancy
516system.cpu.icache.occ_percent::total 0.537930 # Average percentage of cache occupancy
517system.cpu.icache.ReadReq_hits::cpu.inst 114506253 # number of ReadReq hits
518system.cpu.icache.ReadReq_hits::total 114506253 # number of ReadReq hits
519system.cpu.icache.demand_hits::cpu.inst 114506253 # number of demand (read+write) hits
520system.cpu.icache.demand_hits::total 114506253 # number of demand (read+write) hits
521system.cpu.icache.overall_hits::cpu.inst 114506253 # number of overall hits
522system.cpu.icache.overall_hits::total 114506253 # number of overall hits
523system.cpu.icache.ReadReq_misses::cpu.inst 21101 # number of ReadReq misses
524system.cpu.icache.ReadReq_misses::total 21101 # number of ReadReq misses
525system.cpu.icache.demand_misses::cpu.inst 21101 # number of demand (read+write) misses
526system.cpu.icache.demand_misses::total 21101 # number of demand (read+write) misses
527system.cpu.icache.overall_misses::cpu.inst 21101 # number of overall misses
528system.cpu.icache.overall_misses::total 21101 # number of overall misses
529system.cpu.icache.ReadReq_miss_latency::cpu.inst 452371500 # number of ReadReq miss cycles
530system.cpu.icache.ReadReq_miss_latency::total 452371500 # number of ReadReq miss cycles
531system.cpu.icache.demand_miss_latency::cpu.inst 452371500 # number of demand (read+write) miss cycles
532system.cpu.icache.demand_miss_latency::total 452371500 # number of demand (read+write) miss cycles
533system.cpu.icache.overall_miss_latency::cpu.inst 452371500 # number of overall miss cycles
534system.cpu.icache.overall_miss_latency::total 452371500 # number of overall miss cycles
535system.cpu.icache.ReadReq_accesses::cpu.inst 114527354 # number of ReadReq accesses(hits+misses)
536system.cpu.icache.ReadReq_accesses::total 114527354 # number of ReadReq accesses(hits+misses)
537system.cpu.icache.demand_accesses::cpu.inst 114527354 # number of demand (read+write) accesses
538system.cpu.icache.demand_accesses::total 114527354 # number of demand (read+write) accesses
539system.cpu.icache.overall_accesses::cpu.inst 114527354 # number of overall (read+write) accesses
540system.cpu.icache.overall_accesses::total 114527354 # number of overall (read+write) accesses
541system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses
542system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses
543system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses
544system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses
545system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses
546system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses
547system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21438.391545 # average ReadReq miss latency
548system.cpu.icache.ReadReq_avg_miss_latency::total 21438.391545 # average ReadReq miss latency
549system.cpu.icache.demand_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency
550system.cpu.icache.demand_avg_miss_latency::total 21438.391545 # average overall miss latency
551system.cpu.icache.overall_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency
552system.cpu.icache.overall_avg_miss_latency::total 21438.391545 # average overall miss latency
553system.cpu.icache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked
554system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
555system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
556system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
557system.cpu.icache.avg_blocked_cycles::no_mshrs 35.700000 # average number of cycles each access was blocked
558system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
559system.cpu.icache.fast_writes 0 # number of fast writes performed
560system.cpu.icache.cache_copies 0 # number of cache copies performed
561system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4104 # number of ReadReq MSHR hits
562system.cpu.icache.ReadReq_mshr_hits::total 4104 # number of ReadReq MSHR hits
563system.cpu.icache.demand_mshr_hits::cpu.inst 4104 # number of demand (read+write) MSHR hits
564system.cpu.icache.demand_mshr_hits::total 4104 # number of demand (read+write) MSHR hits
565system.cpu.icache.overall_mshr_hits::cpu.inst 4104 # number of overall MSHR hits
566system.cpu.icache.overall_mshr_hits::total 4104 # number of overall MSHR hits
567system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16997 # number of ReadReq MSHR misses
568system.cpu.icache.ReadReq_mshr_misses::total 16997 # number of ReadReq MSHR misses
569system.cpu.icache.demand_mshr_misses::cpu.inst 16997 # number of demand (read+write) MSHR misses
570system.cpu.icache.demand_mshr_misses::total 16997 # number of demand (read+write) MSHR misses
571system.cpu.icache.overall_mshr_misses::cpu.inst 16997 # number of overall MSHR misses
572system.cpu.icache.overall_mshr_misses::total 16997 # number of overall MSHR misses
573system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339326500 # number of ReadReq MSHR miss cycles
574system.cpu.icache.ReadReq_mshr_miss_latency::total 339326500 # number of ReadReq MSHR miss cycles
575system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339326500 # number of demand (read+write) MSHR miss cycles
576system.cpu.icache.demand_mshr_miss_latency::total 339326500 # number of demand (read+write) MSHR miss cycles
577system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339326500 # number of overall MSHR miss cycles
578system.cpu.icache.overall_mshr_miss_latency::total 339326500 # number of overall MSHR miss cycles
579system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses
580system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses
581system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses
582system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses
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585system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19963.905395 # average ReadReq mshr miss latency
586system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19963.905395 # average ReadReq mshr miss latency
587system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency
588system.cpu.icache.demand_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency
589system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency
590system.cpu.icache.overall_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency
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599system.cpu.l2cache.occ_blocks::cpu.inst 365.807656 # Average occupied blocks per requestor
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609system.cpu.l2cache.Writeback_hits::total 1110730 # number of Writeback hits
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611system.cpu.l2cache.UpgradeReq_hits::total 70 # number of UpgradeReq hits
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624system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses
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663system.cpu.l2cache.UpgradeReq_miss_rate::total 0.135802 # miss rate for UpgradeReq accesses
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665system.cpu.l2cache.ReadExReq_miss_rate::total 0.290371 # miss rate for ReadExReq accesses
666system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200817 # miss rate for demand accesses
667system.cpu.l2cache.demand_miss_rate::cpu.data 0.121003 # miss rate for demand accesses
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670system.cpu.l2cache.overall_miss_rate::cpu.data 0.121003 # miss rate for overall accesses
671system.cpu.l2cache.overall_miss_rate::total 0.122115 # miss rate for overall accesses
672system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55008.839128 # average ReadReq miss latency
673system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58544.481490 # average ReadReq miss latency
674system.cpu.l2cache.ReadReq_avg_miss_latency::total 58288.531269 # average ReadReq miss latency
675system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53323.861897 # average ReadExReq miss latency
676system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53323.861897 # average ReadExReq miss latency
677system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55008.839128 # average overall miss latency
678system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54892.099574 # average overall miss latency
679system.cpu.l2cache.demand_avg_miss_latency::total 54894.773606 # average overall miss latency
680system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55008.839128 # average overall miss latency
681system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54892.099574 # average overall miss latency
682system.cpu.l2cache.overall_avg_miss_latency::total 54894.773606 # average overall miss latency
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684system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
685system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
686system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
687system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
688system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
689system.cpu.l2cache.fast_writes 0 # number of fast writes performed
690system.cpu.l2cache.cache_copies 0 # number of cache copies performed
691system.cpu.l2cache.writebacks::writebacks 97626 # number of writebacks
692system.cpu.l2cache.writebacks::total 97626 # number of writebacks
693system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
694system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 25 # number of ReadReq MSHR hits
695system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits
696system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
697system.cpu.l2cache.demand_mshr_hits::cpu.data 25 # number of demand (read+write) MSHR hits
698system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits
699system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
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701system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits
702system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3389 # number of ReadReq MSHR misses
703system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43465 # number of ReadReq MSHR misses
704system.cpu.l2cache.ReadReq_mshr_misses::total 46854 # number of ReadReq MSHR misses
705system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
706system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
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719system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115510 # number of UpgradeReq MSHR miss cycles
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721system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113084396 # number of ReadExReq MSHR miss cycles
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723system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6103554515 # number of demand (read+write) MSHR miss cycles
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725system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453810 # number of overall MSHR miss cycles
726system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6103554515 # number of overall MSHR miss cycles
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728system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200521 # mshr miss rate for ReadReq accesses
729system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051277 # mshr miss rate for ReadReq accesses
730system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054194 # mshr miss rate for ReadReq accesses
731system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.135802 # mshr miss rate for UpgradeReq accesses
732system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.135802 # mshr miss rate for UpgradeReq accesses
733system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290371 # mshr miss rate for ReadExReq accesses
734system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290371 # mshr miss rate for ReadExReq accesses
735system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200521 # mshr miss rate for demand accesses
736system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120982 # mshr miss rate for demand accesses
737system.cpu.l2cache.demand_mshr_miss_rate::total 0.122090 # mshr miss rate for demand accesses
738system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200521 # mshr miss rate for overall accesses
739system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120982 # mshr miss rate for overall accesses
740system.cpu.l2cache.overall_mshr_miss_rate::total 0.122090 # mshr miss rate for overall accesses
741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42329.244615 # average ReadReq mshr miss latency
742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45794.780145 # average ReadReq mshr miss latency
743system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45544.114249 # average ReadReq mshr miss latency
744system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.909091 # average UpgradeReq mshr miss latency
745system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.909091 # average UpgradeReq mshr miss latency
746system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.216217 # average ReadExReq mshr miss latency
747system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.216217 # average ReadExReq mshr miss latency
748system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42329.244615 # average overall mshr miss latency
749system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42165.597125 # average overall mshr miss latency
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751system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42329.244615 # average overall mshr miss latency
752system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42165.597125 # average overall mshr miss latency
753system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42169.340864 # average overall mshr miss latency
754system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
755system.cpu.dcache.replacements 1192376 # number of replacements
756system.cpu.dcache.tagsinuse 4058.257289 # Cycle average of tags in use
757system.cpu.dcache.total_refs 190193687 # Total number of references to valid blocks.
758system.cpu.dcache.sampled_refs 1196472 # Sample count of references to valid blocks.
759system.cpu.dcache.avg_refs 158.962088 # Average number of references to valid blocks.
760system.cpu.dcache.warmup_cycle 4128824000 # Cycle when the warmup percentage was hit.
761system.cpu.dcache.occ_blocks::cpu.data 4058.257289 # Average occupied blocks per requestor
762system.cpu.dcache.occ_percent::cpu.data 0.990785 # Average percentage of cache occupancy
763system.cpu.dcache.occ_percent::total 0.990785 # Average percentage of cache occupancy
764system.cpu.dcache.ReadReq_hits::cpu.data 136223717 # number of ReadReq hits
765system.cpu.dcache.ReadReq_hits::total 136223717 # number of ReadReq hits
766system.cpu.dcache.WriteReq_hits::cpu.data 50992367 # number of WriteReq hits
767system.cpu.dcache.WriteReq_hits::total 50992367 # number of WriteReq hits
768system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488803 # number of LoadLockedReq hits
769system.cpu.dcache.LoadLockedReq_hits::total 1488803 # number of LoadLockedReq hits
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771system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
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775system.cpu.dcache.overall_hits::total 187216084 # number of overall hits
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777system.cpu.dcache.ReadReq_misses::total 1697690 # number of ReadReq misses
778system.cpu.dcache.WriteReq_misses::cpu.data 3246939 # number of WriteReq misses
779system.cpu.dcache.WriteReq_misses::total 3246939 # number of WriteReq misses
780system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses
781system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses
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783system.cpu.dcache.demand_misses::total 4944629 # number of demand (read+write) misses
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785system.cpu.dcache.overall_misses::total 4944629 # number of overall misses
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787system.cpu.dcache.ReadReq_miss_latency::total 26054770000 # number of ReadReq miss cycles
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789system.cpu.dcache.WriteReq_miss_latency::total 58807860452 # number of WriteReq miss cycles
790system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 537000 # number of LoadLockedReq miss cycles
791system.cpu.dcache.LoadLockedReq_miss_latency::total 537000 # number of LoadLockedReq miss cycles
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793system.cpu.dcache.demand_miss_latency::total 84862630452 # number of demand (read+write) miss cycles
794system.cpu.dcache.overall_miss_latency::cpu.data 84862630452 # number of overall miss cycles
795system.cpu.dcache.overall_miss_latency::total 84862630452 # number of overall miss cycles
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797system.cpu.dcache.ReadReq_accesses::total 137921407 # number of ReadReq accesses(hits+misses)
798system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
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801system.cpu.dcache.LoadLockedReq_accesses::total 1488838 # number of LoadLockedReq accesses(hits+misses)
802system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
803system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
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809system.cpu.dcache.ReadReq_miss_rate::total 0.012309 # miss rate for ReadReq accesses
810system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059863 # miss rate for WriteReq accesses
811system.cpu.dcache.WriteReq_miss_rate::total 0.059863 # miss rate for WriteReq accesses
812system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses
813system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses
814system.cpu.dcache.demand_miss_rate::cpu.data 0.025732 # miss rate for demand accesses
815system.cpu.dcache.demand_miss_rate::total 0.025732 # miss rate for demand accesses
816system.cpu.dcache.overall_miss_rate::cpu.data 0.025732 # miss rate for overall accesses
817system.cpu.dcache.overall_miss_rate::total 0.025732 # miss rate for overall accesses
818system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15347.189416 # average ReadReq miss latency
819system.cpu.dcache.ReadReq_avg_miss_latency::total 15347.189416 # average ReadReq miss latency
820system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18111.784808 # average WriteReq miss latency
821system.cpu.dcache.WriteReq_avg_miss_latency::total 18111.784808 # average WriteReq miss latency
822system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15342.857143 # average LoadLockedReq miss latency
823system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15342.857143 # average LoadLockedReq miss latency
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825system.cpu.dcache.demand_avg_miss_latency::total 17162.588023 # average overall miss latency
826system.cpu.dcache.overall_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency
827system.cpu.dcache.overall_avg_miss_latency::total 17162.588023 # average overall miss latency
828system.cpu.dcache.blocked_cycles::no_mshrs 16266 # number of cycles access was blocked
829system.cpu.dcache.blocked_cycles::no_targets 14829 # number of cycles access was blocked
830system.cpu.dcache.blocked::no_mshrs 1654 # number of cycles access was blocked
831system.cpu.dcache.blocked::no_targets 595 # number of cycles access was blocked
832system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.834341 # average number of cycles each access was blocked
833system.cpu.dcache.avg_blocked_cycles::no_targets 24.922689 # average number of cycles each access was blocked
834system.cpu.dcache.fast_writes 0 # number of fast writes performed
835system.cpu.dcache.cache_copies 0 # number of cache copies performed
836system.cpu.dcache.writebacks::writebacks 1110730 # number of writebacks
837system.cpu.dcache.writebacks::total 1110730 # number of writebacks
838system.cpu.dcache.ReadReq_mshr_hits::cpu.data 849485 # number of ReadReq MSHR hits
839system.cpu.dcache.ReadReq_mshr_hits::total 849485 # number of ReadReq MSHR hits
840system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898590 # number of WriteReq MSHR hits
841system.cpu.dcache.WriteReq_mshr_hits::total 2898590 # number of WriteReq MSHR hits
842system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits
843system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits
844system.cpu.dcache.demand_mshr_hits::cpu.data 3748075 # number of demand (read+write) MSHR hits
845system.cpu.dcache.demand_mshr_hits::total 3748075 # number of demand (read+write) MSHR hits
846system.cpu.dcache.overall_mshr_hits::cpu.data 3748075 # number of overall MSHR hits
847system.cpu.dcache.overall_mshr_hits::total 3748075 # number of overall MSHR hits
848system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848205 # number of ReadReq MSHR misses
849system.cpu.dcache.ReadReq_mshr_misses::total 848205 # number of ReadReq MSHR misses
850system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348349 # number of WriteReq MSHR misses
851system.cpu.dcache.WriteReq_mshr_misses::total 348349 # number of WriteReq MSHR misses
852system.cpu.dcache.demand_mshr_misses::cpu.data 1196554 # number of demand (read+write) MSHR misses
853system.cpu.dcache.demand_mshr_misses::total 1196554 # number of demand (read+write) MSHR misses
854system.cpu.dcache.overall_mshr_misses::cpu.data 1196554 # number of overall MSHR misses
855system.cpu.dcache.overall_mshr_misses::total 1196554 # number of overall MSHR misses
856system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11474356500 # number of ReadReq MSHR miss cycles
857system.cpu.dcache.ReadReq_mshr_miss_latency::total 11474356500 # number of ReadReq MSHR miss cycles
858system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8274514996 # number of WriteReq MSHR miss cycles
859system.cpu.dcache.WriteReq_mshr_miss_latency::total 8274514996 # number of WriteReq MSHR miss cycles
860system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19748871496 # number of demand (read+write) MSHR miss cycles
861system.cpu.dcache.demand_mshr_miss_latency::total 19748871496 # number of demand (read+write) MSHR miss cycles
862system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19748871496 # number of overall MSHR miss cycles
863system.cpu.dcache.overall_mshr_miss_latency::total 19748871496 # number of overall MSHR miss cycles
864system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses
865system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses
866system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses
867system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses
868system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses
869system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses
870system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses
871system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses
872system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13527.810494 # average ReadReq mshr miss latency
873system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13527.810494 # average ReadReq mshr miss latency
874system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23753.520165 # average WriteReq mshr miss latency
875system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23753.520165 # average WriteReq mshr miss latency
876system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency
877system.cpu.dcache.demand_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency
878system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency
879system.cpu.dcache.overall_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency
880system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
881
882---------- End Simulation Statistics ----------
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