1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.202425 # Number of seconds simulated 4sim_ticks 202425052500 # Number of ticks simulated 5final_tick 202425052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 117924 # Simulator instruction rate (inst/s) 8host_op_rate 132952 # Simulator op (including micro ops) rate (op/s) --- 648 unchanged lines hidden (view full) --- 657system.cpu.commit.bw_lim_events 22814068 # number cycles where commit BW limit reached 658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 659system.cpu.rob.rob_reads 1104683035 # The number of ROB reads 660system.cpu.rob.rob_writes 1548546574 # The number of ROB writes 661system.cpu.timesIdled 329089 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 10240718 # Total number of cycles that the CPU has spent unscheduled due to idling 663system.cpu.committedInsts 505237723 # Number of Instructions Simulated 664system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated |
665system.cpu.cpi 0.801306 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 0.801306 # CPI: Total CPI of All Threads 667system.cpu.ipc 1.247962 # IPC: Instructions Per Cycle 668system.cpu.ipc_total 1.247962 # IPC: Total IPC of All Threads 669system.cpu.int_regfile_reads 3058680468 # number of integer regfile reads 670system.cpu.int_regfile_writes 751974394 # number of integer regfile writes 671system.cpu.fp_regfile_reads 16 # number of floating regfile reads 672system.cpu.misc_regfile_reads 237852228 # number of misc regfile reads --- 423 unchanged lines hidden --- |