3,5c3,5
< sim_seconds 0.202724 # Number of seconds simulated
< sim_ticks 202723760000 # Number of ticks simulated
< final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.202742 # Number of seconds simulated
> sim_ticks 202741893000 # Number of ticks simulated
> final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 119496 # Simulator instruction rate (inst/s)
< host_op_rate 134724 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 47946894 # Simulator tick rate (ticks/s)
< host_mem_usage 278932 # Number of bytes of host memory used
< host_seconds 4228.09 # Real time elapsed on the host
---
> host_inst_rate 95210 # Simulator instruction rate (inst/s)
> host_op_rate 107343 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 38205910 # Simulator tick rate (ticks/s)
> host_mem_usage 298452 # Number of bytes of host memory used
> host_seconds 5306.56 # Real time elapsed on the host
14,46c14,46
< system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 148203 # Number of read requests accepted
< system.physmem.writeReqs 97674 # Number of write requests accepted
< system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 148209 # Number of read requests accepted
> system.physmem.writeReqs 97655 # Number of write requests accepted
> system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue
48,62c48,62
< system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 9589 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9263 # Per bank write bursts
< system.physmem.perBankRdBursts::2 9230 # Per bank write bursts
< system.physmem.perBankRdBursts::3 8983 # Per bank write bursts
< system.physmem.perBankRdBursts::4 9781 # Per bank write bursts
< system.physmem.perBankRdBursts::5 9608 # Per bank write bursts
< system.physmem.perBankRdBursts::6 9123 # Per bank write bursts
< system.physmem.perBankRdBursts::7 8333 # Per bank write bursts
< system.physmem.perBankRdBursts::8 8801 # Per bank write bursts
< system.physmem.perBankRdBursts::9 8921 # Per bank write bursts
< system.physmem.perBankRdBursts::10 8939 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9732 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9670 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9771 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 9585 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9243 # Per bank write bursts
> system.physmem.perBankRdBursts::2 9257 # Per bank write bursts
> system.physmem.perBankRdBursts::3 8972 # Per bank write bursts
> system.physmem.perBankRdBursts::4 9761 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9639 # Per bank write bursts
> system.physmem.perBankRdBursts::6 9125 # Per bank write bursts
> system.physmem.perBankRdBursts::7 8321 # Per bank write bursts
> system.physmem.perBankRdBursts::8 8799 # Per bank write bursts
> system.physmem.perBankRdBursts::9 8911 # Per bank write bursts
> system.physmem.perBankRdBursts::10 8951 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9736 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9644 # Per bank write bursts
> system.physmem.perBankRdBursts::13 9766 # Per bank write bursts
64,72c64,72
< system.physmem.perBankRdBursts::15 9431 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6268 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6168 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6085 # Per bank write bursts
< system.physmem.perBankWrBursts::3 5885 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6259 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6263 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6041 # Per bank write bursts
< system.physmem.perBankWrBursts::7 5560 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 9461 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6262 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6160 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6087 # Per bank write bursts
> system.physmem.perBankWrBursts::3 5881 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6253 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6276 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6048 # Per bank write bursts
> system.physmem.perBankWrBursts::7 5555 # Per bank write bursts
74,80c74,80
< system.physmem.perBankWrBursts::9 5905 # Per bank write bursts
< system.physmem.perBankWrBursts::10 5991 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6522 # Per bank write bursts
< system.physmem.perBankWrBursts::12 6386 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6332 # Per bank write bursts
< system.physmem.perBankWrBursts::14 6056 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6134 # Per bank write bursts
---
> system.physmem.perBankWrBursts::9 5907 # Per bank write bursts
> system.physmem.perBankWrBursts::10 5994 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6518 # Per bank write bursts
> system.physmem.perBankWrBursts::12 6370 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6328 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6055 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6145 # Per bank write bursts
83c83
< system.physmem.totGap 202723740000 # Total gap between requests
---
> system.physmem.totGap 202741873000 # Total gap between requests
90c90
< system.physmem.readPktSize::6 148203 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 148209 # Read request sizes (log2)
97,104c97,104
< system.physmem.writePktSize::6 97674 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 97655 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
130,132c130,132
< system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see
134,140c134,140
< system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see
142,213c142,213
< system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation
215,221c215,221
< system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation
225d224
< system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation
228,233c227,232
< system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation
235c234
< system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation
239,254c238,252
< system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation
< system.physmem.totQLat 1733533250 # Total ticks spent queuing
< system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks
< system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation
> system.physmem.totQLat 1735354000 # Total ticks spent queuing
> system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks
> system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst
256c254
< system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst
260c258
< system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s
266,272c264,270
< system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing
< system.physmem.readRowHits 118615 # Number of row buffer hits during reads
< system.physmem.writeRowHits 57916 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes
< system.physmem.avgGap 824492.49 # Average gap between requests
< system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined
---
> system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing
> system.physmem.readRowHits 118629 # Number of row buffer hits during reads
> system.physmem.writeRowHits 57942 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes
> system.physmem.avgGap 824609.84 # Average gap between requests
> system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined
274,286c272,284
< system.membus.throughput 77623185 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 46911 # Transaction distribution
< system.membus.trans_dist::ReadResp 46910 # Transaction distribution
< system.membus.trans_dist::Writeback 97674 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 11 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 11 # Transaction distribution
< system.membus.trans_dist::ReadExReq 101292 # Transaction distribution
< system.membus.trans_dist::ReadExResp 101292 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 15736064 # Total data (bytes)
---
> system.membus.throughput 77612139 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 46927 # Transaction distribution
> system.membus.trans_dist::ReadResp 46926 # Transaction distribution
> system.membus.trans_dist::Writeback 97655 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 9 # Transaction distribution
> system.membus.trans_dist::ReadExReq 101282 # Transaction distribution
> system.membus.trans_dist::ReadExResp 101282 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 15735232 # Total data (bytes)
288c286
< system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks)
290c288
< system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks)
292,296c290,294
< system.cpu.branchPred.lookups 182800422 # Number of BP lookups
< system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits
---
> system.cpu.branchPred.lookups 182821881 # Number of BP lookups
> system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits
298,300c296,298
< system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions.
344c342
< system.cpu.numCycles 405447521 # number of cpu cycles simulated
---
> system.cpu.numCycles 405483787 # number of cpu cycles simulated
347,361c345,359
< system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total)
363,371c361,369
< system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total)
375,401c373,399
< system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups
403,420c401,418
< system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle
422,430c420,428
< system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle
434c432
< system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle
436c434
< system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available
465,466c463,464
< system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available
470,471c468,469
< system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued
473c471
< system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued
499,500c497,498
< system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued
503,510c501,508
< system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued
< system.cpu.iq.rate 1.641040 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads
---
> system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued
> system.cpu.iq.rate 1.640858 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
513,515c511,513
< system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores
517,520c515,518
< system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed
523,524c521,522
< system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked
526,542c524,540
< system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute
544,552c542,550
< system.cpu.iew.exec_nop 1559155 # number of nop insts executed
< system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed
< system.cpu.iew.exec_branches 138495848 # Number of branches executed
< system.cpu.iew.exec_stores 62487508 # Number of stores executed
< system.cpu.iew.exec_rate 1.617786 # Inst execution rate
< system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 374730881 # num instructions producing a value
< system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 1558919 # number of nop insts executed
> system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed
> system.cpu.iew.exec_branches 138505177 # Number of branches executed
> system.cpu.iew.exec_stores 62475461 # Number of stores executed
> system.cpu.iew.exec_rate 1.617619 # Inst execution rate
> system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 374710129 # num instructions producing a value
> system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value
554,555c552,553
< system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back
557c555
< system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit
559,562c557,560
< system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle
564,572c562,570
< system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle
576c574
< system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle
587c585
< system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached
589,592c587,590
< system.cpu.rob.rob_reads 1104768676 # The number of ROB reads
< system.cpu.rob.rob_writes 1548495185 # The number of ROB writes
< system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 1104828701 # The number of ROB reads
> system.cpu.rob.rob_writes 1548619548 # The number of ROB writes
> system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling
596,601c594,599
< system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads
< system.cpu.int_regfile_writes 752016829 # number of integer regfile writes
---
> system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads
> system.cpu.int_regfile_writes 752019512 # number of integer regfile writes
603c601
< system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads
605,621c603,619
< system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes)
> system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes)
> system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks)
623c621
< system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks)
625c623
< system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks)
627,631c625,629
< system.cpu.icache.tags.replacements 15073 # number of replacements
< system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 15017 # number of replacements
> system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks.
633,672c631,670
< system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits
< system.cpu.icache.overall_hits::total 114510320 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses
< system.cpu.icache.overall_misses::total 21232 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits
> system.cpu.icache.overall_hits::total 114523215 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses
> system.cpu.icache.overall_misses::total 21116 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked
674c672
< system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
676c674
< system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked
680,709c678,707
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4215 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 4215 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 4215 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 4215 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 4215 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 4215 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17017 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 17017 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 17017 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 17017 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 17017 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 17017 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 416333765 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 416333765 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 416333765 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 416333765 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 416333765 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 416333765 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24465.755715 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24465.755715 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency
711,805c709,799
< system.cpu.l2cache.tags.replacements 115458 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 27089.677773 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1781255 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 146702 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.141995 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 102544951000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23009.492156 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 363.276336 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.909282 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.702194 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011086 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.113431 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.826711 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 13516 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 804499 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 818015 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1111085 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1111085 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 247576 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 247576 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 13516 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1052075 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1065591 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 13516 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1052075 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1065591 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3400 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 43535 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 46935 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3400 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 144828 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3400 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 144828 # number of overall misses
< system.cpu.l2cache.overall_misses::total 148228 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263796250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3483365500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3747161750 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7556144249 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7556144249 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 263796250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11039509749 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11303305999 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 263796250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11039509749 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11303305999 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 16916 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 848034 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 864950 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1111085 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1111085 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 348869 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 348869 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 16916 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1196903 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1213819 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 16916 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1196903 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1213819 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200993 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051336 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.054263 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119048 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119048 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290347 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.290347 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200993 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.121002 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.122117 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200993 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency
---
> system.cpu.l2cache.tags.replacements 115463 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 27089.747444 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1781862 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 146718 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.144808 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 23009.564484 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.930795 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3719.252164 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1110997 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1110997 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 57 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 57 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 13491 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1051959 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1065450 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 13491 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1051959 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1065450 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3369 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 43584 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 46953 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 3369 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 144867 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3369 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 144867 # number of overall misses
> system.cpu.l2cache.overall_misses::total 148236 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260130750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3496707000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3756837750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7547454999 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7547454999 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 260130750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11044161999 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11304292749 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 260130750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11044161999 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11304292749 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 16860 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 847968 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 864828 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1110997 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1110997 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 65 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 65 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 348858 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 348858 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 16860 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1196826 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1213686 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 16860 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1196826 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1213686 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.199822 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051398 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.054292 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.123077 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.123077 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290327 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.290327 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199822 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.121043 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199822 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.121043 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77213.045414 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80229.143722 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 80012.730816 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74518.477918 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74518.477918 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 76258.754614 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 76258.754614 # average overall miss latency
814,815c808,809
< system.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks
< system.cpu.l2cache.writebacks::total 97674 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 97655 # number of writebacks
> system.cpu.l2cache.writebacks::total 97655 # number of writebacks
817,818c811,812
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
820,821c814,815
< system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
823,866c817,860
< system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119048 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119048 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290347 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290347 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.122097 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.122097 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3364 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43563 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 46927 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3364 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 144846 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 148210 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3364 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 144846 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 148210 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 217499500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2949813250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3167312750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262853501 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262853501 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217499500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9212666751 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9430166251 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217499500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9212666751 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9430166251 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051373 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054262 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.123077 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.123077 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290327 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290327 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.122116 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.122116 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64655.023781 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67713.730689 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67494.464807 # average ReadReq mshr miss latency
869,876c863,870
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency
878,882c872,876
< system.cpu.dcache.tags.replacements 1192807 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 1192730 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks.
884,892c878,886
< system.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits
895,920c889,914
< system.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits
< system.cpu.dcache.overall_hits::total 187221113 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses
< system.cpu.dcache.overall_misses::total 4954972 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits
> system.cpu.dcache.overall_hits::total 187223724 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses
> system.cpu.dcache.overall_misses::total 4951929 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses)
923,924c917,918
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses)
927,953c921,947
< system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked
955,956c949,950
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked
959,986c953,980
< system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks
< system.cpu.dcache.writebacks::total 1111085 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles
---
> system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks
> system.cpu.dcache.writebacks::total 1110997 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles
989,1002c983,996
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency