3,5c3,5
< sim_seconds 0.199960 # Number of seconds simulated
< sim_ticks 199959919500 # Number of ticks simulated
< final_tick 199959919500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.199930 # Number of seconds simulated
> sim_ticks 199930442500 # Number of ticks simulated
> final_tick 199930442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 126038 # Simulator instruction rate (inst/s)
< host_op_rate 142101 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 49882714 # Simulator tick rate (ticks/s)
< host_mem_usage 278340 # Number of bytes of host memory used
< host_seconds 4008.60 # Real time elapsed on the host
---
> host_inst_rate 127290 # Simulator instruction rate (inst/s)
> host_op_rate 143512 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 50370674 # Simulator tick rate (ticks/s)
> host_mem_usage 265580 # Number of bytes of host memory used
> host_seconds 3969.18 # Real time elapsed on the host
14,69c14,69
< system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9260800 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9477568 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6246592 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6246592 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 144700 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 148087 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 97603 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 97603 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1084057 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 46313281 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 47397339 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1084057 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1084057 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 31239220 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 31239220 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 31239220 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1084057 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 46313281 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 78636559 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 148088 # Total number of read requests seen
< system.physmem.writeReqs 97603 # Total number of write requests seen
< system.physmem.cpureqs 247534 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 9477568 # Total number of bytes read from memory
< system.physmem.bytesWritten 6246592 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 9477568 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 6246592 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 77 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 6 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 9156 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 9528 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 9506 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 9385 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 9094 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 9054 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 9284 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 9051 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 9215 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 9026 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 5949 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 5987 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 6274 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 6476 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 6181 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 6228 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 6222 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 6039 # Track writes on a per bank basis
---
> system.physmem.bytes_read::cpu.inst 216192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9265152 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9481344 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 216192 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 216192 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6247552 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6247552 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3378 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 144768 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 148146 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 97618 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 97618 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1081336 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 46341877 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 47423213 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1081336 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1081336 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 31248628 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 31248628 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 31248628 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1081336 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 46341877 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 78671841 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 148147 # Total number of read requests seen
> system.physmem.writeReqs 97618 # Total number of write requests seen
> system.physmem.cpureqs 247832 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 9481344 # Total number of bytes read from memory
> system.physmem.bytesWritten 6247552 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 9481344 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 6247552 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 9166 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 9182 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 9622 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 9866 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 9514 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 9519 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 9403 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 9092 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 9052 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 9254 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 8851 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 9077 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 9220 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 9034 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 9025 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 9210 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 5950 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 6289 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 6482 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 6223 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 6230 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 6032 # Track writes on a per bank basis
71,77c71,77
< system.physmem.perBankWrReqs::9 6195 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 5906 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 6101 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 5980 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 5943 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 6048 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 6101 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::9 6184 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 5908 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 6109 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 5989 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 5940 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 6062 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 6095 # Track writes on a per bank basis
79,80c79,80
< system.physmem.numWrRetry 1837 # Number of times wr buffer was full causing retry
< system.physmem.totGap 199959894000 # Total gap between requests
---
> system.physmem.numWrRetry 2058 # Number of times wr buffer was full causing retry
> system.physmem.totGap 199930425500 # Total gap between requests
87,113c87,100
< system.physmem.readPktSize::6 148088 # Categorize read packet sizes
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 99440 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 6 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 138077 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 9290 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
---
> system.physmem.readPktSize::6 148147 # Categorize read packet sizes
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 97618 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 137980 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 9444 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
140,149c127,135
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 4198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4220 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4225 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 4231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 4235 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 4208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 4232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 4234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 4234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 4234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 4234 # What write queue length does an incoming req see
155,166c141,152
< system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 37 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
168,179c154,164
< system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 1699469983 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 4970281233 # Sum of mem lat for all requests
< system.physmem.totBusLat 740055000 # Total cycles spent in databus access
< system.physmem.totBankLat 2530756250 # Total cycles spent in bank access
< system.physmem.avgQLat 11482.05 # Average queueing delay per request
< system.physmem.avgBankLat 17098.43 # Average bank access latency per request
---
> system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
> system.physmem.totQLat 1712037750 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 4981606500 # Sum of mem lat for all requests
> system.physmem.totBusLat 740435000 # Total cycles spent in databus access
> system.physmem.totBankLat 2529133750 # Total cycles spent in bank access
> system.physmem.avgQLat 11561.03 # Average queueing delay per request
> system.physmem.avgBankLat 17078.70 # Average bank access latency per request
181,185c166,170
< system.physmem.avgMemAccLat 33580.49 # Average memory access latency
< system.physmem.avgRdBW 47.40 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 31.24 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 47.40 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 31.24 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 33639.73 # Average memory access latency
> system.physmem.avgRdBW 47.42 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 47.42 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s
189,199c174,184
< system.physmem.avgWrQLen 8.80 # Average write queue length over time
< system.physmem.readRowHits 125322 # Number of row buffer hits during reads
< system.physmem.writeRowHits 52822 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 54.12 # Row buffer hit rate for writes
< system.physmem.avgGap 813867.39 # Average gap between requests
< system.cpu.branchPred.lookups 182791909 # Number of BP lookups
< system.cpu.branchPred.condPredicted 143104920 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 7263448 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 93100856 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 87211306 # Number of BTB hits
---
> system.physmem.avgWrQLen 8.71 # Average write queue length over time
> system.physmem.readRowHits 125393 # Number of row buffer hits during reads
> system.physmem.writeRowHits 52794 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 54.08 # Row buffer hit rate for writes
> system.physmem.avgGap 813502.43 # Average gap between requests
> system.cpu.branchPred.lookups 182807672 # Number of BP lookups
> system.cpu.branchPred.condPredicted 143119940 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 7265200 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 92612738 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 87226650 # Number of BTB hits
201,203c186,188
< system.cpu.branchPred.BTBHitPct 93.674011 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 12676660 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 116192 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 94.184290 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 12677704 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 116304 # Number of incorrect RAS predictions.
247c232
< system.cpu.numCycles 399919840 # number of cpu cycles simulated
---
> system.cpu.numCycles 399860886 # number of cpu cycles simulated
250,264c235,249
< system.cpu.fetch.icacheStallCycles 119359242 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 761526244 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 182791909 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 99887966 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 170136962 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 35675847 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 75471629 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 114518172 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 2437097 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 392580882 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.175648 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.990337 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 119358222 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 761608008 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 182807672 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 99904354 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 170147877 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 35680811 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 75396284 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 468 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 114514342 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 2439022 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 392517505 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.176152 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.990501 # Number of instructions fetched each cycle (Total)
266,274c251,259
< system.cpu.fetch.rateDist::0 222456572 56.67% 56.67% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 14184957 3.61% 60.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 22893267 5.83% 66.11% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 22743461 5.79% 71.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 20901253 5.32% 77.23% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 11599327 2.95% 80.18% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 13055185 3.33% 83.51% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 11991563 3.05% 86.56% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 52755297 13.44% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 222382247 56.66% 56.66% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 14190044 3.62% 60.27% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 22888927 5.83% 66.10% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 22740218 5.79% 71.90% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 20908888 5.33% 77.22% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 11594217 2.95% 80.18% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 13063164 3.33% 83.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 11994936 3.06% 86.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 52754864 13.44% 100.00% # Number of instructions fetched each cycle (Total)
278,304c263,289
< system.cpu.fetch.rateDist::total 392580882 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.457071 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.904197 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 129017942 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 70989640 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 158833179 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 6202041 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 27538080 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 26128135 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 77010 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 825507648 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 295471 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 27538080 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 135602175 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 9653631 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 46459749 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 158272352 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 15054895 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 800579867 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 1059 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 3045560 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 8808243 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 238 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 954266949 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 3500439750 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 3500438390 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 392517505 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.457178 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.904682 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 129005298 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 70927026 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 158858538 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 6186097 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 27540546 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 26127343 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 76683 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 825553021 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 296390 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 27540546 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 135586345 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 9628782 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 46469860 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 158285767 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 15006205 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 800628342 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 1130 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 3045894 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 8758928 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 294 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 954382842 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 3500628672 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 3500627387 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1285 # Number of floating rename lookups
306,323c291,308
< system.cpu.rename.UndoneMaps 288014658 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 2292979 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2292975 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 41576680 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 170252258 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 73485876 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 28570132 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 15813364 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 755065776 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 3775319 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 665331498 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 1369025 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 187382058 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 479835806 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 797687 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 392580882 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.694763 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.735550 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 288130551 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 2292970 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 41448640 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 170247105 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 73473871 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 28488219 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 15923707 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 755060750 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 3775315 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 665323167 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 1373619 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 187375419 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 479909972 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 797683 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 392517505 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.695015 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.735938 # Number of insts issued each cycle
325,333c310,318
< system.cpu.iq.issued_per_cycle::0 137175345 34.94% 34.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 69848009 17.79% 52.73% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 71421264 18.19% 70.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 53409606 13.60% 84.53% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 31213744 7.95% 92.48% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 16052398 4.09% 96.57% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 8748856 2.23% 98.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 2891239 0.74% 99.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 1820421 0.46% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 137188203 34.95% 34.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 69757763 17.77% 52.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 71444239 18.20% 70.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 53382766 13.60% 84.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 31199092 7.95% 92.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 16084863 4.10% 96.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 8731670 2.22% 98.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 2913347 0.74% 99.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 1815562 0.46% 100.00% # Number of insts issued each cycle
337c322
< system.cpu.iq.issued_per_cycle::total 392580882 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 392517505 # Number of insts issued each cycle
339,369c324,354
< system.cpu.iq.fu_full::IntAlu 477908 5.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 6514153 68.18% 73.18% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 2562402 26.82% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 478854 5.03% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 6518035 68.44% 73.47% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 2526744 26.53% 100.00% # attempts to use FU when none available
373,374c358,359
< system.cpu.iq.FU_type_0::IntAlu 447790588 67.30% 67.30% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 383397 0.06% 67.36% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 447790300 67.30% 67.30% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 383235 0.06% 67.36% # Type of FU issued
376c361
< system.cpu.iq.FU_type_0::FloatAdd 96 0.00% 67.36% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued
402,403c387,388
< system.cpu.iq.FU_type_0::MemRead 153366793 23.05% 90.41% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 63790621 9.59% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 153391187 23.06% 90.42% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 63758352 9.58% 100.00% # Type of FU issued
406,414c391,399
< system.cpu.iq.FU_type_0::total 665331498 # Type of FU issued
< system.cpu.iq.rate 1.663662 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 9554463 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.014360 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1734167139 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 947029128 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 646060992 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes
---
> system.cpu.iq.FU_type_0::total 665323167 # Type of FU issued
> system.cpu.iq.rate 1.663887 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 9523633 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.014314 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1734060876 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 947018314 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 646045006 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes
416,418c401,403
< system.cpu.iq.int_alu_accesses 674885846 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 115 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 8559648 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_alu_accesses 674846691 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 8570702 # Number of loads that had data forwarded from stores
420,423c405,408
< system.cpu.iew.lsq.thread0.squashedLoads 44222703 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 810061 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 16625399 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 44217550 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 42225 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 810789 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 16613394 # Number of stores squashed
426,427c411,412
< system.cpu.iew.lsq.thread0.rescheduledLoads 19536 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 4374 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 19530 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 4440 # Number of times an access to memory failed due to the cache being blocked
429,445c414,430
< system.cpu.iew.iewSquashCycles 27538080 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 5027706 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 374233 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 760399793 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1113000 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 170252258 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 73485876 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 2286777 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 218846 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 12338 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 810061 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 4335774 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 4000856 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 8336630 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 655910156 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 150087379 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 9421342 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 27540546 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 5027645 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 374127 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 760395240 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 1110246 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 170247105 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 73473871 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 2286773 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 218357 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 11618 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 810789 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4336068 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 4004006 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 8340074 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 655902697 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 150107572 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 9420470 # Number of squashed instructions skipped in execute
447,455c432,440
< system.cpu.iew.exec_nop 1558698 # number of nop insts executed
< system.cpu.iew.exec_refs 212584480 # number of memory reference insts executed
< system.cpu.iew.exec_branches 138500041 # Number of branches executed
< system.cpu.iew.exec_stores 62497101 # Number of stores executed
< system.cpu.iew.exec_rate 1.640104 # Inst execution rate
< system.cpu.iew.wb_sent 651032473 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 646061008 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 374768785 # num instructions producing a value
< system.cpu.iew.wb_consumers 646479955 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 1559175 # number of nop insts executed
> system.cpu.iew.exec_refs 212574642 # number of memory reference insts executed
> system.cpu.iew.exec_branches 138502057 # Number of branches executed
> system.cpu.iew.exec_stores 62467070 # Number of stores executed
> system.cpu.iew.exec_rate 1.640327 # Inst execution rate
> system.cpu.iew.wb_sent 651021062 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 646045022 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 374765758 # num instructions producing a value
> system.cpu.iew.wb_consumers 646459860 # num instructions consuming a value
457,458c442,443
< system.cpu.iew.wb_rate 1.615476 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.579707 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.615674 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.579720 # average fanout of values written-back
460c445
< system.cpu.commit.commitSquashedInsts 189458167 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 189453742 # The number of squashed insts skipped by commit
462,465c447,450
< system.cpu.commit.branchMispredicts 7189194 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 365042802 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.564113 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.233409 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 7191165 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 364976959 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.564395 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.233817 # Number of insts commited each cycle
467,475c452,460
< system.cpu.commit.committed_per_cycle::0 157342257 43.10% 43.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 98505195 26.98% 70.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 33835922 9.27% 79.36% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 18767828 5.14% 84.50% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 16196095 4.44% 88.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 7449740 2.04% 90.97% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 6969572 1.91% 92.88% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 3172412 0.87% 93.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 22803781 6.25% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 157310366 43.10% 43.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 98490082 26.99% 70.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 33805907 9.26% 79.35% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 18787402 5.15% 84.50% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 16180614 4.43% 88.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 7431287 2.04% 90.97% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 6987633 1.91% 92.88% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 3169968 0.87% 93.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 22813700 6.25% 100.00% # Number of insts commited each cycle
479c464
< system.cpu.commit.committed_per_cycle::total 365042802 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 364976959 # Number of insts commited each cycle
490c475
< system.cpu.commit.bw_lim_events 22803781 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 22813700 # number cycles where commit BW limit reached
492,495c477,480
< system.cpu.rob.rob_reads 1102658217 # The number of ROB reads
< system.cpu.rob.rob_writes 1548511592 # The number of ROB writes
< system.cpu.timesIdled 308911 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 7338958 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 1102578030 # The number of ROB reads
> system.cpu.rob.rob_writes 1548505178 # The number of ROB writes
> system.cpu.timesIdled 308567 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 7343381 # Total number of cycles that the CPU has spent unscheduled due to idling
499,504c484,489
< system.cpu.cpi 0.791548 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.791548 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.263347 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.263347 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 3058721385 # number of integer regfile reads
< system.cpu.int_regfile_writes 752002162 # number of integer regfile writes
---
> system.cpu.cpi 0.791431 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.791431 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.263534 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.263534 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 3058706465 # number of integer regfile reads
> system.cpu.int_regfile_writes 752037507 # number of integer regfile writes
506c491
< system.cpu.misc_regfile_reads 210835812 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 210820275 # number of misc regfile reads
508,512c493,497
< system.cpu.icache.replacements 15017 # number of replacements
< system.cpu.icache.tagsinuse 1100.275071 # Cycle average of tags in use
< system.cpu.icache.total_refs 114497128 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 16875 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 6785.014993 # Average number of references to valid blocks.
---
> system.cpu.icache.replacements 15019 # number of replacements
> system.cpu.icache.tagsinuse 1100.569602 # Cycle average of tags in use
> system.cpu.icache.total_refs 114493231 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 16877 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 6783.980032 # Average number of references to valid blocks.
514,540c499,525
< system.cpu.icache.occ_blocks::cpu.inst 1100.275071 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.537244 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.537244 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 114497128 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 114497128 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 114497128 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 114497128 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 114497128 # number of overall hits
< system.cpu.icache.overall_hits::total 114497128 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 21044 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 21044 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 21044 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 21044 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 21044 # number of overall misses
< system.cpu.icache.overall_misses::total 21044 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 498168000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 498168000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 498168000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 498168000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 498168000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 498168000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 114518172 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 114518172 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 114518172 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 114518172 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 114518172 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 114518172 # number of overall (read+write) accesses
---
> system.cpu.icache.occ_blocks::cpu.inst 1100.569602 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.537388 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.537388 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 114493231 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 114493231 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 114493231 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 114493231 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 114493231 # number of overall hits
> system.cpu.icache.overall_hits::total 114493231 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 21111 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 21111 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 21111 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 21111 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 21111 # number of overall misses
> system.cpu.icache.overall_misses::total 21111 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 514757500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 514757500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 514757500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 514757500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 514757500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 514757500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 114514342 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 114514342 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 114514342 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 114514342 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 114514342 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 114514342 # number of overall (read+write) accesses
547,553c532,538
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23672.685801 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 23672.685801 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 23672.685801 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 23672.685801 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24383.378334 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 24383.378334 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 24383.378334 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 24383.378334 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked
555c540
< system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
557c542
< system.cpu.icache.avg_blocked_cycles::no_mshrs 38.100000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 88.615385 # average number of cycles each access was blocked
561,578c546,563
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4078 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 4078 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 4078 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 4078 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 4078 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 4078 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16966 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 16966 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 16966 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 16966 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 16966 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 16966 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 370390500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 370390500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 370390500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 370390500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 370390500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 370390500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16958 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 16958 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 16958 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 16958 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 16958 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 16958 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375680500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 375680500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375680500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 375680500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375680500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 375680500 # number of overall MSHR miss cycles
585,590c570,575
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21831.339149 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21831.339149 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22153.585328 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22153.585328 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency
592,682c577,667
< system.cpu.l2cache.replacements 115340 # number of replacements
< system.cpu.l2cache.tagsinuse 27103.357438 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 1781605 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 146589 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 12.153743 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 100678479000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 23035.141201 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 363.560333 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 3704.655904 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.702977 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.011095 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.113057 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.827129 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 13475 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 804570 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 818045 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1111113 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1111113 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 86 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 86 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 247517 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 247517 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 13475 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1052087 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1065562 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 13475 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1052087 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1065562 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3393 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 43422 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 46815 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 101299 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 101299 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 144721 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 148114 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 144721 # number of overall misses
< system.cpu.l2cache.overall_misses::total 148114 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 218124500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2897532500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3115657000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5229658000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5229658000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 218124500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8127190500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8345315000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 218124500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8127190500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8345315000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 16868 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 847992 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 864860 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1111113 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1111113 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 92 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 348816 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 348816 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 16868 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1196808 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1213676 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 16868 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1196808 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1213676 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201150 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051206 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.054130 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.065217 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.065217 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290408 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.290408 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201150 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.120922 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.122038 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201150 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.120922 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.122038 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64286.619511 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66729.595597 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 66552.536580 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51625.958795 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51625.958795 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64286.619511 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56157.644709 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 56343.863511 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64286.619511 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56157.644709 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 56343.863511 # average overall miss latency
---
> system.cpu.l2cache.replacements 115398 # number of replacements
> system.cpu.l2cache.tagsinuse 27101.777399 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 1781753 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 146655 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 12.149282 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 100667210000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 23032.613766 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 362.003835 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 3707.159797 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.702900 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.011047 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.113134 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.827081 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 13488 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 804399 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 817887 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1110977 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1110977 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 73 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 73 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 247537 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 247537 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 13488 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1051936 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1065424 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 13488 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1051936 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1065424 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3382 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 43478 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 46860 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 101314 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 101314 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 144792 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 148174 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 144792 # number of overall misses
> system.cpu.l2cache.overall_misses::total 148174 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223286000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2917634500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3140920500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5217385000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5217385000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 223286000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8135019500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8358305500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 223286000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8135019500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8358305500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 16870 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 847877 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 864747 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1110977 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1110977 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 348851 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 348851 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 16870 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1196728 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1213598 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 16870 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1196728 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1213598 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200474 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051279 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.054189 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109756 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109756 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290422 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.290422 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200474 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.120990 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.122095 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200474 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.120990 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.122095 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66021.880544 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67105.996136 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67027.752881 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51497.177093 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51497.177093 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66021.880544 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56184.177993 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 56408.718804 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66021.880544 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56184.177993 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 56408.718804 # average overall miss latency
691,743c676,728
< system.cpu.l2cache.writebacks::writebacks 97603 # number of writebacks
< system.cpu.l2cache.writebacks::total 97603 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43401 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 46789 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101299 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 101299 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 144700 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 148088 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3388 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 144700 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 148088 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175595014 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2357208396 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2532803410 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 60006 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 60006 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3964657000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3964657000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175595014 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6321865396 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6497460410 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175595014 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6321865396 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6497460410 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051181 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054100 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.065217 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.065217 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290408 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290408 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.122016 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.122016 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51828.516529 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54312.306076 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54132.454423 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.writebacks::writebacks 97618 # number of writebacks
> system.cpu.l2cache.writebacks::total 97618 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43455 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 46833 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101314 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 101314 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 144769 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 148147 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 144769 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 148147 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180723170 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2376770410 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2557493580 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3952267092 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3952267092 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180723170 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6329037502 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6509760672 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180723170 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6329037502 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6509760672 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051252 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054158 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.109756 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.109756 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290422 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290422 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.122073 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.122073 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53500.050326 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54694.981245 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.792518 # average ReadReq mshr miss latency
746,753c731,738
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39138.165234 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39138.165234 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39010.078489 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39010.078489 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency
755,759c740,744
< system.cpu.dcache.replacements 1192712 # number of replacements
< system.cpu.dcache.tagsinuse 4058.214665 # Cycle average of tags in use
< system.cpu.dcache.total_refs 190183804 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1196808 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 158.909202 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1192631 # number of replacements
> system.cpu.dcache.tagsinuse 4058.209057 # Cycle average of tags in use
> system.cpu.dcache.total_refs 190187917 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1196727 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 158.923394 # Average number of references to valid blocks.
761,769c746,754
< system.cpu.dcache.occ_blocks::cpu.data 4058.214665 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.990775 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.990775 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 136214217 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 136214217 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 50991947 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 50991947 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488812 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 1488812 # number of LoadLockedReq hits
---
> system.cpu.dcache.occ_blocks::cpu.data 4058.209057 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.990774 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.990774 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 136218647 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 136218647 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 50991635 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 50991635 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488827 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 1488827 # number of LoadLockedReq hits
772,779c757,764
< system.cpu.dcache.demand_hits::cpu.data 187206164 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 187206164 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 187206164 # number of overall hits
< system.cpu.dcache.overall_hits::total 187206164 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1696297 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1696297 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3247359 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3247359 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 187210282 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 187210282 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 187210282 # number of overall hits
> system.cpu.dcache.overall_hits::total 187210282 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1699163 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1699163 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3247671 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3247671 # number of WriteReq misses
782,797c767,782
< system.cpu.dcache.demand_misses::cpu.data 4943656 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4943656 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4943656 # number of overall misses
< system.cpu.dcache.overall_misses::total 4943656 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 26545297500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 26545297500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 57237294950 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 57237294950 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 659000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 659000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 83782592450 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 83782592450 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 83782592450 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 83782592450 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 137910514 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 137910514 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 4946834 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4946834 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4946834 # number of overall misses
> system.cpu.dcache.overall_misses::total 4946834 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 26685574500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 26685574500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 57046648448 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 57046648448 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 615500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 615500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 83732222948 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 83732222948 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 83732222948 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 83732222948 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 137917810 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 137917810 # number of ReadReq accesses(hits+misses)
800,801c785,786
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488853 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 1488853 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488868 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 1488868 # number of LoadLockedReq accesses(hits+misses)
804,811c789,796
< system.cpu.dcache.demand_accesses::cpu.data 192149820 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 192149820 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 192149820 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 192149820 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012300 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.012300 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059871 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.059871 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 192157116 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 192157116 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 192157116 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 192157116 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012320 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.012320 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses
814,833c799,818
< system.cpu.dcache.demand_miss_rate::cpu.data 0.025728 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.025728 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.025728 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.025728 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15648.968017 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15648.968017 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17625.798364 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 17625.798364 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16073.170732 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16073.170732 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 16947.496438 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 16947.496438 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 18139 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 17902 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1666 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 610 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.887755 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 29.347541 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15705.129231 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15705.129231 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17565.402545 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 17565.402545 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15012.195122 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15012.195122 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 16926.426670 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 16926.426670 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 18054 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 15751 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 1658 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 601 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.889023 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 26.207987 # average number of cycles each access was blocked
836,841c821,826
< system.cpu.dcache.writebacks::writebacks 1111113 # number of writebacks
< system.cpu.dcache.writebacks::total 1111113 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847762 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 847762 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898994 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2898994 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 1110977 # number of writebacks
> system.cpu.dcache.writebacks::total 1110977 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850754 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 850754 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899270 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2899270 # number of WriteReq MSHR hits
844,865c829,850
< system.cpu.dcache.demand_mshr_hits::cpu.data 3746756 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3746756 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3746756 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3746756 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848535 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 848535 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348365 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 348365 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1196900 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1196900 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1196900 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1196900 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11831456500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 11831456500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8103165495 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8103165495 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19934621995 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 19934621995 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19934621995 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 19934621995 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006153 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006153 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 3750024 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3750024 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3750024 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3750024 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848409 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 848409 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348401 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 348401 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1196810 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1196810 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1196810 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1196810 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11849237000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 11849237000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8091181496 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8091181496 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19940418496 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 19940418496 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19940418496 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 19940418496 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses
868,879c853,864
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.392435 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.392435 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23260.561466 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23260.561466 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13966.420677 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13966.420677 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23223.760827 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23223.760827 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency